JP6448704B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device having a lateral element.

  A lateral high voltage MOS (Lateral Diffused Metal Oxide Semiconductor: LDMOS) transistor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2011-3608 (Patent Document 1).

In the semiconductor device described in this publication, ap ⁺ buried region formed between the n ⁺ buried region and the p ⁻ epitaxial region is formed. This p ⁺ buried region has a higher p-type impurity concentration than the p ⁻ epitaxial region. As a result, the occurrence of punch-through is suppressed and the withstand voltage is kept high.

In the semiconductor device described in the above publication, the p ⁻ epitaxial region has a lower p-type impurity concentration than the p-type body region. Thus, in the breakdown state, a depletion layer spreads from the pn junction between the n-type drift region and the p ⁻ epitaxial region to the p ⁻ epitaxial region side, and a high breakdown voltage can be achieved.

JP 2011-3608 A

  According to the semiconductor device described in the above publication, the breakdown voltage can be improved in the LDMOS transistor. However, there is room for further improvement in order to provide a semiconductor device having more excellent element characteristics.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the semiconductor device in one embodiment, the semiconductor substrate has a main surface, and has a first recess and a second recess on the main surface. The element isolation insulating film is formed in each of the first recess and the second recess. The pair of impurity regions is one of a pair of source / drain regions and a pair of emitter / collector regions formed so as to sandwich the first recess and the second recess on the main surface. One region of the pair of impurity regions is the first conductivity type. The first region of the second conductivity type is a channel forming region formed on the main surface between the one region and the first recess. The gate electrode layer is formed on the first region with a gate insulating film interposed therebetween, and extends at least on the element isolation insulating film in the first recess. The first concave portion and the second concave portion are arranged so as to be adjacent to each other with the substrate convex portion protruding to the main surface side from the bottom portion of each of the first concave portion and the second concave portion. The semiconductor substrate further includes a third concave portion located on the substrate convex portion, and the third concave portion is formed shallower than the first concave portion and the second concave portion.

  According to the semiconductor device in one embodiment, a semiconductor device having more excellent element characteristics can be realized.

1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment. It is sectional drawing which shows schematically the structure which follows the II-II line | wire of FIG. It is sectional drawing which shows schematically the structure of the semiconductor device in a comparative example. FIG. 4 is a diagram showing a change in on-breakdown voltage when the gate overlap amount GF is changed in each configuration of FIG. 2 and FIG. 3. FIG. 4 is a diagram showing a change in on-resistance when the gate overlap amount GF is changed in each configuration of FIG. 2 and FIG. 3. It is a figure which shows the change of an off-breakdown pressure when the gate overlap amount GF is changed in each structure of FIG. 2 and FIG. It is a figure which shows the potential in the ON operation | movement with the structure of FIG. It is a figure which shows the potential in the ON operation | movement with the structure of FIG. FIG. 11 is a plan view schematically showing a modification of the configuration of the semiconductor device in the first embodiment. FIG. 11 is a plan view schematically showing another modification of the configuration of the semiconductor device in the first embodiment. FIG. 10 is a plan view schematically showing still another modification of the configuration of the semiconductor device in the first embodiment. FIG. 6 is a cross sectional view schematically showing a configuration of a semiconductor device in a second embodiment. FIG. 10 is a cross sectional view schematically showing a modification of the configuration of the semiconductor device in the second embodiment. FIG. 14 is a diagram showing a change in ON breakdown voltage when the gate overlap amount GF is changed in each of the configurations of FIGS. 2, 3, 12, and 13. It is a figure which shows the change of ON resistance when the gate overlap amount GF is changed in each structure of FIG.2, FIG.3, FIG.12 and FIG. FIG. 14 is a diagram showing a change in off breakdown voltage when the gate overlap amount GF is changed in each of the configurations of FIGS. 2, 3, 12, and 13. It is a figure which shows the potential in the ON operation | movement with the structure of FIG. It is a top view which shows roughly the planar shape of the structure of FIG. It is a top view which shows roughly the modification of the planar shape of the structure of FIG. It is a top view which shows roughly the other modification of the planar shape of the structure of FIG. FIG. 13 is a plan view schematically showing still another modification of the planar shape of the configuration of FIG. 12. FIG. 13 is a plan view schematically showing still another modification of the planar shape of the configuration of FIG. 12. It is a top view which shows roughly the planar shape of the structure where both a p-type area | region and an n-type area | region coexist in the active region between element isolation insulating films. It is a top view which shows roughly the modification of the planar shape of the structure where both a p-type area | region and an n-type area | region coexist in the active region between element isolation insulating films. It is a top view which shows roughly the other modification of the planar shape of a structure where both the p-type area | region and n-type area | region are mixed in the active region between element isolation insulating films. It is a top view which shows roughly the further another modification of the planar shape of the structure where both a p-type area | region and an n-type area | region coexist in the active region between element isolation insulating films. FIG. 10 is a cross sectional view schematically showing a configuration of a semiconductor device in a third embodiment. FIG. 10 is a cross sectional view schematically showing a modification of the configuration of the semiconductor device in the third embodiment. It is a top view which shows roughly the planar shape of the structure of FIG. It is a top view which shows roughly the modification of the planar shape of the structure of FIG. It is a top view which shows roughly the other modification of the planar shape of the structure of FIG. FIG. 28 is a plan view schematically showing still another modification of the planar shape of the configuration of FIG. 27. FIG. 28 is a plan view schematically showing still another modification of the planar shape of the configuration of FIG. 27. FIG. 10 is a cross sectional view schematically showing a configuration of a semiconductor device in a fourth embodiment. It is sectional drawing which shows roughly the structure which applied the structure of Embodiment 1 to IGBT. 1 is a cross-sectional view schematically showing a configuration in which the configuration of Embodiment 1 is applied to a bidirectional transistor. FIG. 3 is a cross-sectional view schematically showing a configuration in which the configuration of the first embodiment is applied to LOCOS. 3 is a cross-sectional view schematically showing a configuration in which an element isolation insulating film is formed on a substrate convex portion in the configuration of the first embodiment. FIG. It is a figure which shows the change of ON breakdown voltage when the depth D of recessed part CP4 is changed in the structure of this modification shown in FIG. It is a figure which shows the change of ON resistance when the depth D of recessed part CP4 is changed in the structure of this modification shown in FIG. It is a figure which shows the change of an off-breakdown pressure when the depth D of recessed part CP4 is changed in the structure of this modification shown in FIG.

Hereinafter, embodiments will be described with reference to the drawings.
(Embodiment 1)
Referring to FIGS. 1 and 2, the semiconductor device of the present embodiment has, for example, LDMOS transistor TR. This semiconductor device includes a semiconductor substrate SUB, an n-type buried layer BL, a p ⁻ epitaxial region EP, an n-type drift region DRI, a p-type well region WL, and an n ⁺ source region SR (one of a pair of impurity regions). Region), n ⁺ drain region DR (the other region of the pair of impurity regions), p ⁺ contact region CO, gate insulating film GI, gate electrode layer GE, element isolation structure, and conductive layer CL. Have.

Referring mainly to FIG. 2, semiconductor substrate SUB is made of, for example, silicon. The semiconductor substrate SUB has a main surface (upper surface in the drawing). An n-type buried layer BL is formed inside the semiconductor substrate SUB. A p ⁻ epitaxial region EP is formed in the semiconductor substrate SUB on the main surface side of the n-type buried layer BL so as to form a pn junction with the n-type buried layer BL.

An n-type drift region DRI and a p-type well region WL are formed in the semiconductor substrate SUB on the main surface side of the p ⁻ epitaxial region EP. This n-type drift region DRI forms a pn junction extending in the direction along the main surface with p ⁻ epitaxial region EP. p-type well region WL is, p ^- is formed in contact with the epitaxial region EP, p ^- has a higher p-type impurity concentration than the epitaxial region EP.

  The element isolation structure has, for example, an STI (Shallow Trench Isolation) structure. The element isolation structure of this STI structure has recesses CP1, CP2, CP and an element isolation insulating film SI. Each of the recesses CP1, CP2, CP is formed on the main surface of the semiconductor substrate SUB. The element isolation insulating film SI is formed so as to be embedded in each of the recesses CP1, CP2, and CP.

  The concave portion CP1 (first concave portion) and the concave portion CP2 (second concave portion) are formed on the main surface in the n-type drift region DRI and are formed shallower than the n-type drift region DRI.

N ⁺ drain region DR is formed on the main surface of semiconductor substrate SUB so as to be in contact with n-type drift region DRI, and has an n-type impurity concentration higher than that of n-type drift region DRI. The n ⁺ source region SR is formed on the main surface of the semiconductor substrate SUB in the p-type well region WL so as to form a pn junction with the p-type well region WL.

On the main surface of semiconductor substrate SUB, n ⁺ drain region DR and n ⁺ source region SR are arranged so as to sandwich recesses CP1 and CP2. On the main surface of semiconductor substrate SUB, n ⁺ drain region DR is in contact with recess CP2.

On the main surface of semiconductor substrate SUB, p type well region WL and p ⁻ epitaxial region EP are arranged between n ⁺ source region SR and recess CP1. Of the p-type well region WL and the p ⁻ epitaxial region EP sandwiched between the n ⁺ source region SR and the recess CP1, the portion located on the main surface of the semiconductor substrate SUB becomes a channel formation region (first region). Part. On the main surface of semiconductor substrate SUB, p ⁺ contact region CO is formed adjacent to n ⁺ source region SR.

Gate electrode layer GE is formed on a channel formation region (p-type well region WL and p ⁻ epitaxial region EP) sandwiched between n ⁺ source region SR and recess CP1 with a gate insulating film GI interposed therebetween. ing. A part of the gate electrode layer GE is located on a part of the n-type drift region DRI with the gate insulating film GI interposed therebetween, and runs on the element isolation insulating film SI filling the recess CP1. .

A conductive layer CL serving as a drain electrode is formed on the main surface of the semiconductor substrate SUB so as to be electrically connected to the n ⁺ drain region DR. A conductive layer CL serving as a source electrode is formed on the main surface of semiconductor substrate SUB so as to be electrically connected to n ⁺ source region SR. A conductive layer CL is formed on the main surface of the semiconductor substrate SUB so as to be electrically connected to the p ⁺ contact region CO.

  In the above configuration, on the main surface of the semiconductor substrate SUB, the concave portion CP1 and the concave portion CP2 sandwich the substrate convex portion CV protruding to the main surface side (upper side in the drawing) from the bottom portions of the concave portion CP1 and the concave portion CP2. Are arranged next to each other. The element isolation insulating film SI is not formed on the substrate protrusion CV, and the main surface of the substrate protrusion CV is an active area AA. That is, the concave portion CP1 and the concave portion CP2 are separated on the main surface by the substrate convex portion CV made of the active area AA.

In the present embodiment, n-type drift region DRI is formed on the main surface of active region AA. Therefore, the main surface of active region AA has an n-type impurity concentration lower than the n-type impurity concentration in the main surface of n ⁺ source region SR. In this embodiment, gate electrode layer GE has It does not extend over the active area AA.

The concentration of the n-type impurity in the n-type drift region is, for example, 1 × 10 ¹⁶ cm ⁻³ , and the concentration of each n-type impurity in the n ⁺ source region SR and the n ⁺ drain region DR is, for example, 1 × 10 ¹⁸ cm ^−3. It is.

In the cross section shown in FIG. 2, the LDMOS transistor TR is formed so as to have a line-symmetric configuration with respect to a virtual line AA passing through the n ⁺ drain region DR.

Referring mainly to FIG. 1, recess CP2 is formed as a groove surrounding the entire periphery of n ⁺ drain region DR formed in the main surface of semiconductor substrate SUB in plan view. For this reason, the element isolation insulating film SI filling the recess CP2 is also formed so as to surround the entire periphery of the n ⁺ drain region DR in plan view. The substrate convex portion CV (active area AA) is formed so as to surround the entire outer periphery of the concave portion CP2 in plan view.

  The concave portion CP1 is formed as a groove that surrounds the entire outer periphery of the concave portion CP2 through the substrate convex portion CV (active area AA) in plan view. Therefore, the element isolation insulating film SI filling the recess CP1 is also formed so as to surround the entire outer periphery of the recess CP2 with the substrate protrusion CV (active area AA) interposed therebetween in plan view.

The gate electrode layer GE is formed so as to surround the entire outer periphery of the element isolation insulating film SI embedded in the concave portion CP1 while overlapping with a part of the outer peripheral portion of the element isolation insulating film SI embedded in the concave portion CP1 in plan view. Yes. The n ⁺ source region SR is formed so as to surround the entire outer periphery of the gate electrode layer GE in plan view, and the p ⁺ contact region CO is formed so as to surround the entire outer periphery of the n ⁺ source region SR in plan view. Yes. In plan view, p type well region WL surrounds n type drift region DRI while sandwiching a part of p ⁻ epitaxial region EP on the main surface.

  Next, the results of examining the on-breakdown voltage (Bvon), on-resistance (Rsp), and off-breakdown voltage (Bvoff) of the semiconductor device in this embodiment are shown in FIGS. 4 to 6 in comparison with the comparative example shown in FIG. It explains using.

FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device of a comparative example, and this cross-sectional view shows a portion corresponding to a region R1 in FIG. Referring to FIG. 3, in the semiconductor device of the comparative example, concave portion CP located between n ⁺ source region SR and n + drain region DR is not separated by the active region. Since the configuration of the comparative example other than this is almost the same as the configuration of the present embodiment shown in FIG. 2, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

  Each of FIGS. 4 to 6 shows a dimension GF (a gate overlap amount) in which the element isolation insulating film SI and the gate electrode layer GE filling the recess CP1 (FIG. 2) or the recess CP (FIG. 3) overlap in a plan view. FIG. 2 is a diagram of simulation results showing changes in ON breakdown voltage (Bvon), ON resistance (Rsp), and OFF breakdown voltage (Bvoff) when FIG. 2) is changed. This simulation was performed with each of the STI width of the present embodiment (FIG. 2) and the STI width of the comparative example (FIG. 3) set to 1.7 μm.

  Referring to FIG. 4, it was found that in this embodiment (black squares, white squares, black circles in the figure), the ON breakdown voltage can be improved over the comparative example (white circles in the figure). Moreover, in this Embodiment, it turned out that ON breakdown voltage can be improved, so that the dimension (AA width | variety: FIG. 2) between recessed part CP1 and recessed part CP2 is enlarged.

  Referring to FIG. 5, it was found that the on-resistance can be reduced in the present embodiment (black square, white square, black circle in the figure) as compared with the comparative example (white circle in the figure). Moreover, in this Embodiment, it turned out that ON resistance can be reduced, so that the dimension (AA width | variety: FIG. 2) between recessed part CP1 and recessed part CP2 is enlarged.

  Referring to FIG. 6, it is understood that the present embodiment (black squares, white squares, black circles in the figure) can improve the off breakdown voltage with respect to the comparative example (white circles in the figure) when the gate overlap amount GF increases. It was. For this reason, with regard to the off breakdown voltage, it was found that an off breakdown voltage equal to or higher than that of the comparative example can be obtained in this embodiment by adjusting the gate overlap amount GF.

  Next, the reason why the on-withstand voltage (Bvon), on-resistance (Rsp), and off-withstand voltage (Bvoff) shown in FIGS. 4 to 6 are obtained will be discussed with reference to FIGS. 2, 3, 7, and 8. To do.

On breakdown voltage, a depletion layer from the n ⁺ source region SR side n ⁺ drain region DR side because of the substrate protrusions CV (active region AA) between the recess CP1 and the recess CP2 in this embodiment shown in FIG. 2 This is considered to be an improvement over the comparative example shown in FIG. This can be seen from the comparison of potentials in FIGS. Note that a plurality of curves shown in FIGS. 7 and 8 are contour lines of the potential (potential) in the depletion layer.

That is, in the present embodiment of FIG. 8, since there is the substrate convex portion CV (active area AA) between the concave portion CP1 and the concave portion CP2, the potential contour line enters the substrate convex portion CV (active area AA). . Thereby, in the present embodiment of FIG. 8, the contour lines of the potential are closer to the n ⁺ drain region DR side than the comparative example of FIG. Therefore, in comparison with the comparative example of FIG. 7, in the present embodiment of FIG. 8, the broken line indicating the potential of 40 V in the figure is closer to the n ⁺ drain region DR side, and between the concave portion CP1 and the concave portion CP2. The electric field is relaxed by the substrate convex portion CV (active area AA). Thus, it is considered that the ON breakdown voltage is improved by the electric field relaxation by the substrate convex portion CV (active area AA).

  Further, the on-resistance is such that, as in the present embodiment shown in FIG. 2, the substrate convex portion CV (active region AA) is provided between the concave portion CP1 and the concave portion CP2, so that the region where the current flows is the substrate convex portion CV ( It is considered that the active area AA) is widened and thus decreased.

In addition, in the present embodiment shown in FIG. 2, the off breakdown voltage is considered to be lower than that of the comparative example shown in FIG. 3 because the substrate convex portion CV (active area AA) is present between the concave portion CP1 and the concave portion CP2. . Increasing the gate overlap amount GF in Comparative Example where the electric field is intensive and off-state breakdown voltage is considered that decrease in the n ⁺ drain region DR-side end portion of the concave portion CP in FIG. On the other hand, when the gate overlap amount GF is increased in the present embodiment, the electric field is relaxed by the substrate convex portion CV (active area AA) between the concave portion CP1 and the concave portion CP2 in FIG. It is considered a thing.

  Next, modified examples of the planar structure in plan view of the present embodiment will be described with reference to FIGS.

In FIG. 1, the substrate convex portion CV (active region AA) having the n-type drift region DRI formed on the surface thereof surrounds the entire periphery of the n ⁺ drain region DR in plan view (for example, a rectangular frame in plan view). The shape of the substrate convex portion CV (active region AA) does not have to surround the n ⁺ drain region DR in plan view as shown in FIGS. 9 and 10.

9 and 10, the substrate protrusion CV (active region AA) has a linear shape extending in parallel with the longitudinal direction of the n ⁺ drain region DR (vertical direction in the drawing) in plan view. You may have. In plan view, the length of the linear substrate protrusion CV (active region AA) in the longitudinal direction (vertical direction in the figure) may be longer than the length of the n ⁺ drain region DR in the longitudinal direction. As shown, it may be shorter than the length of the n ⁺ drain region DR in the longitudinal direction.

As shown in FIG. 11, the plurality of substrate protrusions CV (active areas AA) are intermittently arranged along the same direction (vertical direction in the figure) as the longitudinal direction of the n ⁺ drain region DR in plan view. Also good. That is, the element isolation insulating film SI is located between each of the plurality of substrate convex portions CV (active regions AA) arranged along the longitudinal direction of the n ⁺ drain region DR.

  9 to 11 correspond to the configuration shown in FIG. A cross section taken along line III-III in FIG. 11 corresponds to the configuration in FIG.

  In the present embodiment, as shown in FIG. 2, a substrate convex portion CV (active area AA) is arranged between the concave portion CP1 and the concave portion CP2 on the main surface of the semiconductor substrate SUB. For this reason, as shown in FIGS. 4 and 5, it is possible to improve the on-breakdown voltage and reduce the on-resistance as compared with the comparative example (FIG. 3). As shown in FIG. 6, with respect to the off breakdown voltage, an off breakdown voltage equal to or higher than that of the comparative example (FIG. 3) can be obtained in this embodiment by adjusting the gate overlap amount GF.

(Embodiment 2)
Referring to FIG. 12, the configuration of the present embodiment is the surface of substrate convex portion CV (active area AA) between concave portions CP1 and CP2 as compared with the configuration of the first embodiment shown in FIG. The difference is that a p-type impurity region AR (second region) is formed on the (main surface). The p-type impurity region AR is formed shallower than the depth position of the bottom surfaces of the recesses CP1 and CP2. p-type impurity region AR has the same impurity concentration as p ⁺ contact region CO, may be formed in the same step as p ⁺ contact region CO.

  The potential of the p-type impurity region AR is fixed at a floating (floating potential) or GND (ground potential) level. As a method of fixing the p-type impurity region AR to the GND level, a conductive layer (not shown) is connected to the p-type impurity region AR from above the main surface of the semiconductor substrate SUB, and the GND level is interposed via the conductive layer. Can be applied to the p-type impurity region AR.

As another method of fixing the potential of the p-type impurity region AR to the GND level, the p-type impurity region AR may be formed so as to reach the p ⁻ epitaxial region EP as shown in FIG. In this case, the p-type impurity region AR is formed deeper than the depth position of the bottom surfaces of the recesses CP1 and CP2. The p-type impurity region AR has the same impurity concentration as the p-type well region WL, and may be formed in the same process as the p-type well region WL.

  Note that, in the configuration of the present embodiment shown in FIG. 12 and FIG. 13, the configuration other than the above is substantially the same as the configuration of the first embodiment. Do not repeat.

  Next, as a result of examining the on-breakdown voltage (Bvon), on-resistance (Rsp), and off-breakdown voltage (Bvoff) of the semiconductor device in this embodiment, the comparative example shown in FIG. 3 and the first embodiment shown in FIG. This will be described with reference to FIGS.

  Each of FIGS. 14 to 16 shows the ON breakdown voltage when the dimension GF (gate overlap amount: FIG. 2) in which the element isolation insulating film SI and the gate electrode layer GE filling the recess CP1 overlap in plan view is changed. It is a figure of the simulation result which shows the change of Bon), ON resistance (Rsp), and OFF breakdown voltage (Bvoff). In this simulation, each of the STI width of this embodiment (similar to the STI width shown in FIG. 2) and the STI width of the comparative example (FIG. 3) is set to 1.7 μm, and the AA in the first embodiment and this embodiment is used. This was performed with a width of 0.11 μm.

  Referring to FIG. 14, the result in the configuration of FIG. 12 of the present embodiment is indicated by a white triangle in the figure, and the result in the configuration of FIG. 13 of the present embodiment is indicated by a black triangle in the figure. . In the present embodiment (white triangles and black triangles in the figure), it was found that the ON breakdown voltage can be improved as compared with the comparative example in FIG. 3 (white circles in the figure). Further, it has been found that the on-withstand voltage can be improved with the configuration of FIG. 13 of the present embodiment as compared with the configuration of FIG. 12 of the present embodiment.

  Referring to FIG. 15, in the present embodiment (white triangles and black triangles in the figure), the on-resistance is substantially the same as in the comparative example (white circles in FIG. 3) and Embodiment 1 (black circles in the figure). I found out that

  Referring to FIG. 16, the configuration of FIG. 13 of this embodiment (black triangle in the figure) improves the off breakdown voltage with respect to the comparative example of FIG. 3 (white circle in the figure) when the gate overlap amount GF increases. I understood that I could do it. For this reason, with regard to the off breakdown voltage, it was found that an off breakdown voltage equal to or higher than that of the comparative example can be obtained in this embodiment by adjusting the gate overlap amount GF.

  Further, it was found that the configuration of FIG. 12 (white triangles in the figure) of the present embodiment has an off breakdown voltage substantially the same as that of the comparative example of FIG. 3 (white circles in the figure). Further, it was found that if the gate overlap amount GF is adjusted, an off breakdown voltage higher than that of the comparative example can be obtained also in this embodiment.

  Next, the reason why the results of the on breakdown voltage (Bvon), the on resistance (Rsp) and the off breakdown voltage (Bvoff) shown in FIGS. 14 to 16 are obtained will be discussed with reference to FIGS.

The reason why the ON breakdown voltage is improved in the configuration of the present embodiment shown in FIGS. 12 and 13 is the same as the reason described in the first embodiment. That is, in the present embodiment shown in FIGS. 12 and 13, since the substrate convex portion CV (active region AA) is between the concave portion CP1 and the concave portion CP2, the depletion layer is less likely to extend on the n ⁺ drain region DR side. The on-breakdown voltage is considered to be improved over the comparative example. This can be seen from the potential shown in FIG.

Referring to FIG. 17, in the present embodiment, since substrate convex portion CV (active area AA) is provided between concave portion CP1 and concave portion CP2, the potential of the substrate convex portion CV (active area AA) can be reduced. Contour lines enter. Thereby, in the present embodiment of FIG. 17, the contour lines of the potential are closer to the n ⁺ drain region DR side than the comparative example of FIG. Therefore, in comparison with the comparative example of FIG. 7, in the present embodiment of FIG. 17, the broken line indicating the potential of 40 V in the figure is closer to the n ⁺ drain region DR side, and between the concave portion CP1 and the concave portion CP2. It is considered that the electric field is relaxed by the substrate protrusion CV (active area AA) and the on-breakdown voltage is improved.

  Similarly to the first embodiment, the on-resistance is obtained by providing the substrate convex portion CV (active area AA) between the concave portion CP1 and the concave portion CP2 as in the present embodiment shown in FIGS. It is considered that the current flowing region is widened by the substrate convex portion CV (active region AA), so that the current is lowered.

Regarding the off-breakdown voltage, in the present embodiment shown in FIGS. 12 and 13, between the p-type impurity region AR and the n-type drift region DRI formed on the surface of the substrate convex portion CV (active region AA). A pn junction is formed. Therefore, the electric field on the n ⁺ drain region DR side is relaxed, and it is considered that the off breakdown voltage can obtain a breakdown voltage close to that of the comparative example shown in FIG. 3 without changing the gate overlap amount GF.

  Next, modified examples of the planar structure in plan view of the present embodiment will be described with reference to FIGS.

Referring to FIG. 18, in plan view, substrate convex portion CV (active region AA) having p-type impurity region AR formed on the surface may surround the entire periphery of n ⁺ drain region DR and concave portion CP2. . In this configuration, the substrate convex portion CV (active region AA) having the p-type impurity region AR formed on the surface thereof has, for example, a rectangular frame shape in plan view.

Referring to FIGS. 19 and 20, substrate projection CV (active region AA) does not have to surround n ⁺ drain region DR in plan view. In the configurations of FIGS. 19 and 20, the substrate convex portion CV (active region AA) has a linear shape extending in parallel with the longitudinal direction of the n ⁺ drain region DR (vertical direction in the drawing) in plan view. You may have. In plan view, the length of the linear substrate protrusion CV (active region AA) in the longitudinal direction (vertical direction in the figure) is longer than the length of the n ⁺ drain region DR in the longitudinal direction as shown in FIG. Alternatively, as shown in FIG. 20, it may be shorter than the length of the n ⁺ drain region DR in the longitudinal direction.

Further, as shown in FIG. 21, a plurality of substrate protrusions CV (active areas AA) are intermittently arranged in the same direction (vertical direction in the figure) as the longitudinal direction of the n ⁺ drain region DR in plan view. Also good. That is, the element isolation insulating film SI is located between each of the plurality of substrate convex portions CV (active regions AA) arranged along the longitudinal direction of the n ⁺ drain region DR.

  As shown in FIGS. 18 to 21, the gate electrode layer GE may surround the entire periphery of the drain region DR, the substrate protrusion CV (active region AA), and the like in plan view. In this configuration, the gate electrode layer GE has, for example, a rectangular frame shape in plan view.

On the other hand, as shown in FIG. 22, the gate electrode layer GE does not have to surround the entire circumference of the drain region DR, the substrate protrusion CV (active region AA), and the like in plan view. In this configuration, the gate electrode layer GE includes two linear gate electrode portions formed so as to run along the same direction (vertical direction in the drawing) as the longitudinal direction of the n ⁺ drain region DR in plan view. It may be divided into.

The substrate convex portion CV (active region AA) having the p-type impurity region AR formed on the surface surrounds the entire periphery of the n ⁺ drain region DR in plan view and reaches the p-type well region WL on the outer peripheral side. Yes. Thereby, the potential of the p-type impurity region AR can be fixed at the GND level.

  A cross section taken along line XII-XII of FIGS. 19 to 22 corresponds to the configuration of FIG. A cross section taken along line III-III in FIG. 21 corresponds to the configuration in FIG.

As shown in the plan views of FIGS. 23 to 26, the main surface of the substrate convex portion CV (active region AA) has a p-type impurity region AR (second region) and an n-type drift region DRI (third region). May be mixed. As shown in FIG. 23, in plan view, the p-type impurity region AR and the n-type drift are formed along the longitudinal direction on the main surface of the substrate convex portion CV (active region AA) surrounding the entire periphery of the n ⁺ drain region DR. The regions DRI may be formed alternately. Further, as shown in FIGS. 24 and 25, a linear substrate convex portion CV (active region AA) extending so as to run in parallel in the same direction (vertical direction in the drawing) as the longitudinal direction of the n ⁺ drain region DR in plan view. In the main surface, p-type impurity regions AR and n-type drift regions DRI may be alternately formed along the longitudinal direction. Further, as shown in FIG. 26, p is formed on the plurality of substrate convex portions CV (active regions AA) intermittently arranged along the same direction (vertical direction in the drawing) as the longitudinal direction of the n ⁺ drain region DR in plan view. Type impurity regions AR and n type drift regions DRI may be formed alternately.

  23 to 26 correspond to the configuration of FIG. 2, and the cross section along the XII-XII line corresponds to the configuration of FIG.

  According to the present embodiment, as shown in FIGS. 12 and 13, substrate convex portion CV (active area AA) is arranged between concave portion CP <b> 1 and concave portion CP <b> 2 on the main surface of semiconductor substrate SUB. For this reason, as shown in FIGS. 14 and 15, it is possible to reduce the on-resistance while maintaining the on-breakdown voltage as compared with the comparative example (FIG. 3).

  Further, according to the present embodiment, as shown in FIGS. 12 and 13, a pn junction is formed between the p-type impurity region AR and the n-type drift region DRI formed in the substrate convex portion CV (active region AA). Has been. As a result, the electric field on the drain side is relaxed, so that an off breakdown voltage comparable to that of the comparative example can be obtained without adjusting the gate overlap amount GF, and the present embodiment can be achieved by adjusting the gate overlap amount GF. Also in the embodiment, an off breakdown voltage higher than that of the comparative example can be obtained.

(Embodiment 3)
Referring to FIGS. 27 and 28, the configuration of the present embodiment is different from the configuration of the first embodiment shown in FIG. 2 in that substrate convex portion CV (active region AA) between concave portions CP1 and CP2. ) In that an additional conductive layer GE1 is formed through an insulating film GI1. The additional conductive layer GE1 is electrically insulated from the substrate protrusion CV (active area AA) by the insulating film GI1.

  The additional conductive layer GE1 may be electrically insulated from the gate electrode layer GE by being separated from the gate electrode layer GE as shown in FIG. The potential of the additional conductive layer GE1 illustrated in FIG. 27 may be any of floating, GND, drain potential, and gate potential.

  Further, as shown in FIG. 28, the additional conductive layer GE1 may be integrated with the gate electrode layer GE to be electrically connected to the gate electrode layer GE and have the same potential (gate potential).

  27 and 28, the configuration other than the above is substantially the same as the configuration of the first embodiment. Therefore, the same elements are denoted by the same reference numerals and the description thereof is omitted. Do not repeat.

  Next, a modification of the planar structure in plan view of the present embodiment will be described with reference to FIGS.

Referring to FIG. 29, this planar structure has a configuration in which an additional conductive layer GE1 separated from gate electrode layer GE is added to the planar structure of FIG. The additional conductive layer GE1 is formed on the entire substrate protrusion CV (active area AA) in plan view. The additional conductive layer GE1 surrounds the entire periphery of the n ⁺ drain region DR in plan view, and has, for example, a rectangular frame shape.

Referring to FIGS. 30 and 31, these planar structures have a structure in which an additional conductive layer GE1 separated from the gate electrode layer GE is added to the planar structures of FIGS. The additional conductive layer GE1 is formed on the entire substrate protrusion CV (active area AA) in plan view. The additional conductive layer GE1 has a linear shape extending so as to run in parallel in the same direction (vertical direction in the drawing) as the longitudinal direction of the n ⁺ drain region DR in plan view. In plan view, the length in the longitudinal direction (vertical direction in the figure) of the linear additional conductive layer GE1 may be longer than the length in the longitudinal direction of the n ⁺ drain region DR as shown in FIG. As shown at 31, it may be shorter than the length of the n ⁺ drain region DR in the longitudinal direction.

  Referring to FIGS. 32 and 33, these planar structures have a configuration in which an additional conductive layer GE1 separated from the gate electrode layer GE is added to the planar structure of FIG. The additional conductive layer GE1 is formed on the entire substrate protrusion CV (active area AA) in plan view. As shown in FIG. 32, one additional conductive layer GE1 may be disposed over a plurality of substrate convex portions CV (active areas AA) disposed in the longitudinal direction (up and down direction in the drawing) in plan view. . Further, each of the plurality of additional conductive layers GE1 is individually provided on each of the plurality of substrate convex portions CV (active areas AA) arranged in the longitudinal direction (vertical direction in the drawing) in a plan view as shown in FIG. It may be arranged.

  In the configuration of FIG. 27, the off breakdown voltage is improved when the potential of the additional conductive layer GE1 is GND, and the on resistance and the on breakdown voltage are improved when the potential of the additional conductive layer GE1 is the drain voltage. 27 and 28, the on-resistance is improved when the potential of the additional conductive layer GE1 is the gate potential.

(Embodiment 4)
Referring to FIG. 34, the configuration of this embodiment is different from the configuration of Embodiment 1 shown in FIG. 2 in that a plurality of substrate convex portions CV1, CV2 (active region) are provided between concave portions CP1 and CP2. AA1 and AA2) are different in that they are formed. The plurality of substrate convex portions CV1, CV2 (active regions AA1, AA2) are, for example, two substrate convex portions CV1, CV2 (active regions AA1, AA2). The two substrate protrusions CV1, CV2 (active areas AA1, AA2) are separated from each other by the recess CP3. In the recess CP3, an element isolation insulating film SI is embedded as in the recesses CP1 and CP2. The plurality of substrate protrusions CV1, CV2 (active areas AA1, AA2) are not limited to two, and may be three or more.

  Note that, in the configuration of the present embodiment shown in FIG. 34, the configuration other than the above is substantially the same as the configuration of the first embodiment, and therefore the same elements are denoted by the same reference numerals and description thereof is not repeated.

  The same effect as in the first embodiment can be expected even in the configuration in which the plurality of substrate convex portions CV1, CV2 (active regions AA1, AA2) are formed between the concave portion CP1 and the concave portion CP2 as in the present embodiment. .

(Modification 1)
In the above first to fourth embodiments, the LDMOS transistor has been described. However, the configuration in which the substrate convex portions CV, CV1, and CV2 (active regions AA, AA1, and AA2) are formed between the concave portions CP1 and CP2 is as follows. As shown in FIG. 35, the present invention can also be applied to an IGBT (Insulated Gate Bipolar Transistor). Referring to FIG. 35, this IGBT is different from the LDMOS transistor shown in FIG. 2 in that a p ⁺ collector region CR is formed instead of the n ⁺ drain region DR of the transistor, and the LDMOS transistor The difference is that the n ⁺ source region SR functions as the n ⁺ emitter region ER.

  35, the configuration other than the above is substantially the same as the configuration of the LDMOS transistor shown in FIG. 2, and therefore the same elements are denoted by the same reference numerals and description thereof will not be repeated.

(Modification 2)
In the above first to fourth embodiments, the LDMOS transistor has been described. However, the configuration in which the substrate convex portions CV, CV1, and CV2 (active regions AA, AA1, and AA2) are formed between the concave portions CP1 and CP2 is as follows. As shown in FIG. 36, the present invention can also be applied to a lateral bidirectional transistor. Referring to FIG. 36, this lateral bidirectional transistor includes a pair of n-type well regions DRI formed on the main surface of semiconductor substrate SUB and a p-type well formed between the pair of n-type well regions DRI. The region mainly includes a region WL, a pair of impurity regions IP for source / drain regions, a gate insulating film GI, and a gate electrode layer GE.

An n-type buried layer BL is formed inside the semiconductor substrate SUB. A p ⁻ epitaxial region EP is formed in the semiconductor substrate SUB on the main surface side of the n-type buried layer BL so as to form a pn junction with the n-type buried layer.

A pair of n-type well region DRI and p-type well region WL are formed in semiconductor substrate SUB and on the main surface side of p ⁻ epitaxial region EP. This n-type well region DRI forms a pn junction extending in the direction along the main surface with p ⁻ epitaxial region EP2. p-type well region WL is so positioned between the pair of n-type well region DRI, and p ^- is formed in contact with the epitaxial region EP, p ^- have a high p-type impurity concentration than the epitaxial region EP doing.

  An element isolation structure having, for example, an STI structure is formed on the main surface of the semiconductor substrate SUB. The element isolation structure of this STI structure has recesses CP1, CP2, CP and an element isolation insulating film SI. Each of the recesses CP1, CP2, CP is formed on the main surface of the semiconductor substrate SUB. The element isolation insulating film SI is formed so as to be embedded in each of the recesses CP1, CP2, and CP.

  The concave portion CP1 (first concave portion), the concave portion CP2 (second concave portion), and the concave portion CP are formed on the main surface in the n-type well region DRI and are formed shallower than the n-type well region DRI.

  Each of the pair of source / drain region impurity regions IP is formed on the main surface of the semiconductor substrate SUB sandwiched between the recesses CP2 and CP, and has an n-type impurity concentration higher than that of the n-type drift region DRI. ing.

  The gate electrode layer GE is formed on the p-type well region WL sandwiched between the pair of n-type well regions DRI with the gate insulating film GI interposed therebetween. A part of the gate electrode layer GE runs over the element isolation insulating film SI filling the recess CP1. A conductive layer CL serving as an electrode is formed on the main surface of the semiconductor substrate SUB so as to be electrically connected to each of the pair of impurity regions IP for the source / drain regions.

  In the above configuration, the substrate convex portion CV is disposed between the concave portion CP1 and the concave portion CP2 on the main surface of the semiconductor substrate SUB. The element isolation insulating film SI is not formed on the substrate protrusion CV, and the main surface of the substrate protrusion CV is an active area AA. That is, the concave portion CP1 and the concave portion CP2 are separated on the main surface by the active region AA. In the present embodiment, an n-type well region DRI is formed on the main surface of this active region AA. In the present embodiment, the gate electrode layer GE does not extend over the active region AA.

  Also in the above-described lateral bidirectional transistor, the same operational effects as in the first to fourth embodiments can be obtained.

(Modification 3)
In the above description, the STI structure is described as the element isolation structure. However, as shown in FIG. 37, the element isolation insulating film SI may be formed of a silicon oxide film formed by a LOCOS (LOCal Oxidation of Silicon) method.

  37 other than the above is substantially the same as the configuration shown in FIG. 2, and therefore, the same components are denoted by the same reference numerals and description thereof is not repeated.

  Even when a silicon oxide film formed by the LOCOS method is used as the element isolation structure, the same effects as those of the first to fourth embodiments can be obtained.

(Modification 4)
In the above description, the element isolation insulating film SI is not formed on the substrate protrusion CV and the active region AA is described. However, as shown in FIG. 38, the element isolation insulation is formed on the substrate protrusion CV. A film SI may be formed. Specifically, the concave portion CP4 formed on the substrate convex portion CV is formed shallower than the concave portions CP1 and CP2, thereby forming the substrate convex portion CV between the concave portion CP1 and the concave portion CP2.

  38 other than the above is substantially the same as the configuration shown in FIG. 2, and therefore, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.

  Next, the results of examining the on-breakdown voltage (Bvon), on-resistance (Rsp), and off-breakdown voltage (Bvoff) when the depth D of the recess CP4 is changed in the configuration of the present modification shown in FIG. This will be described with reference to FIG.

  39 to 41, the STI width of the present embodiment (FIG. 2) and the STI width of the comparative example (FIG. 3) are 1.7 μm, the gate overlap amount GF is 0.7 μm, The depth of the recesses CP1 and CP2 was set to 0.3 μm. For this reason, the state in which the depth D of the concave portion CP4 in each of FIGS. 39 to 41 is 0.3 μm means that the state in FIG. 3 (comparative example) is obtained, and the depth D of the concave portion CP4 is 0 μm. This means that the state shown in FIG. 2 (Embodiment 1) is obtained.

  39 to 41, even when the concave portion CP4 is formed on the substrate convex portion CV and the element isolation insulating film SI is embedded in the concave portion CP4, as shown in FIG. It was found that the on-breakdown voltage can be improved and the on-resistance can be reduced as compared with the comparative example (depth D is 0.3 μm), similarly to the configuration without the recess CP4 (depth D is 0 μm). Further, it was found that when the depth D of the concave portion CP4 is 0.15 μm or less, substantially the same on breakdown voltage and on resistance as the configuration shown in FIG. 2 (depth D is 0 μm) can be obtained.

  Therefore, as shown in FIG. 38, in the configuration in which the element isolation insulating film SI is formed on the substrate convex portion CV, the comparative example (depth D) is the same as the configuration shown in FIG. 2 (depth D is 0 μm). Can be improved and the on-resistance can be reduced.

(Other)
In the above embodiments and modifications, an n-type LDMOS transistor, an n-type bidirectional transistor, and an IGBT having an n ⁺ emitter region have been described. However, a p-type LDMOS transistor, a p-type bidirectional transistor, and a p ⁺ emitter region have been described. The configuration of the above embodiment can be similarly applied to an IGBT having the same.

Moreover, the said embodiment and modification can be combined suitably.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

AA, AA1 active region, AR p-type impurity region, BL n-type buried layer, CL conductive layer, CO contact region, CP, CP1-CP4 recess, CR p ⁺ collector region, CV, CV1 substrate protrusion, DR n ⁺ drain Region, DRI n-type drift region (n-type well region), EP, EP2 p ^- epitaxial region, ER n ⁺ emitter region, GE gate electrode layer, GE1 additional conductive layer, GI gate insulating film, GI1 insulating film, IP impurity region , SI element isolation insulating film, SR n ⁺ source region, SUB semiconductor substrate, TR transistor, WL p-type well region.

Claims (1)

A semiconductor substrate having a main surface and having a first recess and a second recess on the main surface;
An element isolation insulating film formed in each of the first recess and the second recess;
A pair of impurity regions which are either a pair of source / drain regions and a pair of emitter / collector regions formed so as to sandwich the first recess and the second recess on the main surface;
One region of the pair of impurity regions is a first conductivity type, and a second conductivity type first region serving as a channel formation region formed on the main surface between the one region and the first recess, ,
A gate electrode layer formed on the first region with a gate insulating film interposed therebetween, and extending at least on the element isolation insulating film in the first recess,
The first recess and the second recess are arranged so as to be adjacent to each other with a substrate protrusion protruding to the main surface side from the bottom of each of the first recess and the second recess,
The semiconductor substrate further includes a third concave portion located on the substrate convex portion, the third concave portion is formed shallower than the first concave portion and the second concave portion, and the element isolation insulating film is the third concave portion. A semiconductor device formed in the recess .

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