KR102385949B1 - Lateral power integrated device having a low on resistance - Google Patents

Abstract

The horizontal power integrated device includes: a source region and a drift region of a second conductivity type disposed to be spaced apart from each other in a first direction in a semiconductor layer of a first conductivity type; and a drift region in the drift region. A drain region of a second conductivity type disposed on the drift region, a plurality of planar field insulating plates disposed to be spaced apart from each other in a second direction intersecting the first direction on the drift region, on a surface of the channel region and on a partial surface of the drift region and a gate insulating layer and a gate electrode layer disposed thereon. The gate electrode layer includes a plurality of gate electrode layer extension portions extending over the planar field insulating plates from one end of the gate electrode layer toward the drain region.

Description

Horizontal power integrated device having a low on resistance

Various embodiments of the present disclosure relate to a semiconductor device for power, and more particularly, to a horizontal power integrated device having a low on-resistance.

An integrated circuit in which a control function and a driver function are combined is often referred to as a smart power device. This smart power device typically has a power integrated device such as a LDMOS (Lateral Double diffused MOS) device at an output terminal designed to operate at a high voltage. In such a power integrated device, a breakdown voltage characteristic is an important factor in terms of device stability, and an on-resistance (Ron) characteristic is an important factor in terms of device operation characteristics, for example, current drivability. become a character In order to improve the breakdown voltage characteristic of the device, it is necessary to reduce the doping concentration in the drift region or increase the drift length corresponding to the movement length of the current in the drift region. However, in this case, the on-resistance (Ron) of the device is increased, and the current driving ability is deteriorated. In the opposite case, that is, if the doping concentration in the drift region between the drain region and the channel region is increased or the drift length of the drift region is decreased, the on-resistance Ron of the device decreases but the drain junction breakdown voltage of the device also decreases. lowered together That is, in the LDMOS device, the on-resistance characteristic and the breakdown voltage characteristic have a trade-off relationship.

SUMMARY OF THE INVENTION An object of the present application is to provide a horizontal type power integrated device having a low on-resistance while compensating for deterioration of breakdown characteristics.

A horizontal power integrated device according to an example includes a source region and a drift region of a second conductivity type that are spaced apart from each other in a first direction in a semiconductor layer of a first conductivity type, and a second region that is disposed in the drift region. A conductive drain region, a plurality of planar field insulating plates disposed to be spaced apart from each other in a second direction intersecting the first direction on the drift region, and a gate insulating plate disposed on a surface of the channel region and on a partial surface of the drift region layer and a gate electrode layer. The gate electrode layer includes a plurality of gate electrode layer extension portions extending over the planar field insulating plates from one end of the gate electrode layer toward the drain region.

According to various embodiments, the planar insulating field plates are arranged to be spaced apart from each other in the channel width direction on the drift region, the length of the gate electrode layer is shortened in a region where the planar insulating field plates are not arranged, and the planar insulating field plates are By increasing the length of the gate electrode layer in the region in which it is disposed, there is provided an advantage that the on-resistance can be lowered while compensating for deterioration of the breakdown voltage characteristic.

1 is a layout diagram illustrating a horizontal power integrated device according to an example.
FIG. 2 is a diagram illustrating regions constituting an n-type drift region of the horizontal power integrated device of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 1 .
4 is a cross-sectional view taken along the line II-II' of FIG. 1 .

In order to increase the breakdown voltage of the horizontal power integrated device, a trench field insulating plate having a structure similar to that of the trench isolation layer may be disposed in a drift region between the channel region and the drain region. In this case, the breakdown voltage characteristic of the device is improved, but the drift length increases as carriers move along the side and bottom surfaces of the trench field insulating plate in the drift region, and accordingly, the on-resistance of the device increases. characteristics are reduced. In various embodiments of the present application, the planar insulating field plates are arranged to be spaced apart from each other in the channel width direction on the drift region, the length of the gate electrode layer is shortened in the region where the planar insulating field plates are not arranged, and the planar insulating field plates are arranged. An object of the present invention is to present a horizontal power integrated device capable of lowering the on-resistance while maintaining the breakdown voltage characteristic by increasing the length of the gate electrode layer in the region where the plates are disposed.

In the description of examples of the present application, descriptions such as "first" and "second" are for distinguishing members, and are not used to limit the members themselves or to mean a specific order. In addition, the description that it is located "on" or "upper", "lower", or "side" of a member means a relative positional relationship, and another member is introduced into direct contact with the member or at an interface between the members. It does not limit the specific case of being. In addition, the description that one component is "connected" or "connected" to another component may be directly or electrically connected to another component or may be connected to another component in the middle Separate components may be interposed to form a connection relationship or a connection relationship.

1 is a layout diagram illustrating a horizontal type power integrated device according to an example. And FIG. 2 is a diagram illustrating regions constituting the n-type drift region of the horizontal power integrated device of FIG. 1 . 1 and 2 , the p-type body region 104 and the n-type drift region 106 are disposed to be spaced apart from each other by a predetermined distance along the first direction. In this example, the first direction may be defined as a channel length direction, that is, a direction in which carriers (or currents) move between the drain and the source. The p-type body region 104 and the n-type drift region 106 are surrounded by the p-type semiconductor layer 102 . The p-type semiconductor layer 102 between the p-type body region 104 and the n-type drift region 106 constitutes the first channel region 121 . A p+ type body contact region 108 is disposed in the p-type body region 104 . The p+ type body contact region 108 is disposed in the form of a stripe elongated in a second direction intersecting the first direction.

N+ type source regions 110 are disposed on both sides of the p + type body contact region 108 . A side surface of each of the n+ type source regions 110 forms a junction with both side surfaces of the p+ type body contact region 108 . The p+ type body contact region 108 and the n+ type source region 110 are commonly coupled to the source terminal S. An upper region of the p-type body region 104 between the n+-type source region 110 and the first channel region 121 constitutes the second channel region 122 . The first channel region 121 and the second channel region 122 constitute the entire channel region 120 of the power integrated device 100 . An n+-type drain region 112 is disposed at one edge of the n-type drift region 106 . The n+ type drain region 112 may be disposed in the form of a stripe elongated in the second direction.

The upper region of the n-type drift region 106 may be divided into a first n-type drift region 106A, a second n-type drift region 106B, and an accumulation region 107 as shown in FIG. 2 . . Specifically, as shown in FIGS. 3 and 4 , the accumulation region 107 may be defined as a region that vertically overlaps the gate insulating layer 114 and the gate electrode layer 116 . The accumulation region 107 has a stripe shape extending long in the second direction. The first n-type drift region 106A and the second n-type drift region 106B are to be defined as regions alternately disposed along the second direction between the accumulation region 107 and the n+-type drain region 112 . can Lengths measured in the first direction of the first n-type drift region 106A and the second n-type drift region 106B may be substantially the same. Widths measured in the second direction of the first n-type drift region 106A and the second n-type drift region 106B may be substantially the same. In another example, widths measured in the second direction of the first n-type drift region 106A and the second n-type drift region 106B may be different from each other.

In the first n-type drift region 106A, a planar field insulating plate 130 is disposed on the n-type drift region 106 . Among both sides of the planar field insulating plate 130 , a side facing the n+ type drain region 112 may be aligned with one side of the n+ type drain region 112 . In the second n-type drift region 106B, an upper surface of the n-type drift region 106 is exposed. Although not shown in the drawings, when a silicide process is required, a silicide protection layer may be disposed on the n-type drift region 106 of the second n-type drift region 106B.

The gate electrode layer 116 is disposed on the channel region 120 and a partial region of the n-type drift region 106 , that is, the accumulation region. Although not shown in this planar structure, a gate insulating layer is disposed between the gate electrode layer 116 and the channel region 120 and the n-type drift region 106 . One first side of both sides of the gate electrode layer 116 may be aligned with one side of the n+ type source region 110 in contact with the channel region 120 . A second side of the gate electrode layer 116 opposite to the first side has an accumulation region 107 of the n-type drift region 106 and the first and second n-type drift regions 106A and 106B. It can be aligned with the boundary line between them. The gate electrode layer 116 includes a plurality of gate electrode layer extension portions 116E, each extending from the second side surface in the first direction. The gate electrode layer extension portions 116E are disposed to be spaced apart from each other by a predetermined interval in the second direction. In particular, the gate electrode layer extension portion 116E is disposed to overlap the planar field insulating plate 140 without overlapping the second n-type drift region 106B.

FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 1 . And FIG. 4 is a cross-sectional view taken along the line II-II' of FIG. 1 . 3 and 4, the same reference numerals as in FIGS. 1 and 2 denote the same components. Referring to FIGS. 3 and 4 , the p-type body region 104 and the n-type drift region 106 are disposed to be spaced apart from each other in the first direction, which is the channel length direction, in the upper region of the p-type semiconductor layer 102 . The p-type semiconductor layer 102 may be a p-type semiconductor substrate. The p-type semiconductor layer 102 may be a p-type junction region formed on the upper region of the semiconductor substrate, for example, a p-type well region. The p-type semiconductor layer 102 may be a p-type epitaxial layer formed on a semiconductor substrate. An upper region of the p-type semiconductor layer 102 between the p-type body region 104 and the n-type drift region 106 may be defined as a first channel region 121 .

A p+ type body contact region 108 is disposed in the upper region of the p-type body region 104 . An n+ type source region 110 is disposed on both sides of the p + type body contact region 108 , respectively. Each of both side surfaces of the p+ type body contact region 108 and one side surface of the n+ type source region 110 constitute a junction surface. The p+ type body contact region 108 and the n+ type source region 110 are commonly coupled to the source terminal S. An upper region of the p-type body region 104 between the n+-type source region 110 and the first channel region 121 may be defined as the second channel region 122 . The first channel region 121 and the second channel region 122 constitute the entire channel region 120 .

An n+ type drain region 112 is disposed on the upper region of the n-type drift region 106 . The n+ type drain region 112 is coupled to the drain terminal (D). In the first n-type drift region 106A, a planar field insulating plate 130 is disposed on the n-type drift region 106 . The planar field insulating plate 130 has a lower surface on the same horizontal level as the upper surface of the n-type drift region 106 , and accordingly, the upper surface of the n-type drift region 106 is equal to the thickness of the planar field insulating plate 130 . It protrudes vertically from the surface. A gate insulating layer 114 is disposed on the channel region 120 and the accumulation region 107 . A gate electrode layer 116 is disposed on the gate insulating layer 114 . The gate electrode layer 116 is coupled to the gate terminal (G). In one example, the gate insulating layer 114 may be composed of an oxide layer, and the gate electrode layer 116 may be composed of a polysilicon layer doped with impurity ions.

In the first n-type drift region 106A, the gate electrode layer 116 may include gate electrode layer extension portions 116E extending over the planar field insulating plate 130 . The gate electrode layer extension portions 116E are disposed to be spaced apart from each other in the second direction. Each of the gate electrode layer extension portions 116E overlaps the planar field insulating plate 130 , but does not overlap the second n-type drift region 106B. A length measured along the first direction of the gate electrode layer extension portion 116E is shorter than a length measured along the first direction of the planar field insulating plate 130 . Accordingly, the end of the gate electrode layer extension portion 116E is spaced apart from the n+ type drain region 112 by a predetermined interval. The gate electrode layer extension portion 116E may serve as a conductive field plate.

In the second n-type drift region 106B, an upper surface of the n-type drift region 106 is exposed. That is, as the gate electrode layer extension portion 116E is not disposed in the second n-type drift region 106B, the gate insulating layer 114 and the gate electrode layer 116 are formed in the channel region 120 and the accumulation region 107 . ) overlaps only in the vertical direction.

In the horizontal power integrated device 100 according to the present example, the first n-type drift region 106A and the second n-type drift region 106B of the n-type drift region 106 alternate in the second direction. are placed hostilely. A planar field insulating plate 130 is disposed on the upper surface of the n-type drift region 106 of the first n-type drift region 106A. The upper surface of the n-type drift region 106 of the second n-type drift region 106B is exposed. Accordingly, in the upper region of the n-type drift region 106 between the accumulation region 107 and the n+-type drain region 112 , carriers move along the vicinity of the surface of the n-type drift region 106 to represent the shortest drift length. Accordingly, the on-resistance characteristic of the device due to the drift length can be maximally improved. Meanwhile, the decrease in breakdown voltage due to the short drift length can be compensated for by disposing the planar field insulating plate 130 on the upper surface of the first n-type drift region 106A. Furthermore, the breakdown voltage can be further increased by disposing the gate electrode layer extension 116E serving as a conductive field plate on the planar field insulating plate 130 .

As described above, the embodiments of the present application are illustrated and described with drawings, but this is for explaining what is intended to be presented in the present application, and is not intended to limit what is intended to be presented in the present application to a detailed shape.

100...horizontal power integrated device 102...p-type semiconductor layer
104...p-type body area 106...n-type drift area
106A...First n-type drift region 106B...Second n-type drift region
107...accumulation area 108...p+ type body contact area
110...n+ type source region 112...n+ type drain region
114...Gate insulating layer 116...Gate electrode layer
120...channel area 121...first channel area
122...Second channel area 130...Planner field insulation plate

Claims (15)

a source region and a drift region of a second conductivity type disposed to be spaced apart from each other in a first direction in the semiconductor layer of the first conductivity type;
a drain region of a second conductivity type disposed in the drift region;
a plurality of planar field insulating plates arranged to be spaced apart from each other in a second direction intersecting the first direction on the drift region; and
a gate insulating layer and a gate electrode layer disposed on a surface of a channel region between the source region and the drift region and on a partial surface of the drift region;
The gate electrode layer may include a plurality of gate electrode layer extension portions extending over the planar field insulating plates from one end of the gate electrode layer toward the drain region. According to claim 1,
and a body region of a first conductivity type disposed in the semiconductor layer to surround the source region and spaced apart from the drift region in a first direction. 3. The method of claim 2,
The channel region includes a first channel region between the body region and the drift region, and a second channel region between the source region and the first channel region. According to claim 1,
The source region, the drain region, and the drift region have a stripe shape elongated in the second direction. According to claim 1, wherein the drift region,
an accumulation region vertically overlapping the gate insulating layer and the gate electrode layer; and
and a first drift region and a second drift region alternately disposed in the second direction between the accumulation region and the drain region. 6. The method of claim 5,
The gate insulating layer and the gate electrode layer are disposed on the accumulation region of the drift region. 6. The method of claim 5,
Each of the planar field insulating plates is disposed on the first drift region. 8. The method of claim 7,
Each of the planar field insulating plates has a lower surface on the same horizontal level as an upper surface of the first drift region. 8. The method of claim 7,
A width of the first drift region measured in the second direction is the same as a width of the second drift region measured in the second direction. According to claim 1,
The extended portions of the gate electrode layer are disposed to be spaced apart from each other by a predetermined interval in the second direction. 11. The method of claim 10,
The drift region includes an accumulation region vertically overlapping with the gate insulating layer and the gate electrode layer, and first and second drift regions alternately disposed in the second direction between the accumulation region and the drain region including,
Each of the extended portions of the gate electrode layer overlaps each of the planar field insulating plates, and is disposed so as not to overlap the second drift region. According to claim 1,
A horizontal power integrated device in which a width measured along the second direction of each of the planar field insulating plates is uniform. According to claim 1,
A side of each of the planar field insulating plates, which is disposed toward the drain region, is aligned with one side of the drain region. According to claim 1,
The first conductivity type is a p-type, and the second conductivity type is an n-type horizontal type power integrated device. According to claim 1,
The first direction is a channel length direction, and the second direction is a channel width direction.

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