TWI777225B - Integrated chip and method of forming the same - Google Patents

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

Description

Integrated wafer and method of forming the same

Embodiments of the present invention relate to integrated wafers and methods of forming the same.

Today's integrated chips (ICs) include millions or billions of semiconductor devices formed on a semiconductor substrate (eg, silicon). Depending on the application of the integrated chip (IC), many different types of transistor devices can be used in an integrated chip. In recent years, the growing market for cellular devices and radio frequency (RF) devices has led to a significant increase in the use of high voltage transistor devices. For example, high voltage transistor devices are often used in power amplifiers in RF transmit/receive chains due to their ability to handle high breakdown voltages (eg, greater than about 50V) and high frequencies.

In some embodiments, the present disclosure pertains to an integrated wafer. The integrated wafer includes: a source region disposed in a substrate; a drain region disposed in the substrate and spaced apart from the source region along a first direction; a drift region, in the source region and the source region The drain regions are arranged in the substrate; a plurality of isolation structures are arranged in the drift region; and a gate electrode is arranged in the substrate, the gate electrode has a base region and a plurality of a gate extension part, the base region is disposed between the source region and the drift Between the transition regions, the plurality of gate extensions extend outward from the sidewalls of the base region onto the plurality of isolation structures.

In other embodiments, the present disclosure relates to an integrated wafer. The integrated wafer includes: a source region, arranged in a substrate; a drain region, arranged in the substrate; a gate dielectric, lining the inner surface of the substrate; and a gate electrode, arranged in the substrate There is a base region and a plurality of gate extensions between the source region and the drain region, the base region is located on the gate dielectric, and the plurality of gate extensions extend from the gate sidewalls of the base region of the gate electrode protrude outward toward the drain region; and a plurality of isolation structures extending continuously between the gate dielectric and the drain region, the plurality of isolation structures An isolation structure surrounds one of the plurality of gate extensions, respectively.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a plurality of isolation structures in a substrate; selectively etching the substrate to form gate base grooves in the substrate; selectively etching the plurality of isolation structures, forming a plurality of gate extension trenches extending outward from the gate base groove; forming a conductive material in the gate base groove and the plurality of gate extension trenches to form gate electrodes; and Source and drain regions are formed on opposite sides of the gate electrode.

100, 300, 400, 700, 800: Integrated wafers

102: Substrate

102i, 112i: inner surface

102u: upper surface

104, 104a, 104b, 714: source regions

105: Gate dielectric

106, 106a, 106b, 712: gate structure

107, 722: gate electrode

107b: Base Area

107e: Gate extension

107e ₁ : first gate extension

107e ₂ : the second gate extension

108, 716: drain region

109: Well District

110: Drift Zone

112: Isolation Structure

112a: first isolation structure

112b: Second isolation structure

112c: Third isolation structure

114: First Direction

116: Second direction

200, 216, 222, 500, 600, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400: Cutaway view

202, 502, 602, 910, 1012, 1102, 1212, 1306, 1402, 1510, 1604, 1704: Top View

204: first thickness

206: Second thickness

208: Interlayer Dielectric (ILD) Structure

208a: First ILD layer

208b: Second ILD layer

210: Conductive Contacts

212: Inline

214: Depletion Zone

218: Ditch

220: Additional Ditch

224: Negative Charge

226: positive charge

302, 310: non-zero distance

304: Protrusion

306: Dielectric Structure

308: Silicide

312: Contact Etch Stop Layer (CESL)

402: Spacing

404: Distance

702: High Voltage Transistor Device Area

704: Peripheral logic area

706: First Dielectric Material

708: Second Dielectric Material

710: Third Dielectric Material

717: Gate Dielectric Structure

718: First gate dielectric material

720: Second gate dielectric material

724, 726: Overlying dielectric layer

728, 1904: Sidewall Spacers

802a, 802b: body area

804, 1702, 2102: Line

902, 1208: first depth

904: Thickness

906: Additional isolation structure

908: Second Depth

1002: Isolation Ditch

1004: First Etchant

1006: First masking layer

1008: First hard mask layer

1010: Second hard mask layer

1202: Gate base groove

1204: Second Etchant

1202h ₁ , 1202h ₂ : Horizontally extending surfaces

1202s ₁ , 1202s ₂ : side walls

1206: Second masking layer

1210: Second Depth

1302: Second Dopant Species

1304: Third masking layer

1502: Gate extension trench

1504: Third Depth

1506: Third Etchant

1508: Fourth Masking Layer

1512: 3D View

1602: Gate Material

1802: Gate Stacking

1804: Gate Electrode Materials

1806: The third dielectric material

1808: Fourth dielectric material

1902: Patterned gate stacks

1906: Source Region

1908: Drain region

2002: Dopant species

2104: Dielectric Stacking

2202: Fifth Shading Layer

2204: Opening

2206: Etchant

2500: Method

2502, 2504, 2506, 2508, 2510, 2512, 2514, 2516, 2518, 2520, 2522, 2524, 2526: Actions

A-A′: hatch line

B-B': hatch line

d : distance

Various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 illustrates some embodiments of an integrated wafer with high voltage transistor devices Three-dimensional view of the high voltage transistor device including a gate electrode with a gate extension.

2A-2D illustrate some additional embodiments of integrated wafers having high voltage transistor devices including recessed gate electrodes with gate extensions.

3 illustrates cross-sectional views of some additional embodiments of integrated wafers having high voltage transistor devices including recessed gate electrodes with gate extensions.

4 shows a top view of some additional embodiments of an integrated wafer having a high voltage transistor device including a gate electrode with a gate extension.

5A-5B illustrate some additional embodiments of integrated wafers having high voltage transistor devices including recessed gate electrodes with gate extensions.

6A-6B illustrate some additional embodiments of integrated wafers having high voltage transistor devices including partially recessed gate electrodes with gate extensions.

7 illustrates a cross-sectional view of some embodiments of an integrated wafer having high voltage transistor device regions and surrounding logic regions.

8 shows top views of some additional embodiments of integrated wafers with high voltage transistor devices including gate electrodes with gate extensions.

9A-9B illustrate some additional embodiments of integrated wafers with high voltage transistor devices including recesses with gate extensions gate electrode.

10A-24 illustrate cross-sectional views of some embodiments of methods of forming an integrated wafer with high voltage transistor devices including recessed gate electrodes with gate extensions.

25 shows a flowchart of some embodiments of a method of forming an integrated wafer having a high voltage transistor device including a recessed gate electrode with a gate extension.

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of elements and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is formed Embodiments in which additional features may be formed between and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may reuse reference numbers and/or letters in various instances. This re-use is for the purpose of brevity and clarity and is not itself indicative of the relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, for example, "beneath", "below", "lower", "above" may be used herein. )", "upper" and other spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass installations in addition to the orientation depicted in the figures. different orientations in use or operation. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Integrated wafers often include transistors designed to operate at a variety of different voltages. High voltage transistors are designed to operate at high breakdown voltages (eg, breakdown voltages greater than approximately 20V, greater than approximately 50V, or other suitable values). One common type of high voltage transistor is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS) device. The LDMOS device has a gate structure disposed over a substrate between source and drain regions. The gate structure is separated from the drain region by the drift region. The drift region includes a lightly doped region of the substrate (eg, a region where the doping concentration of the substrate is less than the doping concentration of the source region and/or the doping concentration of the drain region).

During operation, a bias voltage may be applied to the gate structure to form an electric field that causes the channel region to extend under the gate structure and through the drift region. The breakdown voltage of an LDMOS device is generally proportional to the size and doping concentration of the drift region (eg, a larger drift region will result in a larger breakdown voltage). However, if the electric field within the device is not uniform, the breakdown voltage of the transistor device may be negatively affected. For example, the breakdown voltage of an LDMOS may be negatively affected due to spikes in the electric field that may occur at the p-n junction between the drift region and the substrate.

In some embodiments, the present disclosure relates to an integrated wafer including a transistor device having a gate electrode having a plurality of gate electrodes configured to provide a high breakdown voltage to the transistor device gate extension. The gate electrode is disposed in the substrate between the source region and the drain region. The drift region is located between the gate electrode and the drain region. The plurality of gate extensions laterally outward from the sidewall of the gate electrode Protrudes and crosses the drift zone. The plurality of gate extensions are configured to generate an electric field within the drift region, which can spread charge laterally along the p-n junction of the device. By spreading the charge in the lateral direction, the electric field along the surface of the substrate can be spread, reducing spikes in the electric field and increasing the breakdown voltage of the transistor device.

FIG. 1 shows a three-dimensional view of some embodiments of an integrated wafer 100 having a high voltage transistor device including a gate electrode with a gate extension.

The integrated wafer 100 includes a gate structure 106 disposed within a substrate 102 . In some embodiments, gate structure 106 is recessed within substrate 102 . In some such embodiments, the gate structure 106 extends from below the upper surface 102u of the substrate 102 to the upper surface 102u of the substrate 102 . A source region 104 is provided on a first side of the gate structure 106 and a drain region 108 is provided on a second side of the gate structure 106 opposite the first side. The source region 104 and the drain region 108 are separated along the first direction 114 by the gate structure 106 .

A drift region 110 is arranged between the gate structure 106 and the drain region 108 along the first direction 114 . In some embodiments, a well region 109 may be provided within the substrate 102 below the gate structure 106 and the well region 109 laterally contacts the drift region 110 . One or more isolation structures 112 are disposed within the drift region 110 . The one or more isolation structures 112 extend in the first direction 114 along the upper surface of the substrate 102 between the gate structures 106 and the drain regions 108 . The one or more isolation structures 112 are separated from each other by the drift region 110 along a second direction 116 perpendicular to the first direction 114 . In some embodiments, the sidewalls of the one or more isolation structures 112 extend parallel to each other along the first direction 114 . In some embodiments, the one or more isolation structures 112 include one or more dielectric materials disposed within trenches in the substrate 102 . in some In an embodiment, the one or more isolation structures 112 may include shallow trench isolation (STI) structures.

The gate structure 106 includes a gate dielectric 105 and a gate electrode 107 on the gate dielectric 105 . The gate electrode 107 includes a base region 107b and one or more gate extensions 107e. Base region 107b is separated from drift region 110 by gate dielectric 105 . In some embodiments, gate dielectric 105 extends continuously from a first side of base region 107b to an opposite second side of base region 107b. The one or more gate extensions 107e protrude laterally outward from the sidewall of the base region 107b of the gate electrode 107 into the one or more isolation structures 112 . The one or more isolation structures 112 separate the one or more gate extensions 107e from the drift region 110 laterally and vertically. In some embodiments, the one or more gate extensions 107e extend through the sidewalls of the gate dielectric 105 .

During operation, a bias voltage may be applied to the gate electrode 107 . The bias voltage causes the charge (eg, positive or negative) within the gate electrode 107 to create an electric field in the underlying substrate 102 . Typically, due to the crowding of the surface field at the junction of the drift region 110 and the well region 109, the maximum breakdown voltage of the transistor device may be limited by the junction edge breakdown effect. However, the electric field generated by the one or more gate extensions 107e laterally spreads the electric field along the surface of the substrate 102 (eg, in the second direction 116). By spreading the electric field, the one or more gate extensions 107e reduce the electric field strength along the surface of the substrate 102, thereby enabling the transistor device to achieve a higher breakdown voltage.

2A-2C illustrate some additional embodiments of integrated wafers with high voltage transistor devices including gate extensions with gate extensions the recessed gate electrode.

As shown in cross-sectional view 200 of FIG. 2A , the integrated wafer includes source regions 104 and drain regions 108 disposed within substrate 102 . A drift region 110 is arranged between the source region 104 and the drain region 108 . In some embodiments, well region 109 may surround source region 104 , drain region 108 , and drift region 110 . In some embodiments, substrate 102 and well region 109 may have a first doping type (eg, p-type), while source region 104, drain region 108, and drift region 110 may have a second doping type (eg, p-type) n-type). In some embodiments, drift region 110 may have a second doping type (eg, n-type), but with a lower doping concentration than source region 104 and/or drain region 108 .

A gate electrode 107 is provided in the substrate 102 between the source region 104 and the drain region 108 . The gate electrode 107 is separated from the drain region 108 by the drift region 110 . The gate electrode 107 includes a base region 107b and one or more gate extensions 107e. The one or more gate extensions 107e extend outward from the base region 107b to just above the drift region 110 along the first direction 114 . The base region 107b is surrounded by the gate dielectric 105 . The one or more gate extensions 107e are surrounded by one or more isolation structures 112 arranged within the drift region 110 . In some embodiments, the one or more gate extensions 107e may extend directly above the upper surface of the one or more isolation structures 112 and gate dielectric 105 . In some embodiments, the one or more gate extensions 107e may have a bottom surface in contact with both the upper surface of the gate dielectric 105 and the upper surface of the one or more isolation structures 112 .

In some embodiments, the gate electrode 107 may comprise a conductive material, such as a metal (eg, tungsten, aluminum, etc.), doped polysilicon, and the like. In some embodiments, the gate dielectric 105 and the one or more isolation structures 112 may comprise oxides (eg, silicon oxide), nitrides (eg, silicon nitride), and the like.

In some embodiments, the base region 107b can have a first thickness 204 and the one or more gate extensions 107e can have a second thickness 206 . In some embodiments, the second thickness 206 may be smaller than the first thickness 204 . For example, in some embodiments, the second thickness 206 may be between 50% and approximately 90% of the first thickness 204 . In some embodiments, the first thickness 204 may range between approximately 900 angstroms (Å) and approximately 600 Å, between approximately 650 Å and approximately 750 Å, or other similar values. In other embodiments (not shown), the second thickness 206 may be approximately equal to the first thickness 204 .

A plurality of conductive interconnects (conductive contacts 210 to interconnects 212 ) are disposed within an inter-level dielectric (ILD) structure 208 over the substrate 102 . In some embodiments, the plurality of conductive interconnects (conductive contact 210 to interconnect 212 ) may include one or more conductive contacts 210 coupled to interconnect 212 . In some embodiments, the one or more conductive contacts 210 are electrically coupled to the source region 104 , the drain region 108 , and the gate electrode 107 . In some embodiments, the plurality of conductive interconnects (conductive contact 210 to interconnect 212) may comprise one or more of copper, tungsten, aluminum, and the like. In some embodiments, the ILD structure 208 may comprise silicon dioxide, doped silicon dioxide (eg, carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphorous One or more of phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), and the like.

FIG. 2B shows a top view 202 of the integrated wafer of FIG. 2A. The cross-sectional view 200 of FIG. 2A is taken along section line AA ' of FIG. 2B.

As shown in the top view 202 of FIG. 2B, the one or more gates extend The extension 107e protrudes outward from the sidewall of the base region 107b in the first direction 114 , and the base region 107b extends beyond the one or more gate extensions 107e in the second direction 116 . Adjacent ones of the one or more gate extensions 107e are separated in the second direction 116 by both the drift region 110 and portions of at least two of the one or more isolation structures 112 . separated.

In some embodiments, the one or more isolation structures 112 extend continuously in the first direction 114 from a first end contacting the gate dielectric 105 to a second end contacting the drain region 108 . In some embodiments, the one or more gate extensions 107e are separated from the drain region 108 by the one or more isolation structures 112 . In such an embodiment, the one or more gate extensions 107e are separated from one end of the one or more isolation structures 112 by a non-zero distance d . In various embodiments, the non-zero distance d may be within a range of between approximately 400 μm and approximately 1,000 μm, between approximately 400 μm and approximately 750 μm, between approximately 250 μm and approximately 500 μm, or other suitable values.

Figure 2C shows a cross-sectional view 216 of the integrated wafer taken along section line BB ' of Figure 2B.

As shown in cross-sectional view 216 , the one or more isolation structures 112 are disposed within trenches 218 formed by the inner surface 102 i of the substrate 102 . The gate extensions 107e are disposed within additional trenches 220 formed by the inner surfaces 112i of the one or more isolation structures 112 . This causes the one or more gate extensions 107e to be separated from each other in the second direction 116 by the drift region 110 and the one or more isolation structures 112 .

As shown in cross-sectional view 200 of FIG. 2A and cross-sectional view 216 of FIG. 2C , depletion regions 214 exist along the p-n junction between drift region 110 and well region 109 and/or substrate 102 . The depletion region 214 allows the formation of an electric field along the p-n junction. applied to the source region 104, the bias voltage of the drain region 108 and/or the gate electrode 107, and thus the electric field increases during operation of the transistor device. However, the one or more gate extensions 107e can generate an electric field that spreads charge along the p-n junction.

For example, Figure 2D shows a cross-sectional view 222 of the integrated wafer taken along section line BB ' of Figure 2B during operation of the high voltage transistor device.

As shown in cross-sectional view 222 of FIG. 2D, during operation, a bias voltage may be applied to the one or more gate extensions 107e. The bias voltage causes the one or more gate extensions 107e to form an electric field that extends into the well region 109 and the drift region 110 . Due to the doping type of well region 109 and the doping type of drift region 110 , the electric field causes charges 224 and 226 of opposite polarities to accumulate within well region 109 and within drift region 110 . For example, in some embodiments, negative charge 224 may be accumulated within well region 109 and positive charge 226 may be accumulated within drift region 110 . The one or more gate extensions 107e may spread charges 224 and 226 along the second direction 116 and beyond the outermost one of the one or more gate extensions 107e. Extending the charges 224 and 226 may increase the width of the depletion region 214 along the second direction 116 and alleviate spikes in the electric field along the surface of the substrate 102 (eg, making the surface electric field over the p-n junction less than that corresponding to the breakdown voltage of the device) critical electric field). By reducing the spikes in the electric field along the surface of the substrate 102, the breakdown voltage of the high voltage transistor device can be increased.

3 shows a cross-sectional view of some additional embodiments of an integrated wafer 300 with high voltage transistor devices including recessed gate electrodes with gate extensions.

The integrated wafer 300 includes recessed gate electrodes 107 below the upper surface of the substrate 102 . Gate electrode 107 is separated from substrate 102 by gate dielectric 105 and by one or more isolation structures 112 . The gate electrode 107 includes the base region 107b and One or more gate extensions 107e, the base region 107b disposed over the gate dielectric 105, the one or more gate extensions 107e projecting outward from the base region 107b to the one or more isolations above structure 112 . The gate dielectric 105 extends along the sidewalls and the lower surface of the base region 107b. The one or more isolation structures 112 extend along sidewalls and a lower surface of the one or more gate extensions 107e.

In some embodiments, the one or more isolation structures 112 may have a different thickness ( e.g. greater thickness). In some embodiments, the one or more isolation structures 112 may extend in a vertical direction from the bottom of the one or more gate extensions 107e to below the bottommost surface of the gate dielectric 105 . In some additional embodiments, the one or more isolation structures 112 may extend in a vertical direction from a horizontal plane extending along the top of the gate dielectric 105 to below the bottommost surface of the gate dielectric 105 .

In some embodiments, gate dielectric 105 may extend laterally directly over portions, but not all, of the one or more isolation structures 112 . In some such embodiments, the gate dielectric 105 may line the upper surface and inner sidewalls of the one or more isolation structures 112 . In some additional embodiments, the gate dielectric 105 may extend a non-zero distance 302 below the upper surface of the one or more isolation structures 112 . In such an embodiment, the gate dielectric 105 may also line the outermost sidewalls of the one or more isolation structures 112 .

In some embodiments, gate dielectric 105 may include protrusions 304 extending outwardly from the upper surface of gate dielectric 105 between base region 107b and the one or more gate extensions 107e. In some embodiments, protrusions 304 extend above the bottom surface of the one or more gate extensions 107e. In some embodiments, the protrusions 304 may have tapered sidewalls such that the width of protrusion 304 decreases with increasing height above the upper surface. The protrusions 304 may be the result of the etching process used to form the one or more gate extensions 107e. For example, during fabrication, gate dielectric 105 may be formed along the sloped sidewalls of the one or more isolation structures 112 . The one or more isolation structures 112 may then be etched to form gate extension trenches extending from within the one or more isolation structures 112 to the sloped sidewalls. Over-etching of gate dielectric 105 will cause gate dielectric 105 to recess under the tops of the sloped sidewalls, creating protrusions 304 . In other embodiments (not shown), the etch process may etch the gate dielectric 105 beyond the sloped sidewalls such that the gate dielectric 105 on the sloped sidewalls is completely removed and the resulting gate dielectric The mass 105 has outer sidewalls that are spaced a non-zero distance from the sidewalls of the isolation structures 112 overlying the upper surfaces of the one or more isolation structures 112 .

In some embodiments, one or more dielectric structures 306 are disposed over opposing outer edges of gate electrode 107 . In some embodiments, the one or more dielectric structures 306 extend continuously from a first outer edge directly above the base region 107b to a second outer edge directly above the source region 104 . In some embodiments, the one or more dielectric structures 306 extend continuously from a third outer edge directly above the one or more gate extensions 107e of the gate electrode 107 to the drain region The fourth outer edge just above the 108. In some embodiments, the one or more dielectric structures 306 may extend a non-zero distance 310 over opposing edges of the gate electrode 107 . In some embodiments, the non-zero distance 310 may range between approximately 200 Å and approximately 600 Å, between approximately 350 Å and approximately 500 Å, or other suitable values. In some embodiments, the one or more dielectric structures 306 may include one or more dielectric materials, such as oxides, nitrides, and the like.

A silicide 308 is arranged along the upper surface of the source region 104 , the upper surface of the drain region 108 and the upper surface of the gate electrode 107 . The silicide 308 is configured to provide a low resistance connection to the conductive interconnects (conductive contacts 210 to interconnects 212). In various embodiments, the silicide 308 may include nickel silicide, titanium silicide, or the like. In some embodiments, the outer edge of silicide 308 is laterally spaced from the outer edge of source region 104, the outer edge of drain region 108, and the outer edge of gate electrode 107, such that source region 104, drain The portion of region 108 and gate electrode 107 directly below the one or more dielectric structures 306 may be free of silicide 308 .

A contact etch stop layer (CESL) 312 vertically separates the substrate 102 and the one or more dielectric structures 306 from the first interlayer dielectric (ILD) layer 208a. In some embodiments, the CESL 312 and/or the first ILD layer 208a extend from directly above the one or more dielectric structures 306 to the sidewalls of the one or more dielectric structures 306 . A second ILD layer 208b is provided on the first ILD layer 208a.

4 shows a top view of some additional embodiments of an integrated wafer 400 having a high voltage transistor device including a gate electrode with a gate extension.

The integrated wafer 400 includes a gate electrode 107 having a base region 107b and one or more gate extensions 107e. The one or more gate extensions 107e protrude outwardly from the base region 107b into the one or more isolation structures 112 along the first direction 114 . The one or more gate extensions 107e are spaced apart from each other along a second direction 116 perpendicular to the first direction 114 .

In some embodiments, the one or more isolation structures 112 may be aligned along the second direction 116 at a pitch 402 with the closest gate extension 107e of the one or more gate extensions 107e being spaced apart The distance 404 is greater than the spacing 402 . In such an embodiment, the closest gate extension 107e of the one or more gate extensions 107e is separated by an isolation structure that does not include a gate extension. For example, in some embodiments, the one or more gate extensions 107e may include a first gate extension 107e ₁ and a _{second gate extension 107e 2 that} are The gate extension closest to the _first gate extension 107e1. The first gate extension 107e ₁ is disposed in the first isolation structure 112a and the second gate extension 107e ₂ is disposed in the second isolation structure 112b. A third isolation structure 112c that does not surround the gate extension separates the first gate extension 107e ₁ from the second gate extension 107e ₂ .

5A-5B illustrate some additional embodiments of integrated wafers having high voltage transistor devices including recessed gate electrodes with gate extensions.

As shown in cross-sectional view 500 of FIG. 5A (taken along section line AA ′ of FIG. 5B ), the integrated wafer includes gate electrodes 107 disposed over substrate 102 . Gate electrode 107 includes a base region 107b and one or more gate extensions 107e that protrude outwardly from base region 107b over one or more isolation structures 112 . The gate dielectric 105 extends continuously along the sidewalls and lower surface of the base region 107b and the sidewalls and lower surface of the one or more gate extensions 107e. Gate dielectric 105 separates the one or more gate extensions 107e from the one or more isolation structures 112 vertically and laterally.

As shown in the top view 502 of FIG. 5B , the gate dielectric 105 extends around the periphery of the gate electrode 107 in a closed and unbroken loop. By surrounding both the base region 107b and the one or more gate extensions 107 with the gate dielectric 105, one or more processing steps may be eliminated from the fabrication process used to form the transistor device (eg, one or more lithography and/or etching processes). By eliminating one or more processing steps from the fabrication process used to form the transistor device, the cost of forming an integrated wafer may be reduced.

6A-6B illustrate some additional embodiments of integrated wafers having high voltage transistor devices including gate electrodes with gate extensions.

As shown in cross-sectional view 600 of FIG. 6A (taken along section line AA ' of FIG. 6B ), the integrated wafer includes a gate electrode 107 having a base region 107b and one or more gate extensions 107e. The gate dielectric 105 extends along the sidewalls and the lower surface of the base region 107b. The base region 107b protrudes outward from the upper surface 102u of the substrate 102 . The one or more gate extensions 107e protrude outwardly from the sidewall of the base region 107b above the upper surface 102u of the substrate 102 to just above the one or more isolation structures 112 .

As shown in top view 602 of FIG. 6B (taken along section line BB ' of FIG. 6A ), gate dielectric 105 extends around the periphery of base region 107b in a closed and uninterrupted ring. By having the one or more gate extensions 107e protrude outward from the sidewalls of the base region 107b located above the upper surface 102u of the substrate 102, one or more processes may be eliminated from the fabrication process used to form the transistor device steps (eg, one or more lithography and/or etching processes). By eliminating one or more processing steps from the fabrication process used to form the transistor device, the cost of forming an integrated wafer may be reduced.

7 illustrates a cross-sectional view of some embodiments of an integrated wafer 700 having high voltage transistor device regions and surrounding logic regions.

High voltage transistor device region 702 includes a high voltage transistor device including a gate disposed between source region 104 and drain region 108 Pole electrode 107 . The gate electrode 107 has a base region 107b and one or more gate extensions 107e extending outward from the base region 107b.

One or more dielectric structures 306 are disposed over opposing edges of the gate electrode 107 . The one or more dielectric structures 306 include a first dielectric material 706 and a second dielectric material 708 overlying the first dielectric material 706, respectively. In some embodiments, the third dielectric material 710 may extend along the outermost sidewalls of the first dielectric material 706 and the outermost sidewalls of the second dielectric material 708 . In some embodiments, the first dielectric material 706 and the second dielectric material 708 may comprise different dielectric materials, and the third dielectric material 710 may be the same as the first dielectric material 706 or the second dielectric material 708 the same dielectric material. In various embodiments, the first dielectric material 706, the second dielectric material 708, and the third dielectric material 710 may include oxides (eg, silicon dioxide), nitrides (eg, silicon nitride), carbides (eg, silicon carbide), and the like.

Peripheral logic region 704 includes one or more additional transistor devices. The one or more additional transistor devices include gate structures 712 arranged between source regions 714 and drain regions 716 and laterally surrounded by one or more sidewall spacers 728 . The gate structure 712 includes a gate dielectric structure 717 separating the gate electrode 722 from the substrate 102 . One or more overlying dielectric layers 724 - 726 may be disposed over the gate electrode 722 . In some embodiments, the gate dielectric structure 717 may include a first gate dielectric material 718 and a second gate dielectric material 720 overlying the first gate dielectric material 718 . In some embodiments, the first gate dielectric material 718 may be the same material as the first dielectric material 706, the second gate dielectric material 720 may be the same material as the second dielectric material 708, and all The one or more sidewall spacers 728 may be the same material as the third dielectric material 710 . In some embodiments, the first gate dielectric material 718 may have substantially the same value as the first dielectric material 706 thickness and the second gate dielectric material 720 may have substantially the same thickness as the second dielectric material 708 .

8 shows a top view of some additional embodiments of an integrated wafer 800 with high voltage transistor devices including recessed gate electrodes with gate extensions.

Integrated wafer 800 includes drain region 108 surrounded on opposite sides by source regions 104a-b. Gate structures 106a-106b are also disposed along opposite sides of drain region 108 and separate drain region 108 from source regions 104a-104b, respectively. Gate structures 106a-106b include a base region 107 and one or more gate extensions 107e extending outwardly from base region 107b toward drain region 108, respectively. In some embodiments, the body regions 802a-802b may be separated from the gate structures 106a-106b by the source regions 104a-104b.

In some embodiments, the source regions 104a-104b are electrically coupled together and the gate structures 106a-106b are electrically coupled together. In some additional embodiments, gate structures 106a-106b, source regions 104a-104b, and body regions 802a-802b are substantially symmetrical about line 804 that bisects drain region 108.

During operation, the charge within the drift region 110 is separated from the charge within the gate electrode 107 by both the gate dielectric 105 and the one or more STI regions 112 . Since the gate electrode extension 107e expands the charges in the drift region 110 in the lateral direction, the gate electrode extension 107e increases the capacitance between the drift region 110 and the gate electrode 107 .

9A-9B illustrate some additional embodiments of integrated wafers having high voltage transistor devices including recessed gate electrodes with gate extensions.

As shown in the cross-sectional view 900 of FIG. 9A , a gate electrode 107 is disposed within the substrate 102 between the source region 104 and the drain region 108 . Gate electrode 107 includes a base region 107b surrounded by gate dielectric 105 and one or more gate extensions 107e surrounded by one or more isolation structures 112 . In some embodiments, gate electrode 107 extends into substrate 102 to first depth 902 . In some embodiments, the first depth 902 may range between approximately 200 Å and approximately 800 Å, between approximately 500 Å and approximately 700 Å, or other suitable values. In some embodiments, the gate dielectric 105 may have a thickness 904 in a range between approximately 700 Å and approximately 1,000 Å, between approximately 800 Å and approximately 900 Å, or other suitable values.

In some embodiments, source region 104 and drain region 108 are laterally surrounded by one or more additional isolation structures 906 . The one or more additional isolation structures 906 are separated from the one or more isolation structures 112 by source regions 104 and drain regions 108 . In some embodiments, the one or more isolation structures 112 extending into the substrate 102 to the second depth 908 are substantially the same as the one or more additional isolation structures 906 . In some embodiments, the second depth 908 may range between approximately 2,000 Å and approximately 3,000 Å, between approximately 2,000 Å and approximately 2,500 Å, or other suitable values. As shown in the top view 910 of FIG. 9B, in some embodiments, the one or more additional isolation structures 906 may be wrapped around the transistor device in a closed-loop fashion.

10A-24 illustrate some embodiments of a method of forming an integrated wafer having a high voltage transistor device including a recessed gate electrode with a gate extension. Although FIGS. 10A-24 are illustrated with respect to one method, it should be understood that the structures disclosed in FIGS. 10A-24 are not limited to this method, but may exist independently of the method described.

As shown in cross-sectional view 1000 of FIG. 10A , substrate 102 is patterned to form one or more isolation trenches 1002 . In various embodiments, the substrate 102 may be any type of semiconductor body (eg, silicon, SiGe, silicon-on-insulator (SOI), etc.), such as a semiconductor wafer and/or one on a wafer or multiple dies, and any other types of semiconductor and/or epitaxial layers associated with the wafer. The one or more isolation trenches 1002 are formed by sidewalls and horizontally extending surfaces of the substrate 102 . As shown in the top view 1012 of FIG. 10B , in some embodiments, the one or more isolation trenches 1002 include rectangular-shaped trenches that extend parallel to each other in the first direction 114 and along the first direction 114 . The second directions 116, which are perpendicular to the direction 114, are spaced apart from each other.

In some embodiments, the one or more isolation trenches 1002 may be formed by selectively exposing the substrate 102 to the first etchant 1004 in accordance with the first masking layer 1006 . In some embodiments, the first masking layer 1006 may comprise a hard mask including a first hard mask layer 1008 and a second hard mask layer 1010 overlying the first hard mask layer 1008 . In some embodiments, the first hard mask layer 1008 includes a first dielectric material (eg, oxide, nitride, etc.) and the second hard mask layer 1010 includes a second dielectric that is different from the first dielectric material Materials (eg, oxides, nitrides, etc.). In some embodiments, the first etchant 1004 may comprise a dry etchant. For example, in some embodiments, the first etchant 1004 may comprise an oxygen etchant.

As shown in cross-sectional view 1100 of FIG. 11A , isolation structures 112 are formed within the one or more isolation trenches 1002 . As shown in the top view 1102 of FIG. 11B , the one or more isolation structures 112 are spaced apart from each other along the second direction 116 . In some embodiments, the one or more isolation structures 112 may be formed by forming one or more dielectric materials within the one or more isolation trenches 1002 . in some real In embodiments, the one or more dielectric materials may include oxides, nitrides, and the like. In some embodiments, the one or more dielectric materials may be formed by a deposition process (eg, chemical vapor deposition (CVD) process, plasma enhanced CVD process, etc.). In some embodiments, the one or more dielectric materials may be formed within the one or more isolation trenches 1002 prior to removing the entire first masking layer (1006 of FIG. 10A). A planarization process (eg, a chemical mechanical planarization process) may then be performed to laterally remove excess dielectric material from outside the one or more isolation trenches 1002 . In some embodiments, the one or more isolation structures 112 may be formed with additional isolation structures (not shown) that provide isolation between adjacent transistor devices (eg, as shown in FIGS. 9A-9B ). shown) formed at the same time.

As shown in cross-sectional view 1200 of FIG. 12A , gate base grooves 1202 are formed within substrate 102 . In some embodiments, the gate base recess 1202 may also extend into the one or more isolation structures 112 . In some embodiments, the gate base recess 1202 extends into the substrate 102 to a first depth 1208 that is less than the second depth 1210 of the one or more isolation structures 112 . Gate base recess 1202 is formed by one or more sidewalls 1202s ₁ and horizontally extending surface 1202h ₁ of substrate 102 . In some embodiments, gate base recess 1202 may be further formed by one or more sidewalls 1202s ₂ and horizontally extending surface 1202h ₂ of the one or more isolation structures 112 . As shown in the top view 1212 of FIG. 12B , the gate base grooves 1202 extend continuously in the second direction 116 beyond opposing sidewalls of the one or more isolation structures 112 .

In some embodiments, the gate base recess 1202 may be formed by selectively exposing the substrate 102 to the second etchant 1204 according to the second masking layer 1206 . In various embodiments, the second masking layer 1206 may include a hard mask layer, a photosensitive material (eg, lithography glue), and the like. In some embodiments, the second etchant 1204 may comprise a dry etchant. For example, in some embodiments, the second etchant 1204 may comprise an oxygen plasma etchant.

As shown in cross-sectional view 1300 of FIG. 13A and top view 1306 of FIG. 13B , well region 109 and drift region 110 are formed within substrate 102 . The drift region 110 laterally surrounds the one or more isolation structures 112 and extends vertically below the one or more isolation structures 112 . The well region 109 adjoins the drift region 110 vertically and/or laterally. In some embodiments, well region 109 may be formed by implanting a first dopant species into substrate 102 and then may be formed by implanting a second dopant species 1302 into substrate 102 according to third shielding layer 1304 to form the drift region 110 . In various embodiments, the first dopant species may include a first doping type (eg, formed from p-type dopants such as boron, aluminum, etc.) and the second dopant species 1302 may include a second doping type (For example, formed from n-type dopants such as phosphorous, arsenic, etc.). In some embodiments, the third shielding layer 1304 may include a photosensitive material (eg, lithographic glue). In some alternative embodiments, the well region 109 and/or the drift region 110 may be formed prior to forming the one or more isolation structures 112 .

As shown in cross-sectional view 1400 of FIG. 14A and top view 1402 of FIG. 14B , gate dielectric 105 is formed over substrate 102 . In some embodiments, gate dielectric 105 is formed within gate base recess 1202 and over substrate 102 and the one or more isolation structures 112 . In some embodiments, gate dielectric 105 may include oxides, nitrides, or the like. In some embodiments, the gate dielectric 105 may be formed by a deposition process (eg, a CVD process, a PE-CVD process, etc.).

As shown in the cross-sectional view 1500 of FIG. 15A , one or more gate extension trenches 1502 are formed within the one or more isolation structures 112 . The one or more gate extension trenches 1502 extend into the one or more isolation structures 112 to a third depth 1504 that is less than the second depth 1210 . In some embodiments, the third depth 1504 may also be less than the first depth 1208 of the gate base recess 1202 . In some embodiments, the one or more isolation structures 112 extend beyond the one or more gate extension trenches 1502 by a distance d such that the one or more gate extension trenches 1502 are separated by the one or more gate extension trenches 1502 Sidewalls and horizontally extending surfaces of the isolation structures 112 are formed. Figure 15B shows a top view 1510 of the cross-sectional view 1500 of Figure 15A. As shown in top view 1510 , the one or more gate extension trenches 1502 extend outward from various locations of gate base recess 1202 .

In some embodiments, the one or more gates may be formed by selectively exposing the gate dielectric 105 and the one or more isolation structures 112 to the third etchant 1506 according to the fourth masking layer 1508 Pole extension trench 1502. In various embodiments, the fourth masking layer 1508 may include a hard mask layer, a photosensitive material (eg, lithography glue), and the like. In some embodiments, the third etchant 1506 may comprise a dry etchant. In some alternative embodiments (not shown), the gate extension trench 1502 may be formed concurrently with the gate base recess 1202 . In some such embodiments, etchants with relatively low etch selectivity between silicon and silicon oxide (eg, dry etchants including CF4 ₎ may be used. 15C shows a three-dimensional view 1512 of the cross-sectional view of FIG. 15A and a top view 1510 of FIG. 15B after the fourth masking layer 1508 has been removed.

As shown in cross-sectional view 1600 of FIG. 16A and top view 1604 of FIG. 16B , gate material 1602 is formed within gate base recess 1202 and within the one or more gate extension trenches 1502 . In some embodiments, gate material 1602 may be formed from gate base recess 1202 and within the one or more gate extension trenches 1502 extends to just above the upper surface of the substrate 102 . In some embodiments, gate material 1602 may include polysilicon, metal, or the like. In some embodiments, gate material 1602 may be formed by deposition processes (eg, CVD processes, PE-CVD processes, etc.) and/or plating processes (eg, electroplating processes, electroless plating processes, etc.).

As shown in cross-sectional view 1700 of FIG. 17A , a planarization process is performed along line 1702 to form gate electrode 107 by removing excess gate material ( 1602 of FIG. 16 ) and gate dielectric 105 from above substrate 102 . As shown in the top view 1704 of FIG. 17B , the gate electrode 107 includes a base region 107b and protrudes laterally outwardly from the sidewall of the gate electrode 107 forming the base region 107b to just above the one or more isolation structures 112 one or more gate extensions 107e. In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

As shown in cross-sectional view 1800 of FIG. 18 , a gate stack 1802 is formed over substrate 102 . Gate stack 1802 extends beyond opposite sides of gate electrode 107 . In some embodiments, the gate stack 1802 may include a first dielectric material 706 , a second dielectric material 708 overlying the first dielectric material 706 , a gate electrode material overlying the second dielectric material 708 1804 , a third dielectric material 1806 overlying the gate electrode material 1804 , and a fourth dielectric material 1808 overlying the third dielectric material 1806 .

As shown in cross-sectional view 1900 of FIG. 19 , the gate stack ( 1802 of FIG. 18 ) is patterned to form patterned gate stack 1902 . In some embodiments, after the gate stack ( 1802 of FIG. 18 ) is patterned, one or more sidewall spacers 1904 are formed along opposite sides of the patterned gate stack 1902 . The patterned gate stack 1902 exposes the source region 1906 of the substrate 102 on the opposite side of the gate electrode 107 and drain region 1908. In some embodiments (not shown), the gate stacks may be patterned to form additional gate stacks in peripheral logic regions on another portion of the substrate (eg, as shown in FIG. 7 ).

As shown in cross-sectional view 2000 of FIG. 20 , one or more dopant species 2002 are implanted into substrate 102 to form source regions 104 and drain regions 108 on opposite sides of gate electrode 107 . In some embodiments, the one or more dopant species 2002 may be selectively implanted into the substrate 102 according to the patterned gate stack 1902 . In such an embodiment, source region 104 is formed within source region 1906 and drain region 108 is formed within drain region 1908 . In various embodiments, the one or more dopant species 2002 may include n-type dopants (eg, phosphorous, arsenic, etc.) or p-type dopants (eg, boron, aluminum, etc.). In some embodiments, an anneal may be performed after implanting the one or more dopant species 2002 into the substrate 102 to drive the dopants further into the substrate 102 .

As shown in cross-sectional view 2100 of FIG. 21 , a planarization process (along line 2102 ) is performed on the patterned gate stack ( 1902 of FIG. 20 ) to remove one or more layers of the patterned gate stack and form a dielectric stack 2104 . In some embodiments, the planarization process removes the gate electrode material (1804 of FIG. 18), the third dielectric material (1806 of FIG. 18), and the fourth dielectric material (1808 of FIG. 18). In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

As shown in cross-sectional view 2200 of FIG. 22, the dielectric stack (2104 of FIG. 21) may be selectively etched to remove portions of the dielectric stack. In some embodiments, the dielectric stack is not removed from over the gate dielectric 105 to prevent damage to the gate dielectric 105 . In such an embodiment, etching the dielectric stack forms one or more dielectric structures 306 that cover the gate At least one uppermost surface of the dielectric 105 has sidewalls forming openings 2204 extending through the one or more dielectric structures 306 to expose the upper surface of the gate electrode 107 . In some embodiments, this can be achieved by forming a fifth masking layer 2202 over the dielectric stack and then exposing the unmasked portion of the dielectric stack to an etchant 2206 that removes the unmasked portion of the dielectric stack The dielectric stack (2104 of Figure 21) is selectively etched.

As shown in cross-sectional view 2300 of FIG. 23, a salicide process is performed. The salicide process forms silicide 308 along the upper surface of the source region 104 , the upper surface of the drain region 108 and the upper surface of the gate electrode 107 . In some embodiments, the silicide 308 is back-shaped laterally relative to the edge of the source region 104, the edge of the drain region 108, and the edge of the gate electrode 107 covered by the one or more dielectric structures 306 . In some embodiments, the salicide process may be performed by depositing metal (eg, aluminum) into the source region 104, drain region 108, and gate electrode 107, followed by a high temperature anneal.

As shown in cross-sectional view 2400 of FIG. 24 , an interlayer dielectric (ILD) structure 208 is formed over substrate 102 , and a plurality of conductive interconnects (conductive contacts 210 to interconnects 212 ) are formed within ILD structure 208 . In some embodiments, the ILD structure 208 may include a plurality of stacked ILD layers formed over the substrate 102 . In some embodiments (not shown), the plurality of stacked ILD layers are separated by an etch stop layer (not shown). In some embodiments, the plurality of conductive interconnects may include conductive contacts 210 and interconnects 212 . In some embodiments, the plurality of conductive interconnects (conductive contacts 210 to interconnects 212 ) may be formed by forming the one or more ILD layers (eg, oxide) over the substrate 102 , a low-k dielectric, or an ultra-low-k dielectric); selectively perform the ILD layer Etching to form via holes and/or trenches within the ILD layer; forming conductive material (eg, copper, aluminum, etc.) within the via holes and/or trenches; and performing a planarization process (eg, a chemical mechanical planarization process) .

25 shows a flowchart of some embodiments of a method 2500 of forming an integrated wafer with high voltage transistor devices including recessed gate electrodes with gate extensions.

Although the disclosed method 2500 is shown and described herein as a series of acts or events, it is to be understood that the order in which these acts or events are shown should not be construed in a limiting sense. For example, certain acts may occur in a different order, and/or may occur concurrently with other acts or events than those shown and/or described herein. Additionally, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Furthermore, one or more of the actions depicted herein may be performed in one or more separate actions and/or phases.

At act 2502, one or more isolation structures are formed within the substrate. FIGS. 10A-11B illustrate cross-sectional views 1000 and 1100 and top views 1012 and 1102 of some embodiments corresponding to act 2502 .

At act 2504, the substrate is selectively etched to form gate base recesses within the substrate. FIGS. 12A-12B illustrate a cross-sectional view 1200 and a top view 1212 of some embodiments corresponding to act 2504 .

At act 2506, a well region and a drift region are formed within the substrate. FIGS. 13A-13B illustrate a cross-sectional view 1300 and a top view 1306 of some embodiments corresponding to act 2506 .

At act 2508, within the gate base recess and the one or more A gate dielectric is formed over the isolation structure. FIGS. 14A-14B illustrate a cross-sectional view 1400 and a top view 1402 of some embodiments corresponding to act 2508 .

At act 2510, one or more gate extension trenches are formed extending outwardly from the gate base recess into the one or more isolation structures. 15A-15C illustrate a cross-sectional view 1500 , a top view 1510 , and a three-dimensional view 1512 of some embodiments corresponding to act 2510 .

At act 2512, a gate electrode is formed within the gate base recess and the one or more gate extension trenches. FIGS. 16A-17B illustrate cross-sectional views 1600 and 1700 and top views 1604 and 1704 of some embodiments corresponding to act 2512 .

At act 2514, a gate stack is formed over the gate electrode. FIG. 18 shows a cross-sectional view 1800 of some embodiments corresponding to act 2514 .

At act 2516, the gate stack is patterned to form a patterned gate stack over the gate electrode. FIG. 19 shows a cross-sectional view 1900 of some embodiments corresponding to act 2516 .

At act 2518, the substrate is implanted according to the patterned gate stack to form source and drain regions on opposite sides of the gate electrode. FIG. 20 shows a cross-sectional view 2000 of some embodiments corresponding to act 2518 .

At act 2520, one or more layers are removed from the patterned gate stack to form a dielectric stack. FIG. 21 shows a cross-sectional view 2100 of some embodiments corresponding to act 2520 .

At act 2522, the dielectric stack is patterned to form one or more dielectric structures overlying the gate dielectric. 22 shows a cross-sectional view 2200 of some embodiments corresponding to act 2522.

At act 2524, a salicide process is performed. 23 shows a cross-sectional view 2300 of some embodiments corresponding to act 2524.

At act 2526, one or more conductive contacts are formed within an interlayer dielectric (ILD) layer formed over the gate electrode. FIG. 24 shows a cross-sectional view 2400 of some embodiments corresponding to act 2526 .

Accordingly, in some embodiments, the present disclosure is directed to an integrated wafer including a transistor device having a gate structure having a gate structure configured to provide a high breakdown voltage to the transistor device gate extension.

In some embodiments, the present disclosure pertains to an integrated wafer. The integrated wafer includes: a source region disposed in a substrate; a drain region disposed in the substrate and spaced apart from the source region along a first direction; a drift region, in the source region and the source region The drain regions are arranged in the substrate; a plurality of isolation structures are arranged in the drift region; and a gate electrode is arranged in the substrate, the gate electrode has a base region and a plurality of a gate extension part, the base region is disposed between the source region and the drift region, and the plurality of gate extension parts extend outward from the sidewall of the base region to between the plurality of isolation structures superior. In some embodiments, the plurality of isolation structures have outer sidewalls spaced from the drift region in a second direction perpendicular to the first direction. In some embodiments, the plurality of isolation structures extend beyond opposite sides of respective gate extensions of the plurality of gate extensions in a second direction perpendicular to the first direction, respectively. In some embodiments, the plurality of gate extensions are separated from each other by the plurality of isolation structures and by the drift region along a second direction perpendicular to the first direction. In some embodiments, the plurality of isolation structures are located between the plurality of gate extensions and the drain region. In some embodiments, the integrated wafer further includes: a gate dielectric, along the base region of the gate electrode The sidewalls and the lower surface of the isolation structures are provided, and the plurality of isolation structures have sidewalls that are in direct contact with the sidewalls of the gate dielectric. In some embodiments, the integrated chip further includes: a gate dielectric disposed along sidewalls and a lower surface of the base region of the gate electrode, and the plurality of isolation structures along the upper surface of the base A surface extends continuously from the gate dielectric to the drain region. In some embodiments, the plurality of isolation structures comprise one or more dielectric materials disposed within trenches in the substrate; and the plurality of gate extensions are disposed within the plurality of isolation structures within additional trenches formed on the surface. In some embodiments, the integrated chip further includes: a gate dielectric disposed along the sidewall and lower surface of the base region of the gate electrode; one or more dielectric structures disposed on the gate electrode over opposing outer edges of gate electrodes and over the gate dielectric; and an interlayer dielectric (ILD) disposed over the one or more dielectric structures and along the one or more dielectric structures The sidewalls of the dielectric structures are provided.

In other embodiments, the present disclosure relates to an integrated wafer. The integrated wafer includes: a source region, arranged in a substrate; a drain region, arranged in the substrate; a gate dielectric, lining the inner surface of the substrate; and a gate electrode, arranged in the substrate There is a base region and a plurality of gate extensions between the source region and the drain region, the base region is located on the gate dielectric, and the plurality of gate extensions extend from the gate sidewalls of the base region of the gate electrode protrude outward toward the drain region; and a plurality of isolation structures extending continuously between the gate dielectric and the drain region, the plurality of isolation structures An isolation structure surrounds one of the plurality of gate extensions, respectively. In some embodiments, the integrated wafer further includes: a drift region disposed in the substrate between the base region and the drain region, and the plurality of isolation structures are separated from each other by the drift region separated. In some embodiments, the drift region extends beyond opposite sides of the plurality of isolation structures in a first direction and in a second direction perpendicular to the first direction side. In some embodiments, the integrated wafer further includes: one or more dielectric structures disposed over opposing outer edges of the gate electrodes; an interlayer dielectric (ILD) disposed over the one above and along the sidewalls of the one or more dielectric structures; and a silicide, arranged along the upper surface of the gate electrode, the one or more dielectric structures covering the One or more portions of the gate electrode outside the silicide. In some embodiments, the one or more dielectric structures each include a first dielectric material, a second dielectric material overlying the first dielectric material, and sidewalls along the first dielectric material and a third dielectric material on the sidewalls of the second dielectric material. In some embodiments, the base region extends to a first depth below the upper surface of the substrate, and the plurality of gate extensions extend to a second depth below the upper surface of the substrate, the first depth The second depth is less than the first depth. In some embodiments, the plurality of isolation structures extend to a greater depth within the substrate than the gate dielectric. In some embodiments, the gate dielectric includes protrusions arranged between the base region and gate extensions of the plurality of gate extensions, the protrusions extending from above the base region The surface extends outwardly above the bottom of the gate extension. In some embodiments, both the bottom surface of the gate extension of the plurality of gate extensions and the upper surface of the gate dielectric and the upper surface of the isolation structure of the plurality of isolation structures touch.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a plurality of isolation structures in a substrate; selectively etching the substrate to form gate base grooves in the substrate; selectively etching the plurality of isolation structures, forming a plurality of gate extension trenches extending outward from the gate base groove; forming a conductive material in the gate base groove and the plurality of gate extension trenches to form gate electrodes; and at the gate Source and drain regions are formed on opposite sides of the electrode electrode. In some embodiments, the method further comprises: forming a gate dielectric within the gate base recess before selectively etching the plurality of isolation structures to form the plurality of gate extension trenches Electricity.

The features of several embodiments have been summarized above so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or implementing the embodiments described herein example of the same advantages. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure .

100: Integrated wafer

102: Substrate

102u: upper surface

104: source region

105: Gate dielectric

106: Gate structure

107: Gate electrode

107b: Base Area

107e: Gate extension

108: Drain region

109: Well District

110: Drift Zone

112: Isolation Structure

114: First Direction

116: Second direction

Claims (10)

An integrated wafer, comprising: a source region, arranged in a substrate; a drain region, arranged in the substrate and separated from the source region along a first direction; a drift region, in the source region and the source region The drain regions are arranged in the substrate and separated from the source region along the first direction; a plurality of isolation structures are arranged in the drift region; and a gate electrode is arranged in the In the substrate, wherein the gate electrode includes a base region and a plurality of gate extensions, the base region is disposed between the source region and the drift region, and the gate extensions extend from the base region. The sidewalls of the base region extend outwardly over the plurality of isolation structures, and wherein the plurality of isolation structures completely cover the sidewalls of the plurality of gate extensions facing the drain region. The integrated wafer of claim 1, wherein the plurality of isolation structures respectively extend beyond respective gate extensions of the plurality of gate extensions in a second direction perpendicular to the first direction opposite side. The integrated chip of claim 1, wherein the plurality of isolation structures are located between the plurality of gate extensions and the drain region. The integrated chip of claim 1, further comprising: a gate dielectric disposed along sidewalls and a lower surface of the base region of the gate electrode, wherein the plurality of isolation structures have a connection with the gate electrode The sidewall of the polar dielectric sidewall contacts. The integrated chip of claim 1, further comprising: a gate dielectric disposed along the sidewall and lower surface of the base region of the gate electrode, wherein the plurality of isolation structures are along the base upper surface from the gate dielectric The charge extends continuously to the drain region. The integrated chip according to claim 1, further comprising: a gate dielectric, disposed along the sidewall and lower surface of the base region of the gate electrode; one or more dielectric structures disposed on the gate electrode over opposing outer edges of the gate electrode and over the gate dielectric; and an interlayer dielectric disposed over the one or more dielectric structures and along the one or more dielectric structures The side walls of the structure are provided. An integrated wafer, comprising: a source region, arranged in a substrate; a drain region, arranged in the substrate; a gate dielectric, lining the inner surface of the substrate; and a gate electrode, arranged in the substrate Between the source region and the drain region and including a base region and a plurality of gate extensions, the base region is over the gate dielectric, wherein the plurality of gate extensions extend from the gate sidewalls of the base region of the gate electrode protrude outward toward the drain region; and a plurality of isolation structures extending continuously between the gate dielectric and the drain region, wherein the A plurality of isolation structures respectively surround one of the plurality of gate extensions, and wherein a bottom surface of the gate extension of the plurality of gate extensions and an upper surface of the gate dielectric and The upper surfaces of the isolation structures of the plurality of isolation structures are both in contact. The integrated wafer of claim 7, wherein the base region extends to a first depth below the upper surface of the substrate, and the plurality of gate extensions extend to a first depth below the upper surface of the substrate two depths, the second depth is less than the first depth. The integrated wafer of claim 7, wherein the gate dielectric includes protrusions arranged between the base region and the gate extension of the plurality of gate extensions, the A protrusion extends outwardly from the upper surface of the base region to above the bottom of the gate extension. A method for forming an integrated wafer, comprising: forming a plurality of isolation structures in a substrate; selectively etching the substrate to form gate base grooves in the substrate; selecting the plurality of isolation structures selectively etched to form a plurality of gate extension trenches extending outward from the gate base groove, wherein the plurality of isolation structures completely cover the plurality of gate extension trenches away from the gate base sidewalls of the recess; forming conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming source and drain regions on opposite sides of the gate electrode polar region.

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