TW202109894A - Integrated chip and method of forming the same - Google Patents

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

Description

High voltage device with gate extension

Today's integrated chip (IC) includes millions or billions of semiconductor devices formed on a semiconductor substrate (for example, silicon). Depending on the application of the integrated chip (IC), many different types of transistor devices can be used on the integrated chip. In recent years, the increasing market for cellular devices and radio frequency (RF) devices has led to a significant increase in the use of high voltage transistor devices. For example, since high voltage transistor devices can cope with high breakdown voltage (for example, greater than about 50 V) and high frequency, they are often used in power amplifiers in the RF transmit/receive chain.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are only examples and not intended to be limiting. For example, the formation of the first feature on the second feature or the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include the first feature An embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. This repeated use is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and/or configurations discussed by itself.

In addition, for ease of description, this article may use, for example, "beneath", "below", "lower", "above )", "upper" and other spatially relative terms are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. The terms of spatial relativity are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the figures. The device can have other orientations (rotated by 90 degrees or in other orientations), and the spatial relativity descriptors used herein can also be interpreted accordingly.

Integrated wafers often include transistors designed to operate at a variety of different voltages. The high voltage transistor is designed to operate at a high breakdown voltage (for example, a breakdown voltage greater than approximately 20 V, greater than approximately 50 V, or other suitable values). A common type of high voltage transistor is a laterally diffused MOSFET (LDMOS) device. The LDMOS device has a gate structure disposed on the substrate between the source region and the drain region. The gate structure is separated from the drain region by the drift region. The drift region includes a lightly doped region of the substrate (for example, a region where the doping concentration of the substrate is lower than the doping concentration of the source region and/or the doping concentration of the drain region).

During operation, a bias voltage can be applied to the gate structure to form an electric field that causes the channel region to extend under the gate structure and through the drift region. The breakdown voltage of an LDMOS device is usually proportional to the size and doping concentration of the drift region (for example, a larger drift region will bring about a larger breakdown voltage). However, if the electric field in the device is not uniform, the breakdown voltage of the transistor device may be negatively affected. For example, due to a spike in the electric field that may appear at the p-n junction between the drift region and the substrate, the breakdown voltage of the LDMOS may be negatively affected.

In some embodiments, the present disclosure relates to an integrated wafer including a transistor device having a gate electrode having a plurality of transistors configured to provide a high breakdown voltage to the transistor device. Gate extension. The gate electrode is arranged in the substrate between the source region and the drain region. The drift region is located between the gate electrode and the drain region. The plurality of gate extensions protrude laterally outward from the sidewall of the gate electrode and cross the drift region. The plurality of gate extensions are configured to generate an electric field in the drift region, which can spread the charge laterally along the p-n junction of the device. By expanding the charge in the lateral direction, the electric field along the surface of the substrate can be expanded, thereby reducing spikes in the electric field and increasing the breakdown voltage of the transistor device.

Figure 1 shows a three-dimensional view of some embodiments of an integrated wafer 100 having a high voltage transistor device that includes a gate electrode with a gate extension.

The integrated wafer 100 includes a gate structure 106 disposed in a substrate 102. In some embodiments, the gate structure 106 is recessed in the substrate 102. In some such embodiments, the gate structure 106 extends from below the upper surface 102 u of the substrate 102 to the upper surface 102 u of the substrate 102. A source region 104 is provided on a first side of the gate structure 106 and a drain region 108 is provided on a second side of the gate structure 106 opposite to the first side. The source region 104 and the drain region 108 are separated along the first direction 114 by the gate structure 106.

A drift region 110 is arranged between the gate structure 106 and the drain region 108 along the first direction 114. In some embodiments, a well region 109 may be provided in the substrate 102 below the gate structure 106 and the well region 109 contacts the drift region 110 in a lateral direction. One or more isolation structures 112 are provided in the drift region 110. The one or more isolation structures 112 extend in the first direction 114 between the gate structure 106 and the drain region 108 along the upper surface of the substrate 102. The one or more isolation structures 112 are separated from each other by the drift region 110 along the second direction 116 perpendicular to the first direction 114. In some embodiments, the sidewalls of the one or more isolation structures 112 extend parallel to each other along the first direction 114. In some embodiments, the one or more isolation structures 112 include one or more dielectric materials disposed in trenches in the substrate 102. In some embodiments, the one or more isolation structures 112 may include a shallow trench isolation (STI) structure.

The gate structure 106 includes a gate dielectric 105 and a gate electrode 107 on the gate dielectric 105. The gate electrode 107 includes a base region 107b and one or more gate extensions 107e. The base region 107b is separated from the drift region 110 by the gate dielectric 105. In some embodiments, the gate dielectric 105 continuously extends from a first side of the base region 107b to an opposite second side of the base region 107b. The one or more gate extensions 107e protrude laterally outward from the sidewall of the base region 107b of the gate electrode 107 into the one or more isolation structures 112. The one or more isolation structures 112 separate the one or more gate extensions 107e from the drift region 110 in the lateral direction and in the vertical direction. In some embodiments, the one or more gate extensions 107e extend through the sidewall of the gate dielectric 105.

During operation, a bias voltage may be applied to the gate electrode 107. The bias voltage causes the charges (for example, positive or negative charges) in the gate electrode 107 to form an electric field in the underlying substrate 102. Generally, because the surface field at the junction of the drift region 110 and the well region 109 is crowded, the maximum breakdown voltage of the transistor device may be limited by the junction edge breakdown effect. However, the electric field generated by the one or more gate extensions 107e expands the electric field in the lateral direction along the surface of the substrate 102 (for example, in the second direction 116). By expanding the electric field, the one or more gate extensions 107e will reduce the intensity of the electric field along the surface of the substrate 102, thereby enabling the transistor device to achieve a higher breakdown voltage.

Figures 2A to 2C show some additional embodiments of integrated wafers with high-voltage transistor devices that include recessed gate electrodes with gate extensions.

As shown in the cross-sectional view 200 of FIG. 2A, the integrated wafer includes a source region 104 and a drain region 108 disposed in the substrate 102. A drift region 110 is arranged between the source region 104 and the drain region 108. In some embodiments, the well region 109 may surround the source region 104, the drain region 108 and the drift region 110. In some embodiments, the substrate 102 and the well region 109 may have a first doping type (for example, p-type), and the source region 104, the drain region 108, and the drift region 110 may have a second doping type (for example, n type). In some embodiments, the drift region 110 may have a second doping type (for example, n-type), but the doping concentration is lower than that of the source region 104 and/or the drain region 108.

A gate electrode 107 is provided in the substrate 102 between the source region 104 and the drain region 108. The gate electrode 107 is separated from the drain region 108 by the drift region 110. The gate electrode 107 includes a base region 107b and one or more gate extensions 107e. The one or more gate extensions 107e extend outward from the base region 107b to directly above the drift region 110 in the first direction 114. The base area 107b is surrounded by the gate dielectric 105. The one or more gate extensions 107e are surrounded by one or more isolation structures 112 arranged in the drift region 110. In some embodiments, the one or more gate extensions 107e may extend directly above the upper surface of the one or more isolation structures 112 and the gate dielectric 105. In some embodiments, the one or more gate extensions 107e may have a bottom surface contacting both the upper surface of the gate dielectric 105 and the upper surface of the one or more isolation structures 112.

In some embodiments, the gate electrode 107 may include conductive materials, such as metals (for example, tungsten, aluminum, etc.), doped polysilicon, and the like. In some embodiments, the gate dielectric 105 and the one or more isolation structures 112 may include oxide (for example, silicon oxide), nitride (for example, silicon nitride), and the like.

In some embodiments, the base region 107b may have a first thickness 204 and the one or more gate extensions 107e may have a second thickness 206. In some embodiments, the second thickness 206 may be less than the first thickness 204. For example, in some embodiments, the second thickness 206 may be between 50% and approximately 90% of the first thickness 204. In some embodiments, the first thickness 204 may be between approximately 900 Angstroms (Å) and approximately 600 Å, between approximately 650 Å and approximately 750 Å, or other similar values. In other embodiments (not shown), the second thickness 206 may be approximately equal to the first thickness 204.

A plurality of conductive interconnects (conductive contacts 210 to interconnects 212) are provided in an inter-level dielectric (ILD) structure 208 on the substrate 102. In some embodiments, the plurality of conductive interconnects (conductive contact 210 to interconnect 212) may include one or more conductive contacts 210 coupled to interconnect 212. In some embodiments, the one or more conductive contacts 210 are electrically coupled to the source region 104, the drain region 108 and the gate electrode 107. In some embodiments, the plurality of conductive interconnects (conductive contact 210 to interconnect 212) may include one or more of copper, tungsten, aluminum, and the like. In some embodiments, the ILD structure 208 may include silicon dioxide, doped silicon dioxide (for example, carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphorous One or more of phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), etc.

FIG. 2B shows a top view 202 of the integrated wafer of FIG. 2A. The cross-sectional view 200 of FIG. 2A is taken along the section line A-A' of FIG. 2B.

As shown in the top view 202 of FIG. 2B, the one or more gate extensions 107e protrude outward from the sidewall of the base area 107b in the first direction 114, and the base area 107b extends beyond the sidewall in the second direction 116 One or more gate extensions 107e. The adjacent gate extension 107e of the one or more gate extensions 107e passes through both the drift region 110 and the part of at least two of the one or more isolation structures 112 along the second direction 116. Separate.

In some embodiments, the one or more isolation structures 112 extend continuously from the first end contacting the gate dielectric 105 to the second end contacting the drain region 108 along the first direction 114. In some embodiments, the one or more gate extensions 107 e are separated from the drain region 108 by the one or more isolation structures 112. In this embodiment, the one or more gate extensions 107e are separated from one end of the one or more isolation structures 112 by a non-zero distance d . In various embodiments, the non-zero distance d may be between approximately 400 µm and approximately 1,000 µm, between approximately 400 µm and approximately 750 µm, between approximately 250 µm and approximately 500 µm, or other suitable value ranges Inside.

FIG. 2C shows a cross-sectional view 216 of the integrated wafer taken along the section line B-B' of FIG. 2B.

As shown in the cross-sectional view 216, the one or more isolation structures 112 are disposed in a trench 218 formed by the inner surface 102i of the substrate 102. The gate extension 107e is disposed in the additional trench 220 formed by the inner surface 112i of the one or more isolation structures 112. This allows the one or more gate extensions 107e to be separated from each other along the second direction 116 by the drift region 110 and the one or more isolation structures 112.

As shown in the cross-sectional view 200 of FIG. 2A and the cross-sectional view 216 of FIG. 2C, there is a depletion region 214 along the p-n junction between the drift region 110 and the well region 109 and/or the substrate 102. The depletion region 214 allows an electric field to be formed along the p-n junction. Due to the bias voltage applied to the source region 104, the drain region 108, and/or the gate electrode 107, the electric field increases during the operation of the transistor device. However, the one or more gate extensions 107e can generate an electric field that spreads charges along the p-n junction.

For example, FIG. 2D shows a cross-sectional view 222 of the integrated wafer taken along the section line B-B' of FIG. 2B during the operation of the high-voltage transistor device.

As shown in the cross-sectional view 222 of FIG. 2D, during operation, a bias voltage may be applied to the one or more gate extensions 107e. The bias voltage causes the one or more gate extensions 107e to form an electric field extending into the well region 109 and the drift region 110. Due to the doping type of the well region 109 and the doping type of the drift region 110, the electric field causes the charges 224 and 226 with opposite polarities to be accumulated in the well region 109 and the drift region 110. For example, in some embodiments, negative charges 224 may be accumulated in the well region 109 and positive charges 226 may be accumulated in the drift region 110. The one or more gate extensions 107e can extend the charges 224 and 226 along the second direction 116 and beyond the outermost one of the one or more gate extensions 107e. Extending the charges 224 and 226 can increase the width of the depletion region 214 in the second direction 116 and reduce the spikes in the electric field along the surface of the substrate 102 (for example, make the surface electric field above the pn junction smaller than that corresponding to the breakdown voltage of the device). Critical electric field). By reducing the spikes in the electric field along the surface of the substrate 102, the breakdown voltage of the high voltage transistor device will increase.

Figure 3 shows a cross-sectional view of some additional embodiments of an integrated wafer 300 having a high voltage transistor device that includes a recessed gate electrode with a gate extension.

The integrated wafer 300 includes a recessed gate electrode 107 below the upper surface of the substrate 102. The gate electrode 107 is separated from the substrate 102 by the gate dielectric 105 and by one or more isolation structures 112. The gate electrode 107 includes a base area 107b and one or more gate extensions 107e, the base area 107b is disposed on the gate dielectric 105, and the one or more gate extensions 107e extend outward from the base area 107b It protrudes above the one or more isolation structures 112. The gate dielectric 105 extends along the sidewall and lower surface of the base region 107b. The one or more isolation structures 112 extend along the sidewall and the lower surface of the one or more gate extension portions 107e.

In some embodiments, the one or more isolation structures 112 may have a different thickness along the bottom of the one or more gate extensions 107e than along the sidewalls of the one or more gate extensions 107e ( For example, greater thickness). In some embodiments, the one or more isolation structures 112 may extend from the bottom of the one or more gate extensions 107e to below the bottommost surface of the gate dielectric 105 in the vertical direction. In some additional embodiments, the one or more isolation structures 112 may extend from a horizontal plane extending along the top of the gate dielectric 105 in a vertical direction to below the bottommost surface of the gate dielectric 105.

In some embodiments, the gate dielectric 105 may extend laterally directly above a portion of the one or more isolation structures 112, but not all. In some such embodiments, the gate dielectric 105 may line the upper surface and inner sidewalls of the one or more isolation structures 112. In some additional embodiments, the gate dielectric 105 may extend to a non-zero distance 302 below the upper surface of the one or more isolation structures 112. In this embodiment, the gate dielectric 105 can also line the outermost sidewall of the one or more isolation structures 112.

In some embodiments, the gate dielectric 105 may include a protrusion 304 extending outward from the upper surface of the gate dielectric 105 between the base region 107b and the one or more gate extensions 107e. In some embodiments, the protrusion 304 extends above the bottom surface of the one or more gate extensions 107e. In some embodiments, the protrusion 304 may have tapered sidewalls such that the width of the protrusion 304 decreases as the height above the upper surface increases. The protrusion 304 may be the result of an etching process used to form the one or more gate extensions 107e. For example, during the manufacturing process, the gate dielectric 105 may be formed along the inclined sidewalls of the one or more isolation structures 112. The one or more isolation structures 112 may then be etched to form gate extension trenches extending from the one or more isolation structures 112 to the inclined sidewalls. The over-etching of the gate dielectric 105 will cause the gate dielectric 105 to dent below the top of the inclined sidewall, thereby generating a protrusion 304. In other embodiments (not shown), the etching process can etch the gate dielectric 105 beyond the inclined sidewall, so that the gate dielectric 105 on the inclined sidewall is completely removed, and the resulting gate dielectric The mass 105 has an outer side wall separated from the side wall of the isolation structure 112 by a non-zero distance, and the side wall of the isolation structure 112 is located on the upper surface of the one or more isolation structures 112.

In some embodiments, one or more dielectric structures 306 are provided on the opposite outer edges of the gate electrode 107. In some embodiments, the one or more dielectric structures 306 continuously extend from a first outer edge directly above the base region 107b to a second outer edge directly above the source region 104. In some embodiments, the one or more dielectric structures 306 continuously extend from the third outer edge directly above the one or more gate extensions 107e of the gate electrode 107 to the drain region. 108 right above the fourth outer edge. In some embodiments, the one or more dielectric structures 306 may extend a non-zero distance 310 above the opposite edges of the gate electrode 107. In some embodiments, the non-zero distance 310 may be between approximately 200 Å and approximately 600 Å, between approximately 350 Å and approximately 500 Å, or within a range of other suitable values. In some embodiments, the one or more dielectric structures 306 may include one or more dielectric materials, such as oxides, nitrides, and the like.

A silicide 308 is arranged along the upper surface of the source region 104, the upper surface of the drain region 108, and the upper surface of the gate electrode 107. The silicide 308 is configured to provide a low resistance connection with the conductive interconnect (conductive contact 210 to interconnect 212). In various embodiments, the silicide 308 may include nickel silicide, titanium silicide, and the like. In some embodiments, the outer edge of the silicide 308 is laterally separated from the outer edge of the source region 104, the outer edge of the drain region 108, and the outer edge of the gate electrode 107, so that the source region 104, the drain The region 108 and the portion of the gate electrode 107 directly below the one or more dielectric structures 306 may not contain silicide 308.

A contact etch stop layer (CESL) 312 vertically separates the substrate 102 and the one or more dielectric structures 306 from the first interlayer dielectric (ILD) layer 208a. In some embodiments, the CESL 312 and/or the first ILD layer 208 a extends from directly above the one or more dielectric structures 306 to the sidewalls of the one or more dielectric structures 306. A second ILD layer 208b is provided on the first ILD layer 208a.

Figure 4 shows a top view of some additional embodiments of an integrated wafer 400 having a high voltage transistor device that includes a gate electrode with a gate extension.

The integrated wafer 400 includes a gate electrode 107 having a base region 107b and one or more gate extensions 107e. The one or more gate extensions 107e protrude outward from the base region 107b into the one or more isolation structures 112 along the first direction 114. The one or more gate extensions 107 e are spaced apart from each other along a second direction 116 perpendicular to the first direction 114.

In some embodiments, the one or more isolation structures 112 may be arranged along the second direction 116 at a pitch 402, and the closest gate extension 107e of the one or more gate extensions 107e is separated A distance 404 greater than the spacing 402. In this embodiment, the closest gate extension 107e of the one or more gate extensions 107e is separated by an isolation structure that does not include the gate extension. For example, in some embodiments, the one or more gate extensions 107e may include a first gate extension 107e ₁ and a second gate extension 107e ₂ , and the second gate extension 107e ₂ is closest to the gate electrode extending portion of the first gate electrode extending portion 107e _1. The first gate extension 107e _{1 is} disposed in the first isolation structure 112a and the second gate extension 107e _{2 is} disposed in the second isolation structure 112b. The third isolation structure 112c that does not surround the gate extension separates the first gate extension 107e ₁ from the second gate extension 107e ₂ .

Figures 5A to 5B show some additional embodiments of integrated wafers with high voltage transistor devices that include recessed gate electrodes with gate extensions.

As shown in the cross-sectional view 500 of FIG. 5A (taken along the section line A-A′ of FIG. 5B ), the integrated wafer includes a gate electrode 107 disposed on the substrate 102. The gate electrode 107 includes a base region 107b and one or more gate extensions 107e, and the one or more gate extensions 107e protrude outward from the base region 107b to the one or more isolation structures 112. The gate dielectric 105 continuously extends along the sidewalls and lower surface of the base region 107b and the sidewalls and lower surface of the one or more gate extension portions 107e. The gate dielectric 105 separates the one or more gate extensions 107e from the one or more isolation structures 112 in the vertical direction and in the lateral direction.

As shown in the top view 502 of FIG. 5B, the gate dielectric 105 extends around the outer periphery of the gate electrode 107 in a closed and uninterrupted ring. By using the gate dielectric 105 to surround both the base region 107b and the one or more gate extensions 107, one or more processing steps (e.g., one or Multiple lithography and/or etching processes). By eliminating one or more processing steps from the manufacturing process used to form the transistor device, the cost of forming an integrated wafer can be reduced.

Figures 6A to 6B show some additional embodiments of integrated wafers with high-voltage transistor devices that include gate electrodes with gate extensions.

As shown in the cross-sectional view 600 of FIG. 6A (taken along the section line A-A' of FIG. 6B), the integrated wafer includes a gate electrode 107 having a base region 107b and one or more gate extensions 107e. The gate dielectric 105 extends along the sidewall and lower surface of the base region 107b. The base area 107b protrudes outward from the upper surface 102u of the substrate 102. The one or more gate extensions 107e protrude outward from the sidewall of the base region 107b located on the upper surface 102u of the substrate 102 to directly above the one or more isolation structures 112.

As shown in the top view 602 of FIG. 6B (taken along the section line B-B' of FIG. 6A), the gate dielectric 105 extends around the outer periphery of the base region 107b in a closed and uninterrupted ring. By making the one or more gate extensions 107e protrude outward from the sidewalls of the base region 107b located on the upper surface 102u of the substrate 102, one or more processes can be eliminated from the manufacturing process for forming the transistor device Steps (for example, one or more lithography and/or etching processes). By eliminating one or more processing steps from the manufacturing process used to form the transistor device, the cost of forming an integrated wafer can be reduced.

FIG. 7 shows a cross-sectional view of some embodiments of an integrated wafer 700 having a high voltage transistor device area and a peripheral logic area.

The high voltage transistor device region 702 includes a high voltage transistor device including a gate electrode 107 disposed between the source region 104 and the drain region 108. The gate electrode 107 has a base area 107b and one or more gate extensions 107e extending outward from the base area 107b.

One or more dielectric structures 306 are provided on the opposite edges of the gate electrode 107. The one or more dielectric structures 306 respectively include a first dielectric material 706 and a second dielectric material 708 on the first dielectric material 706. In some embodiments, the third dielectric material 710 may extend along the outermost sidewall of the first dielectric material 706 and the outermost sidewall of the second dielectric material 708. In some embodiments, the first dielectric material 706 and the second dielectric material 708 may include different dielectric materials, and the third dielectric material 710 may be the same as the first dielectric material 706 or the second dielectric material 708. The same dielectric material. In various embodiments, the first dielectric material 706, the second dielectric material 708, and the third dielectric material 710 may include oxides (for example, silicon dioxide), nitrides (for example, silicon nitride), and carbides. (For example, silicon carbide) one or more of the others.

The peripheral logic area 704 includes one or more additional transistor devices. The one or more additional transistor devices include a gate structure 712 that is arranged between the source region 714 and the drain region 716 and is laterally surrounded by one or more sidewall spacers 728. The gate structure 712 includes a gate dielectric structure 717 that separates the gate electrode 722 from the substrate 102. One or more overlying dielectric layers 724 to 726 may be provided on the gate electrode 722. In some embodiments, the gate dielectric structure 717 may include a first gate dielectric material 718 and a second gate dielectric material 720 on the first gate dielectric material 718. In some embodiments, the first gate dielectric material 718 may be the same material as the first dielectric material 706, and the second gate dielectric material 720 may be the same material as the second dielectric material 708, and so The one or more sidewall spacers 728 may be the same material as the third dielectric material 710. In some embodiments, the first gate dielectric material 718 may have substantially the same thickness as the first dielectric material 706 and the second gate dielectric material 720 may have substantially the same thickness as the second dielectric material 708. thickness.

Figure 8 shows a top view of some additional embodiments of an integrated wafer 800 having a high voltage transistor device that includes a recessed gate electrode with gate extensions.

The integrated wafer 800 includes a drain region 108 surrounded by source regions 104a to 104b on the opposite side. The gate structures 106a to 106b are also arranged along opposite sides of the drain region 108 and separate the drain region 108 from the source regions 104a to 104b, respectively. The gate structures 106 a to 106 b respectively include a base region 107 and one or more gate extensions 107 e extending from the base region 107 b toward the drain region 108. In some embodiments, the body regions 802a to 802b may be separated from the gate structures 106a to 106b by the source regions 104a to 104b.

In some embodiments, the source regions 104a-104b are electrically coupled together and the gate structures 106a-106b are electrically coupled together. In some additional embodiments, the gate structures 106a to 106b, the source regions 104a to 104b, and the body regions 802a to 802b are substantially symmetrical about the line 804 that bisects the drain region 108.

During operation, the charge in the drift region 110 is separated from the charge in the gate electrode 107 by both the gate dielectric 105 and the one or more STI regions 112. Since the gate electrode extension 107e expands the charge in the drift region 110 in the lateral direction, the gate electrode extension 107e increases the capacitance between the drift region 110 and the gate electrode 107.

9A to 9B show some additional embodiments of integrated wafers with high voltage transistor devices that include recessed gate electrodes with gate extensions.

As shown in the cross-sectional view 900 of FIG. 9A, a gate electrode 107 is provided in the substrate 102 between the source region 104 and the drain region 108. The gate electrode 107 includes a base region 107 b surrounded by a gate dielectric 105 and one or more gate extensions 107 e surrounded by one or more isolation structures 112. In some embodiments, the gate electrode 107 extends into the substrate 102 to a first depth 902. In some embodiments, the first depth 902 may be between approximately 200 Å and approximately 800 Å, between approximately 500 Å and approximately 700 Å, or within a range of other suitable values. In some embodiments, the gate dielectric 105 may have a thickness 904 between approximately 700 Å and approximately 1,000 Å, between approximately 800 Å and approximately 900 Å, or other suitable values.

In some embodiments, the source region 104 and the drain region 108 are surrounded by one or more additional isolation structures 906 in the lateral direction. The one or more additional isolation structures 906 are separated from the one or more isolation structures 112 by the source region 104 and the drain region 108. In some embodiments, the one or more isolation structures 112 extending into the substrate 102 to the second depth 908 and the one or more additional isolation structures 906 are substantially the same. In some embodiments, the second depth 908 may be between approximately 2,000 Å and approximately 3,000 Å, between approximately 2,000 Å and approximately 2,500 Å, or within a range of other suitable values. As shown in the top view 910 of FIG. 9B, in some embodiments, the one or more additional isolation structures 906 may be wrapped around the transistor device in a closed loop manner.

Figures 10A to 24 show some embodiments of a method of forming an integrated wafer with a high-voltage transistor device that includes a recessed gate electrode with a gate extension. Although FIGS. 10A to 24 are described for one method, it should be understood that the structure disclosed in FIGS. 10A to 24 is not limited to this method, but may exist as a structure independent of the method.

As shown in the cross-sectional view 1000 of FIG. 10A, the substrate 102 is patterned to form one or more isolation trenches 1002. In various embodiments, the substrate 102 can be any type of semiconductor body (for example, silicon, SiGe, silicon-on-insulator (SOI), etc.), such as a semiconductor wafer and/or a semiconductor wafer located on the wafer. Or multiple dies, and any other type of semiconductor and/or epitaxial layer associated with the wafer. The one or more isolation trenches 1002 are formed by the sidewall and horizontally extending surface of the substrate 102. As shown in the top view 1012 of FIG. 10B, in some embodiments, the one or more isolation trenches 1002 include rectangular-shaped trenches that extend parallel to each other along the first direction 114 and extend along the first direction 114. The second directions 116 that are perpendicular to the direction 114 are spaced apart from each other.

In some embodiments, the one or more isolation trenches 1002 may be formed by selectively exposing the substrate 102 to the first etchant 1004 according to the first shielding layer 1006. In some embodiments, the first masking layer 1006 may include a hard mask including a first hard mask layer 1008 and a second hard mask layer 1010 located on the first hard mask layer 1008. In some embodiments, the first hard mask layer 1008 includes a first dielectric material (eg, oxide, nitride, etc.) and the second hard mask layer 1010 includes a second dielectric material different from the first dielectric material. Material (for example, oxide, nitride, etc.). In some embodiments, the first etchant 1004 may include a dry etchant. For example, in some embodiments, the first etchant 1004 may include an oxygen etchant.

As shown in the cross-sectional view 1100 of FIG. 11A, an isolation structure 112 is formed in the one or more isolation trenches 1002. As shown in the top view 1102 of FIG. 11B, the one or more isolation structures 112 are spaced apart from each other along the second direction 116. In some embodiments, the one or more isolation structures 112 may be formed by forming one or more dielectric materials in the one or more isolation trenches 1002. In some embodiments, the one or more dielectric materials may include oxides, nitrides, and the like. In some embodiments, the one or more dielectric materials may be formed by a deposition process (for example, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD process, etc.). In some embodiments, the one or more dielectric materials may be formed in the one or more isolation trenches 1002 before removing the entire first shielding layer (1006 of FIG. 10A). A planarization process (for example, a chemical mechanical planarization process) may then be performed to remove excess dielectric material from outside the one or more isolation trenches 1002 in the lateral direction. In some embodiments, the one or more isolation structures 112 may be combined with the formation of additional isolation structures (not shown) that provide isolation between adjacent transistor devices (for example, as shown in FIGS. 9A to 9B). Show) at the same time.

As shown in the cross-sectional view 1200 of FIG. 12A, a gate base groove 1202 is formed in the substrate 102. In some embodiments, the gate base groove 1202 may also extend into the one or more isolation structures 112. In some embodiments, the gate base groove 1202 extends into the substrate 102 to a first depth 1208, and the first depth 1208 is smaller than the second depth 1210 of the one or more isolation structures 112. The gate base groove 1202 is formed by one or more sidewalls 1202s _{1 of the} substrate 102 and a horizontally extending surface 1202h ₁ . In some embodiments, the gate base groove 1202 may be further formed by one or more sidewalls 1202s ₂ and horizontally extending surfaces 1202h _{2 of} the one or more isolation structures 112. As shown in the top view 1212 of FIG. 12B, the gate base groove 1202 continuously extends beyond the opposite sidewalls of the one or more isolation structures 112 in the second direction 116.

In some embodiments, the gate base groove 1202 may be formed by selectively exposing the substrate 102 to the second etchant 1204 according to the second shielding layer 1206. In various embodiments, the second shielding layer 1206 may include a hard mask layer, a photosensitive material (for example, lithography glue), and the like. In some embodiments, the second etchant 1204 may include a dry etchant. For example, in some embodiments, the second etchant 1204 may include an oxygen plasma etchant.

As shown in the cross-sectional view 1300 of FIG. 13A and the top view 1306 of FIG. 13B, a well region 109 and a drift region 110 are formed in the substrate 102. The drift region 110 laterally surrounds the one or more isolation structures 112 and extends below the one or more isolation structures 112 in the vertical direction. The well region 109 adjoins the drift region 110 in the vertical direction and/or laterally. In some embodiments, the well region 109 may be formed by injecting a first dopant species into the substrate 102 and then a second dopant species 1302 may be injected into the substrate 102 according to the third shielding layer 1304. To form a drift region 110. In various embodiments, the first dopant species may include a first doping type (for example, formed of p-type dopants such as boron, aluminum, etc.) and the second dopant species 1302 may include a second doping type (For example, it is formed of n-type dopants such as phosphorus and arsenic). In some embodiments, the third shielding layer 1304 may include a photosensitive material (for example, lithographic glue). In some alternative embodiments, the well region 109 and/or the drift region 110 may be formed before the one or more isolation structures 112 are formed.

As shown in the cross-sectional view 1400 of FIG. 14A and the top view 1402 of FIG. 14B, a gate dielectric 105 is formed on the substrate 102. In some embodiments, the gate dielectric 105 is formed in the gate base groove 1202 and on the substrate 102 and the one or more isolation structures 112. In some embodiments, the gate dielectric 105 may include oxide, nitride, and the like. In some embodiments, the gate dielectric 105 may be formed by a deposition process (for example, a CVD process, a PE-CVD process, etc.).

As shown in the cross-sectional view 1500 of FIG. 15A, one or more gate extension trenches 1502 are formed in the one or more isolation structures 112. The one or more gate extension trenches 1502 extend into the one or more isolation structures 112 to a third depth 1504 that is less than the second depth 1210. In some embodiments, the third depth 1504 may also be smaller than the first depth 1208 of the gate base groove 1202. In some embodiments, the one or more isolation structures 112 extend beyond the one or more gate extension trenches 1502 by a distance d , so that the one or more gate extension trenches 1502 are separated from the one or more gate extension trenches 1502. The sidewalls and horizontally extending surfaces of the isolation structure 112 are formed. FIG. 15B shows a top view 1510 of the cross-sectional view 1500 of FIG. 15A. As shown in the top view 1510, the one or more gate extension trenches 1502 extend outward from different positions of the gate base groove 1202.

In some embodiments, the one or more gates may be formed by selectively exposing the gate dielectric 105 and the one or more isolation structures 112 to the third etchant 1506 according to the fourth shielding layer 1508 Polar extension trench 1502. In various embodiments, the fourth shielding layer 1508 may include a hard mask layer, a photosensitive material (for example, lithography glue), and the like. In some embodiments, the third etchant 1506 may include a dry etchant. In some alternative embodiments (not shown), the gate extension trench 1502 may be formed at the same time as the gate base groove 1202. In some such embodiments, an etchant having a relatively low etching selectivity between silicon and silicon oxide (for example, _{a dry etchant containing CF 4} ) may be used. FIG. 15C shows a three-dimensional view 1512 of the cross-sectional view of FIG. 15A and a top view 1510 of FIG. 15B after the fourth shielding layer 1508 is removed.

As shown in the cross-sectional view 1600 of FIG. 16A and the top view 1604 of FIG. 16B, a gate material 1602 is formed in the gate base groove 1202 and the one or more gate extension trenches 1502. In some embodiments, the gate material 1602 may be formed to extend from the gate base groove 1202 and the one or more gate extension trenches 1502 to directly above the upper surface of the substrate 102. In some embodiments, the gate material 1602 may include polysilicon, metal, and the like. In some embodiments, the gate material 1602 may be formed by a deposition process (for example, a CVD process, a PE-CVD process, etc.) and/or a plating process (for example, an electroplating process, an electroless plating process, etc.).

As shown in the cross-sectional view 1700 of FIG. 17A, by removing excess gate material (1602 in FIG. 16) and the gate dielectric 105 from the substrate 102, a planarization process is performed along the line 1702 to form the gate electrode 107. As shown in the top view 1704 of FIG. 17B, the gate electrode 107 includes a base region 107b and laterally protrudes from the sidewall of the gate electrode 107 forming the base region 107b to directly above the one or more isolation structures 112 One or more gate extensions 107e. In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

As shown in the cross-sectional view 1800 of FIG. 18, a gate stack 1802 is formed on the substrate 102. The gate stack 1802 extends beyond the opposite side of the gate electrode 107. In some embodiments, the gate stack 1802 may include a first dielectric material 706, a second dielectric material 708 on the first dielectric material 706, and a gate electrode material on the second dielectric material 708 1804, a third dielectric material 1806 on the gate electrode material 1804, and a fourth dielectric material 1808 on the third dielectric material 1806.

As shown in the cross-sectional view 1900 of FIG. 19, the gate stack (1802 of FIG. 18) is patterned to form a patterned gate stack 1902. In some embodiments, after patterning the gate stack (1802 of FIG. 18), one or more sidewall spacers 1904 are formed along opposite sides of the patterned gate stack 1902. The patterned gate stack 1902 exposes the source region 1906 and the drain region 1908 of the substrate 102 on opposite sides of the gate electrode 107. In some embodiments (not shown), the gate stack may be patterned to form an additional gate stack in the peripheral logic region on another part of the substrate (eg, as shown in FIG. 7).

As shown in the cross-sectional view 2000 of FIG. 20, one or more dopant species 2002 are implanted into the substrate 102 to form a source region 104 and a drain region 108 on opposite sides of the gate electrode 107. In some embodiments, the one or more dopant species 2002 may be selectively implanted into the substrate 102 according to the patterned gate stack 1902. In this embodiment, the source region 104 is formed in the source region 1906 and the drain region 108 is formed in the drain region 1908. In various embodiments, the one or more dopant species 2002 may include n-type dopants (eg, phosphorus, arsenic, etc.) or p-type dopants (eg, boron, aluminum, etc.). In some embodiments, annealing may be performed after implanting the one or more dopant species 2002 into the substrate 102 to further drive the dopants into the substrate 102.

As shown in the cross-sectional view 2100 of FIG. 21, a planarization process (along line 2102) is performed on the patterned gate stack (1902 of FIG. 20) to remove one or more layers of the patterned gate stack and form a dielectric stack 2104. In some embodiments, the planarization process removes the gate electrode material (1804 in FIG. 18), the third dielectric material (1806 in FIG. 18), and the fourth dielectric material (1808 in FIG. 18). In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

As shown in the cross-sectional view 2200 of FIG. 22, the dielectric stack (2104 of FIG. 21) may be selectively etched to remove portions of the dielectric stack. In some embodiments, the dielectric stack is not removed from the gate dielectric 105 to prevent damage to the gate dielectric 105. In this embodiment, etching the dielectric stack will form one or more dielectric structures 306 that cover at least one uppermost surface of the gate dielectric 105 and have openings. 2204, the opening 2204 extends through the one or more dielectric structures 306 to expose the upper surface of the gate electrode 107. In some embodiments, it can be achieved by forming a fifth shielding layer 2202 over the dielectric stack and then exposing the unshielded portion of the dielectric stack to an etchant 2206 that removes the unshielded portion of the dielectric stack. The dielectric stack (2104 in FIG. 21) is selectively etched.

As shown in the cross-sectional view 2300 of FIG. 23, a salicide process is performed. The salicide process forms a silicide 308 along the upper surface of the source region 104, the upper surface of the drain region 108, and the upper surface of the gate electrode 107. In some embodiments, the silicide 308 is reshaped laterally with respect to the edge of the source region 104, the edge of the drain region 108, and the edge of the gate electrode 107 covered by the one or more dielectric structures 306 . In some embodiments, the salicide process can be performed by depositing metal (for example, aluminum) into the source region 104, the drain region 108, and the gate electrode 107, followed by high temperature annealing.

As shown in the cross-sectional view 2400 of FIG. 24, an interlayer dielectric (ILD) structure 208 is formed on the substrate 102, and a plurality of conductive interconnects (conductive contacts 210 to interconnects 212) are formed in the ILD structure 208. In some embodiments, the ILD structure 208 may include a plurality of stacked ILD layers formed on the substrate 102. In some embodiments (not shown), the plurality of stacked ILD layers are separated by an etch stop layer (not shown). In some embodiments, the plurality of conductive interconnects may include conductive contacts 210 and interconnects 212. In some embodiments, the plurality of conductive interconnects (the conductive contact 210 to the interconnect 212) can be formed by forming the one or more ILD layers (for example, oxide , Low-k dielectric or ultra-low-k dielectric); selectively etching the ILD layer to form via holes and/or trenches in the ILD layer; in the via holes and / Or forming a conductive material (for example, copper, aluminum, etc.) in the trench; and performing a planarization process (for example, a chemical mechanical planarization process).

Figure 25 shows a flowchart of some embodiments of a method 2500 of forming an integrated wafer with a high voltage transistor device that includes a recessed gate electrode with a gate extension.

Although the disclosed method 2500 is shown and described herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as having a restrictive meaning. For example, certain actions may occur in a different order, and/or may occur simultaneously with other actions or events than those shown and/or described herein. In addition, not all of the illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions illustrated herein may be performed in one or more separate actions and/or stages.

At act 2502, one or more isolation structures are formed within the substrate. 10A-11B show cross-sectional views 1000 and 1100 and top views 1012 and 1102 of some embodiments corresponding to action 2502.

At act 2504, the substrate is selectively etched to form gate base grooves in the substrate. 12A to 12B show a cross-sectional view 1200 and a top view 1212 of some embodiments corresponding to action 2504.

At action 2506, a well zone and a drift zone are formed in the substrate. FIGS. 13A to 13B show a cross-sectional view 1300 and a top view 1306 of some embodiments corresponding to action 2506.

At act 2508, a gate dielectric is formed in the gate base recess and over the one or more isolation structures. 14A to 14B show a cross-sectional view 1400 and a top view 1402 of some embodiments corresponding to action 2508.

At act 2510, one or more gate extension trenches extending outward from the gate base groove into the one or more isolation structures are formed. 15A to 15C show a cross-sectional view 1500, a top view 1510, and a three-dimensional view 1512 of some embodiments corresponding to action 2510.

At act 2512, a gate electrode is formed in the gate base groove and the one or more gate extension trenches. 16A to 17B show cross-sectional views 1600 and 1700 and top views 1604 and 1704 of some embodiments corresponding to act 2512.

At act 2514, a gate stack is formed over the gate electrode. FIG. 18 shows a cross-sectional view 1800 of some embodiments corresponding to act 2514.

At act 2516, the gate stack is patterned to form a patterned gate stack over the gate electrode. FIG. 19 shows a cross-sectional view 1900 of some embodiments corresponding to act 2516.

At act 2518, the substrate is implanted according to the patterned gate stack to form source and drain regions on opposite sides of the gate electrode. FIG. 20 shows a cross-sectional view 2000 of some embodiments corresponding to act 2518.

At act 2520, one or more layers are removed from the patterned gate stack to form a dielectric stack. FIG. 21 shows a cross-sectional view 2100 of some embodiments corresponding to act 2520.

At act 2522, the dielectric stack is patterned to form one or more dielectric structures covering the gate dielectric. FIG. 22 shows a cross-sectional view 2200 of some embodiments corresponding to act 2522.

At act 2524, a self-aligned silicide process is performed. FIG. 23 shows a cross-sectional view 2300 of some embodiments corresponding to act 2524.

At act 2526, one or more conductive contacts are formed in the interlayer dielectric (ILD) layer formed over the gate electrode. FIG. 24 shows a cross-sectional view 2400 of some embodiments corresponding to act 2526.

Therefore, in some embodiments, the present disclosure relates to an integrated wafer including a transistor device having a gate structure having a structure configured to provide a high breakdown voltage to the transistor device Gate extension.

In some embodiments, the present disclosure relates to an integrated wafer. The integrated wafer includes: a source region arranged in a substrate; a drain region arranged in the substrate and separated from the source region along a first direction; a drift region in the source region and The drain regions are arranged in the substrate; a plurality of isolation structures are arranged in the drift region; and a gate electrode is arranged in the substrate, the gate electrode has a base region and a plurality of A gate extension, the base region is disposed between the source region and the drift region, and the plurality of gate extensions extend outward from the sidewall of the base region to one of the plurality of isolation structures on. In some embodiments, the plurality of isolation structures have outer sidewalls that are separated from the drift region along a second direction perpendicular to the first direction. In some embodiments, the plurality of isolation structures respectively extend beyond opposite sides of corresponding ones of the plurality of gate extensions in a second direction perpendicular to the first direction. In some embodiments, the plurality of gate extensions are separated from each other by the plurality of isolation structures and by the drift region in a second direction perpendicular to the first direction. In some embodiments, the plurality of isolation structures are located between the plurality of gate extensions and the drain region. In some embodiments, the integrated wafer further includes: a gate dielectric, which is disposed along the sidewall and the lower surface of the base region of the gate electrode, and the plurality of isolation structures are connected to the gate electrode The side wall of the dielectric is in direct contact with the side wall. In some embodiments, the integrated wafer further includes a gate dielectric, which is arranged along the sidewall and the lower surface of the base region of the gate electrode, and the plurality of isolation structures are arranged along the upper surface of the substrate. The surface extends continuously from the gate dielectric to the drain region. In some embodiments, the plurality of isolation structures includes one or more dielectric materials disposed in trenches in the substrate; and the plurality of gate extensions are disposed in the plurality of isolation structures. In the additional trenches formed on the surface. In some embodiments, the integrated wafer further includes: a gate dielectric, which is arranged along the sidewall and the lower surface of the base area of the gate electrode; one or more dielectric structures are arranged on the On the opposite outer edges of the gate electrode and on the gate dielectric; and an interlayer dielectric (ILD) disposed on the one or more dielectric structures and along the one or more The sidewalls of a dielectric structure are provided.

In other embodiments, the present disclosure relates to an integrated wafer. The integrated wafer includes: a source region arranged in the substrate; a drain region arranged in the substrate; a gate dielectric lining the inner surface of the substrate; a gate electrode arranged in the substrate Between the source region and the drain region, there is a base region and a plurality of gate extensions, the base region is located on the gate dielectric, and the plurality of gate extensions extend from the The sidewalls of the base region of the gate electrode protrude outward toward the drain region; and a plurality of isolation structures extending continuously between the gate dielectric and the drain region, the plurality The isolation structure respectively surrounds one of the plurality of gate extensions. In some embodiments, the integrated wafer further includes a drift region, which is provided in the substrate between the base region and the drain region, and the plurality of isolation structures are connected to each other through the drift region. Separate. In some embodiments, the drift region extends beyond opposite sides of the plurality of isolation structures in a first direction and in a second direction perpendicular to the first direction. In some embodiments, the integrated wafer further includes: one or more dielectric structures disposed on opposite outer edges of the gate electrode; and an interlayer dielectric (ILD) disposed on the one Or a plurality of dielectric structures are disposed along the sidewalls of the one or more dielectric structures; and silicides are arranged along the upper surface of the gate electrode, and the one or more dielectric structures cover the One or more parts of the gate electrode located outside the silicide. In some embodiments, the one or more dielectric structures respectively include a first dielectric material, a second dielectric material located on the first dielectric material, and sidewalls along the first dielectric material And the third dielectric material of the sidewall of the second dielectric material. In some embodiments, the base region extends to a first depth below the upper surface of the substrate, and the plurality of gate extensions extend to a second depth below the upper surface of the substrate, the first The second depth is smaller than the first depth. In some embodiments, the plurality of isolation structures extend within the substrate to a depth greater than that of the gate dielectric. In some embodiments, the gate dielectric includes protrusions arranged between the base region and the gate extensions of the plurality of gate extensions, and the protrusions extend from above the base region. The surface extends outward to above the bottom of the gate extension. In some embodiments, both the bottom surface of the gate extension of the plurality of gate extensions and the upper surface of the gate dielectric and the upper surface of the isolation structure of the plurality of isolation structures contact.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a plurality of isolation structures in a substrate; selectively etching the substrate to form a gate base groove in the substrate; selectively etching the plurality of isolation structures, To form a plurality of gate extension trenches extending outward from the gate base groove; forming a conductive material in the gate base groove and the plurality of gate extension trenches to form gate electrodes; and A source region and a drain region are formed on opposite sides of the gate electrode. In some embodiments, the method further includes: before selectively etching the plurality of isolation structures to form the plurality of gate extension trenches, forming a gate dielectric in the gate base groove Electricity.

The features of several embodiments are summarized above, so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose as the embodiments described herein and/or achieve the implementations described herein Example of the same advantages. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations in this article without departing from the spirit and scope of the present disclosure. .

100, 300, 400, 700, 800: integrated wafer 102: substrate 102i, 112i: inner surface 102u: upper surface 104, 104a, 104b, 714: source region 105: gate dielectric 106, 106a, 106b, 712: gate structure 107, 722: gate electrode 107b: base region 107e: gate extension 107e ₁ : first gate extension 107e ₂ : second gate extension 108, 716: drain region 109: well Region 110: drift region 112: isolation structure 112a: first isolation structure 112b: second isolation structure 112c: third isolation structure 114: first direction 116: second direction 200, 216, 222, 500, 600, 900, 1000 , 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400: Sectional view 202, 502, 602, 910, 1012, 1102, 1212, 1306, 1402, 1510, 1604, 1704: top view 204: first thickness 206: second thickness 208: interlayer dielectric (ILD) structure 208a: first ILD layer 208b: second ILD layer 210: conductive contact 212: interconnection 214: depletion region 218: trench 220: additional trench 224: negative charge 226: positive charge 302, 310: non-zero distance 304: protrusion 306: dielectric structure 308: silicide 312: contact etching stop layer (CESL) 402: pitch 404: distance 702 : High voltage transistor device area 704: Peripheral logic area 706: First dielectric material 708: Second dielectric material 710: Third dielectric material 717: Gate dielectric structure 718: First gate dielectric material 720 : Second gate dielectric material 724, 726: overlying dielectric layer 728, 1904: sidewall spacers 802a, 802b: body regions 804, 1702, 2102: lines 902, 1208: first depth 904: thickness 906: Additional isolation structure 908: second depth 1002: isolation trench 1004: first etchant 1006: first masking layer 1008: first hard mask layer 1010: second hard mask layer 1202: gate base groove 1204: first Two etchants 1202h ₁ , 1202h ₂ : horizontal extension surface 1202s ₁ , 1202s ₂ : sidewall 1206: second shielding layer 1210: second depth 1302: second dopant species 1304: third shielding layer 1502: gate extension trench 1504: third depth 1506: third etchant 1508: fourth masking layer 1512: three-dimensional view 1602: gate material 1802: gate stack 1804: gate electrode material 1806: third dielectric material 180 8: fourth dielectric material 1902: patterned gate stack 1906: source region 1908: drain region 2002: dopant species 2104: dielectric stack 2202: fifth shielding layer 2204: opening 2206: etchant 2500: Methods 2502, 2504, 2506, 2508, 2510, 2512, 2514, 2516, 2518, 2520, 2522, 2524, 2526: Action AA´: Section line BB´: Section line d : Distance

Read the following detailed description in conjunction with the accompanying drawings to best understand all aspects of the present disclosure. It should be noted that the various features are not drawn to scale according to standard practices in this industry. In fact, in order to make the discussion clear, the size of various features can be increased or decreased arbitrarily. Figure 1 shows a three-dimensional view of some embodiments of an integrated wafer with a high voltage transistor device that includes a gate electrode with a gate extension. Figures 2A to 2D show some additional embodiments of integrated wafers with high-voltage transistor devices that include recessed gate electrodes with gate extensions. Figure 3 shows a cross-sectional view of some additional embodiments of an integrated wafer with a high voltage transistor device that includes a recessed gate electrode with a gate extension. Figure 4 shows a top view of some additional embodiments of an integrated wafer with a high voltage transistor device including a gate electrode with a gate extension. Figures 5A to 5B show some additional embodiments of integrated wafers with high voltage transistor devices that include recessed gate electrodes with gate extensions. 6A to 6B show some additional embodiments of integrated wafers with high voltage transistor devices that include partially recessed gate electrodes with gate extensions. Figure 7 shows a cross-sectional view of some embodiments of an integrated wafer having a high voltage transistor device area and a peripheral logic area. Figure 8 shows top views of some additional embodiments of integrated wafers with high voltage transistor devices that include gate electrodes with gate extensions. 9A to 9B show some additional embodiments of integrated wafers with high voltage transistor devices that include recessed gate electrodes with gate extensions. 10A-24 show cross-sectional views of some embodiments of a method of forming an integrated wafer with a high-voltage transistor device that includes a recessed gate electrode with a gate extension. Figure 25 shows a flowchart of some embodiments of a method of forming an integrated wafer with a high voltage transistor device that includes a recessed gate electrode with a gate extension.

100: Integrated chip

102: Base

102u: upper surface

104: source region

105: gate dielectric

106: Gate structure

107: gate electrode

107b: Basic area

107e: gate extension

108: Drain region

109: Well Area

110: Drift Zone

112: Isolation structure

114: first direction

116: second direction

Claims (20)

An integrated wafer including: The source area is set in the substrate; The drain region is arranged in the substrate and separated from the source region along the first direction; A drift region, arranged in the substrate between the source region and the drain region; A plurality of isolation structures are arranged in the drift zone; and The gate electrode is disposed in the substrate, wherein the gate electrode includes a base region and a plurality of gate extensions, the base region is disposed between the source region and the drift region, and the multiple A gate extension part extends outward from the sidewall of the base area to above the plurality of isolation structures. The integrated wafer according to claim 1, wherein the plurality of isolation structures have outer sidewalls, and the outer sidewalls are separated from the drift region in a second direction perpendicular to the first direction. The integrated wafer according to claim 1, wherein the plurality of isolation structures respectively extend beyond the corresponding ones of the plurality of gate extensions in a second direction perpendicular to the first direction Opposite side. The integrated wafer according to claim 1, wherein the plurality of gate extensions are separated from each other by the plurality of isolation structures and by the drift region in a second direction perpendicular to the first direction. The integrated chip according to claim 1, wherein the plurality of isolation structures are located between the plurality of gate extensions and the drain region. The integrated wafer as described in claim 1, further including: The gate dielectric is arranged along the sidewalls and the lower surface of the base region of the gate electrode, wherein the plurality of isolation structures have sidewalls contacting the sidewalls of the gate dielectric. The integrated wafer as described in claim 1, further including: The gate dielectric is arranged along the sidewall and the lower surface of the base region of the gate electrode, wherein the plurality of isolation structures continuously extend from the gate dielectric to the upper surface of the substrate The drain region. The integrated wafer as described in claim 1, Wherein the plurality of isolation structures include one or more dielectric materials disposed in trenches in the substrate; and The plurality of gate extensions are arranged in additional trenches formed by the inner surfaces of the plurality of isolation structures. The integrated wafer as described in claim 1, further including: The gate dielectric is arranged along the sidewall and the lower surface of the base area of the gate electrode; One or more dielectric structures disposed on the opposite outer edges of the gate electrode and on the gate dielectric; and The interlayer dielectric is disposed on the one or more dielectric structures and along the sidewalls of the one or more dielectric structures. An integrated wafer including: The source area is set in the substrate; The drain region is arranged in the substrate; Gate dielectric, lining the inner surface of the substrate; The gate electrode is disposed between the source region and the drain region and includes a base region and a plurality of gate extensions, the base region is located on the gate dielectric, wherein the multiple A gate extension part protrudes outward from the sidewall of the base region of the gate electrode toward the drain region; and A plurality of isolation structures continuously extend between the gate dielectric and the drain region, wherein the plurality of isolation structures respectively surround one of the plurality of gate extensions. The integrated wafer described in claim 10 further includes: A drift region is provided in the substrate between the base region and the drain region, wherein the plurality of isolation structures are separated from each other by the drift region. The integrated wafer according to claim 11, wherein the drift region extends beyond opposite sides of the plurality of isolation structures in a first direction and in a second direction perpendicular to the first direction. The integrated wafer described in claim 10 further includes: One or more dielectric structures arranged on the opposite outer edges of the gate electrode; An interlayer dielectric is disposed on the one or more dielectric structures and along the sidewalls of the one or more dielectric structures; and The silicide is arranged along the upper surface of the gate electrode, wherein the one or more dielectric structures cover one or more parts of the gate electrode outside the silicide. The integrated chip according to claim 13, wherein the one or more dielectric structures respectively include a first dielectric material, a second dielectric material located on the first dielectric material, and along the first dielectric material. A side wall of a dielectric material and a third dielectric material of the side wall of the second dielectric material. The integrated wafer according to claim 10, wherein the base area extends to a first depth below the upper surface of the substrate, and the plurality of gate extensions extend to a first depth below the upper surface of the substrate Two depths, the second depth is smaller than the first depth. The integrated wafer according to claim 15, wherein the plurality of isolation structures extend in the substrate to a depth greater than that of the gate dielectric. The integrated wafer according to claim 10, wherein the gate dielectric includes protrusions arranged between the base region and the gate extensions of the plurality of gate extensions, the protrusions from The upper surface of the base area extends outward to above the bottom of the gate extension. The integrated chip according to claim 10, wherein the bottom surface of the gate extension of the plurality of gate extensions is isolated from the upper surface of the gate dielectric and the isolation in the plurality of isolation structures The upper surface of the structure is in contact with both. A method for forming an integrated wafer includes: Forming multiple isolation structures in the substrate; Selectively etching the substrate to form a gate base groove in the substrate; Selectively etching the plurality of isolation structures to form a plurality of gate extension trenches extending outward from the gate base groove; Forming a conductive material in the gate base groove and the plurality of gate extension trenches to form a gate electrode; and A source region and a drain region are formed on opposite sides of the gate electrode. The method for forming an integrated wafer as described in claim 19 further includes: Before selectively etching the plurality of isolation structures to form the plurality of gate extension trenches, a gate dielectric is formed in the gate base groove.

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