TWI780870B - Integrated circuit product and chip floorplan arrangement thereof - Google Patents

Abstract

An integrated circuit product includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; and a sixth chip; a seventh chip; and an eighth chip. The areas and compositions of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and compositions of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Description

Integrated circuit products and their chip layout

The present invention relates to the packaging of integrated circuits (integrated circuit, IC), especially to the chip (chip) and/or small chip (chiplet) (hereinafter collectively referred to as chip) arrangement (floorplan arrangement) of integrated circuit packaging.

Advanced packaging is the current trend of integrated circuits. However, poor die layout can have the following disadvantages: wasted area (resulting in an uncompetitive finished product that is too large), poor heat dissipation from the die (reducing die performance), and difficult output and/or input routing (increasing packaging difficulty) And/or the relative position of the chip is not ideal (resulting in waste of chip pins). Therefore, a wafer arrangement is needed to solve at least one of the above-mentioned problems.

In view of this, how to alleviate or eliminate the lack of chip arrangement in the above-mentioned related fields is a problem to be solved.

This specification provides an embodiment of an integrated circuit product, which includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip; and an eighth chip. The areas and components of the first wafer, the second wafer, the third wafer, and the fourth wafer are substantially the same; the fifth wafer, the sixth wafer, the seventh wafer, and the eighth wafer The areas and components are substantially the same; the first chip, the second chip, the third chip, and the fourth chip are respectively located on the four sides of the integrated circuit product; and the fifth chip, the sixth chip , the seventh chip, and the eighth chip are located in a central area of the integrated circuit product.

The specification further provides an embodiment of an integrated circuit product. The integrated circuit product has a first side, a second side, a third side, and a fourth side. The integrated circuit product includes: a first logic chip located on the first side; a second logic chip located on the second side; a third logic chip located on the third side; a fourth logic chip located on the The fourth side; a first memory chip; a second memory chip; a third memory chip; and a fourth memory chip. The arrangement of the first logic chip, the second logic chip, the third logic chip, and the fourth logic chip is point-symmetrical with respect to a center of the integrated circuit product, and the first memory chip, The arrangement of the second memory chip, the third memory chip, and the fourth memory chip is point-symmetrical with respect to the center.

One of the advantages of the above embodiments is that it can improve the heat dissipation performance of integrated circuit products, reduce the difficulty of output and/or input wiring, and improve the competitiveness of integrated circuit products.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

Embodiments of the present invention will be described below in conjunction with related figures. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a schematic diagram of a simplified chip layout of an integrated circuit product according to an embodiment of the present invention. The integrated circuit product 100 includes a first logic chip 112 , a second logic chip 114 , a third logic chip 116 , a fourth logic chip 118 , a first memory chip 122 , a second memory chip 124 , and a third memory chip 126 , and the fourth memory chip 128 . FIG. 1 shows a top view of an integrated circuit product 100 , and FIGS. 2 and 3 each show a simplified side view (along AA' cross-section of FIG. 1 ) of an integrated circuit product according to an embodiment of the present invention. In the embodiment of FIG. 2 , the integrated circuit product 100 includes a substrate 150 , and the logic chips and the memory chips shown in FIG. 1 are located above the substrate 150 . There are a plurality of micro-bumps 152 between the substrate 150 and the logic chip and between the substrate 150 and the memory chip, and a plurality of bumps 154 under the substrate 150 . In the embodiment of FIG. 3 , the integrated circuit product 100 includes an interposer 140 , and the logic chips and the memory chips shown in FIG. 1 are located above the interposer 140 . There are a plurality of micro bumps 152 between the interposer 140 and the substrate 150 , and a plurality of bumps 154 under the substrate 150 . The first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 may be logic circuits with computing capabilities, such as System on a chip (SoC). The logic chip can access the memory chip to realize a specific function. For example, the logic chip realizes the function by reading and executing the program code or program instructions stored in the memory chip.

Back to Figure 1. The integrated circuit product 100 has a first side 102 , a second side 104 , a third side 106 , and a fourth side 108 . The four sides of the integrated circuit product 100 may be the four sides of the substrate 150 . The integrated circuit product 100 also has a center 101 . The first logic chip 112 is arranged on the first side 102, that is, the first logic chip 112 is located on the first side 102, which means that the first logic chip 112 is adjacent to the first side 102 (ie, the first logic chip 112 One side of the die 112 is substantially aligned with the first side 102 , or the first logic die 112 is substantially flush with the substrate 150 ). Similarly, a second logic die 114 is located on (equivalently arranged on, adjacent to) the second side 104 , a third logic die 116 is located on the third side 106 , and a fourth logic die 118 is located on the fourth side 108 .

The first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 are arranged at four edges of the integrated circuit product 100 in a ring shape. The first logic die 112 is adjacent to the fourth logic die 118 and the second logic die 114; the second logic die 114 is adjacent to the first logic die 112 and the third logic die 116; the third logic die 116 is adjacent to the second logic die 114 and the fourth logic die 114 the logic die 118 ; and the fourth logic die 118 adjacent to the third logic die 116 and the first logic die 112 .

The first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are not adjacent to any side of the integrated circuit product 100, but are surrounded by the first logic chip 112, the second The logic die 114 , the third logic die 116 , and the fourth logic die 118 surround together. More specifically, as shown in FIG. 4, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are located in the central area 160 of the integrated circuit product 100, The distances from the central area 160 to the first side 102 , the second side 104 , the third side 106 and the fourth side 108 are d1 , d2 , d3 and d4 respectively (d1 , d2 , d3 , d4 are substantially equal). As shown in Figure 1, the central region 160 is completely surrounded by the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118, that is, the four sides of the central region 160 are respectively connected to the first logic chip 118. Logic die 112 , second logic die 114 , third logic die 116 , and fourth logic die 118 are completely contiguous.

In some embodiments, the areas of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially the same, and the first memory chip 122, the second memory chip 124 , the third memory chip 126 , and the fourth memory chip 128 have substantially the same area.

In some embodiments, the constituent elements of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially the same, and the first memory chip 122, the second memory chip The components of 124, the third memory chip 126, and the fourth memory chip 128 are substantially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are the same in type and quantity, and the first memory chip 122, the second logic chip 122 The components of the second memory chip 124 , the third memory chip 126 , and the fourth memory chip 128 are the same in type and quantity.

The first logic chip 112 is adjacent to the first memory chip 122, the second memory chip 124, and the second logic chip 114, and the relative position between the first logic chip 112 and the first memory chip 122 is substantially equal to that of the second logic chip. The relative position between the chip 114 and the second memory chip 124 . More specifically, please refer to Figure 1 and Figure 5 together. The first logic chip 112 and the first memory chip 122 form a first polygon 132, the second logic chip 114 and the second memory chip 124 form a second polygon 134, and if the first polygon 132 is opposite When the center 101 of the integrated circuit product 100 is rotated 90 degrees clockwise, it will completely overlap with the second polygon 134; that is, the first polygon 132 and the second polygon 134 are rotationally symmetrical (the center of rotational symmetry is center 101, while the rotation angle is 90 degrees). Similarly, the third logic chip 116 is adjacent to the third memory chip 126, the fourth memory chip 128 and the fourth logic chip 118, and the relative position between the third logic chip 116 and the third memory chip 126 is substantially equal to The relative position between the fourth logic die 118 and the fourth memory die 128 . In other words, in some embodiments, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are respectively connected to the first memory chip 122, the second memory chip 124, The third memory chip 126 and the fourth memory chip 128 form a constituent unit of the integrated circuit product 100, that is, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth The logic chip 118 can access or be coupled to the first memory chip 122 , the second memory chip 124 , the third memory chip 126 , and the fourth memory chip 128 respectively. One of the advantages of such an arrangement is that the external pins of the first logic chip 112 (the second logic chip 114, the third logic chip 116, or the fourth logic chip 118) (that is, the outside of the integrated circuit product 100) can be arranged On the first side 102 (the second side 104, the third side 106, or the fourth side 108), the inner pins (such as the first memory chip 122, the second memory chip 124, the third memory chip Die 126 , or pins communicating with the fourth memory die 128 ) can be arranged on the side adjacent to the memory die. In this way, because the chip arrangement of the integrated circuit product 100 is simple (only need to rotate the first polygon by 90 degrees, 180 degrees, and 270 degrees), different regions of the integrated circuit product 100 can use the same light. Cover to manufacture, thus greatly simplifying the manufacturing process without wasting pins.

From another perspective, the first logic chip 112 is adjacent to the first memory chip 122, the second memory chip 124, and the fourth logic chip 118, and the relative position between the first logic chip 112 and the second memory chip 124 It is substantially equal to the relative position between the fourth logic die 118 and the first memory die 122 . More specifically, please refer to Figure 1 and Figure 6 together. The fourth logic chip 118 and the first memory chip 122 form the third polygon 136, the first logic chip 112 and the second memory chip 124 form the fourth polygon 138, and if the third polygon 136 is opposite When the center 101 of the integrated circuit product 100 is rotated 90 degrees clockwise, it will completely overlap with the fourth polygon 138; that is, the third polygon 136 and the fourth polygon 138 are rotationally symmetrical (the center of rotational symmetry is center 101, while the rotation angle is 90 degrees). Similarly, the third logic chip 116 is adjacent to the third memory chip 126, the fourth memory chip 128 and the second logic chip 114, and the relative position between the third logic chip 116 and the fourth memory chip 128 is substantially equal to The relative position between the second logic die 114 and the third memory die 126 . In other words, in other embodiments, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are respectively connected to the second memory chip 124 and the third memory chip 126. , the fourth memory chip 128, and the first memory chip 122 form a constituent unit of the integrated circuit product 100, that is, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the first logic chip 116. The four logic chips 118 can respectively access or be coupled to the second memory chip 124 , the third memory chip 126 , the fourth memory chip 128 , and the first memory chip 122 . The advantages of such an arrangement are similar or identical to those described in the previous paragraph, so details are not repeated here.

If first logic die 112, second logic die 114, third logic die 116, and fourth logic die 118 are rotated 180 degrees relative to center 101, first logic die 112 and third logic die 116 substantially overlap, and The second logic chip 114 substantially overlaps with the fourth logic chip 118 , in other words, the first logic chip 112 and the third logic chip 116 present point symmetry (point symmetry) (the center of symmetry is the center 101 ), and the second logic chip 114 and the third logic chip 116 are point symmetric. The fourth logic die 118 exhibits point symmetry. Similarly, the first memory chip 122 and the third memory chip 126 are point-symmetrical to the center 101 , and the second memory chip 124 and the fourth memory chip 128 are point-symmetrical to the center 101 . In other words, the first logic chip 112, the second logic chip 114, the third logic chip 116, the fourth logic chip 118, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth The overall arrangement of the memory chip 128 is symmetrical with respect to the center 101 .

In other embodiments, the integrated circuit product 100 is a square.

FIG. 7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 7 shows a top view of the integrated circuit product 200 . The integrated circuit product 200 includes a first logic chip 212 , a second logic chip 214 , a third logic chip 216 , a fourth logic chip 218 , a first memory chip 222 , a second memory chip 224 , and a third memory chip 226 , a fourth memory chip 228 , a first other chip 232 , a second other chip 234 , a third other chip 236 , and a fourth other chip 238 . Similar to IC product 100 , IC product 200 includes a substrate and may or may not include an interposer (see FIGS. 2 and 3 ).

In some embodiments, the first other die 232, the second other die 234, the third other die 236, and the fourth other die 238 are input/output dies containing input/output circuits, the first logic die 212, the second The logic chip 214 , the third logic chip 216 , and the fourth logic chip 218 use input/output circuits to transmit or receive signals. In other embodiments, the first other die 232 , the second other die 234 , the third other die 236 , and the fourth other die 238 are silicon dies that do not contain any circuitry.

The first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are located on the first side 202, the second side 204, the third side 206, and the fourth side of the integrated circuit product 200, respectively. edge 208 , and the first memory chip 222 , the second memory chip 224 , the third memory chip 226 , and the fourth memory chip 228 are located in the central region 260 of the integrated circuit product 200 . Please refer to FIG. 4 , the central area 260 of the integrated circuit product 200 is the area where the first memory chip 222 , the second memory chip 224 , the third memory chip 226 , and the fourth memory chip 228 are located.

In some embodiments, the areas of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are substantially the same; the first memory chip 222, the second memory chip 224, The areas of the third memory chip 226 and the fourth memory chip 228 are substantially the same; and the areas of the first other chip 232, the second other chip 234, the third other chip 236, and the fourth other chip 238 are substantially the same .

In some embodiments, the constituent elements of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are substantially the same, and the first memory chip 222, the second memory chip 224 , the third memory chip 226, and the constituent elements of the fourth memory die 228 are substantially the same, and the constituent elements of the first other die 232, the second other die 234, the third other die 236, and the fourth other die 238 essentially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are the same in type and quantity, and the first memory chip 222, the second logic chip The components of the memory chip 224, the third memory chip 226, and the fourth memory chip 228 are identical in type and quantity, and the first other chip 232, the second other chip 234, the third other chip 236, and the first other chip 236 The components of the four other chips 238 are the same in type and quantity.

Similar to the embodiment of FIG. 1 , the first logic die 212 , the second logic die 214 , the third logic die 216 , and the fourth logic die 218 collectively surround the central region 260 of the integrated circuit product 200 . More specifically, the four sides of the central area 260 are respectively completely adjacent to the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218, that is to say, the integrated circuit product 200 The central region 260 is completely surrounded by the first logic die 212 , the second logic die 214 , the third logic die 216 , and the fourth logic die 218 .

The first other die 232 , the second other die 234 , the third other die 236 , and the fourth other die 238 are located outside the central region 260 of the integrated circuit product 200 . More specifically, the first other chip 232 , the second other chip 234 , the third other chip 236 , and the fourth other chip 238 are respectively located at four corners of the integrated circuit product 200 . That is, the first apex 233 of the first other die 232 is aligned with the first apex 203 of the integrated circuit product 200 , the second apex 235 of the second other die 234 is aligned with the second apex 205 of the integrated circuit product 200 , The third apex 237 of the third other die 236 is aligned with the third apex 207 of the IC product 200 , and the fourth apex 239 of the fourth other die 238 is aligned with the fourth apex 209 of the IC product 200 .

If the first logic die 212, the second logic die 214, the third logic die 216, and the fourth logic die 218 are rotated 180 degrees relative to the center 201, the first logic die 212 and the third logic die 216 substantially overlap, and The second logic chip 214 substantially overlaps with the fourth logic chip 218, in other words, the first logic chip 212 and the third logic chip 216 present point symmetry (the center of symmetry is the center 201), and the second logic chip 214 and the fourth logic chip 218 exhibits point symmetry. Similarly, the first memory chip 222 and the third memory chip 226 are point-symmetrical to the center 201 , and the second memory chip 224 and the fourth memory chip 228 are point-symmetrical to the center 201 . Similarly, the first other wafer 232 and the third other wafer 236 are point-symmetrical to the center 201 , and the second other wafer 234 and the fourth other wafer 238 are point-symmetrical to the center 201 . In other words, the first logic chip 212, the second logic chip 214, the third logic chip 216, the fourth logic chip 218, the first memory chip 222, the second memory chip 224, the third memory chip 226, the fourth memory chip The overall arrangement of the bulk wafer 228 , the first other wafer 232 , the second other wafer 234 , the third other wafer 236 , and the fourth other wafer 238 is point-symmetrical with respect to the center 201 .

In other embodiments, the integrated circuit product 200 is a square.

The first logic chip 212 is adjacent to the first memory chip 222, the second memory chip 224, and the first other chip 232, and the relative position between the first logic chip 212 and the first memory chip 222 is substantially equal to that of the second memory chip 222. The relative position between the logic die 214 and the second memory die 224 . More specifically, please refer to FIG. 5 and FIG. 7 at the same time. The first logic die 212, the first memory die 222, and the first other die 232 form the first polygon 132, and the second logic die 214, the second memory die 224, and the second other die 234 form the second polygon 132. 134 , and if the first polygon 132 is rotated 90 degrees clockwise relative to the center 201 of the integrated circuit product 200 , it will completely overlap the second polygon 134 . Similarly, the third logic chip 216 is adjacent to the third memory chip 226, the fourth memory chip 228, and the third other chip 236, and the relative position between the third logic chip 216 and the third memory chip 226 is substantially It is equal to the relative position between the fourth logic die 218 and the fourth memory die 228 . In other words, in some embodiments, the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 can respectively access or be coupled to the first memory chip 222, the second logic chip The second memory chip 224 , the third memory chip 226 , and the fourth memory chip 228 .

From another point of view, the first logic chip 212 is adjacent to the first memory chip 222, the second memory chip 224, the first other chip 232 and the fourth other chip 238, and the first logic chip 212 and the second memory chip 224 The relative position between them is substantially equal to the relative position between the fourth logic die 218 and the first memory die 222 . More specifically, please refer to FIG. 6 and FIG. 7 at the same time. The fourth logic chip 218, the first memory chip 222, and the fourth other chip 238 form the third polygon 136, and the first logic chip 212, the second memory chip 224, and the first other chip 232 form the fourth polygon 136. 138 , and if the third polygon 136 is rotated 90 degrees clockwise relative to the center 201 of the integrated circuit product 200 , it will completely overlap the fourth polygon 138 . Similarly, the third logic chip 216 is adjacent to the third memory chip 226, the fourth memory chip 228, the second other chip 234, and the third other chip 236, and the third logic chip 216 and the fourth memory chip 228 The relative position between them is substantially equal to the relative position between the second logic die 214 and the third memory die 226 . In other words, in other embodiments, the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 can respectively access or be coupled to the second memory chip 224, The third memory chip 226 , the fourth memory chip 228 , and the first memory chip 222 .

FIG. 8 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention. FIG. 8 shows a top view of the integrated circuit product 300 . The integrated circuit product 300 includes a first logic chip 312 , a second logic chip 314 , a third logic chip 316 , a fourth logic chip 318 , a first memory chip 322 , a second memory chip 324 , and a third memory chip 326 , a fourth memory chip 328 , a first other chip 332 , a second other chip 334 , a third other chip 336 , and a fourth other chip 338 . Similar to IC product 100 , IC product 300 includes a substrate and may or may not include an interposer (see FIGS. 2 and 3 ).

In some embodiments, first other die 332 , second other die 334 , third other die 336 , and fourth other die 338 are input/output dies, including input/output circuits. In other embodiments, the first other die 332 , the second other die 334 , the third other die 336 , and the fourth other die 338 are silicon dies that do not contain any circuitry.

The first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are located on the first side 302, the second side 304, the third side 306, and the fourth side of the integrated circuit product 300, respectively. edge 308 , and the first memory chip 322 , the second memory chip 324 , the third memory chip 326 , and the fourth memory chip 328 are located in the central area 360 of the integrated circuit product 300 . Please refer to FIG. 4 , the central area 360 of the integrated circuit product 300 is the area where the first memory chip 322 , the second memory chip 324 , the third memory chip 326 , and the fourth memory chip 328 are located.

In some embodiments, the areas of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are substantially the same; the first memory chip 322, the second memory chip 324, The areas of the third memory chip 326 and the fourth memory chip 328 are substantially the same; and the areas of the first other chip 332, the second other chip 334, the third other chip 336, and the fourth other chip 338 are substantially the same .

In some embodiments, the components of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are substantially the same, the first memory chip 322, the second memory chip 324 , the third memory chip 326, and the constituent elements of the fourth memory die 328 are substantially the same, and the constituent elements of the first other die 332, the second other die 334, the third other die 336, and the fourth other die 338 essentially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. In some other embodiments, the constituent elements of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are the same in type and quantity, and the first memory chip 322, the second The components of the memory chip 324, the third memory chip 326, and the fourth memory chip 328 are identical in type and quantity, and the first other chip 332, the second other chip 334, the third other chip 336, and the first other chip 332 The components of the four other chips 338 are the same in type and quantity.

In the embodiment of FIG. 8 , the first logic die 312 , the second logic die 314 , the third logic die 316 , and the fourth logic die 318 collectively surround the central area 360 of the integrated circuit product 300 . More specifically, the first logic die 312, the second logic die 314, the third logic die 316, and the fourth logic die 318 do not completely surround the central area 360 of the integrated circuit product 300 because the center of the integrated circuit product 300 The four sides of the area 360 are not completely adjacent to the first logic die 312 , the second logic die 314 , the third logic die 316 , and the fourth logic die 318 .

The first other die 332 , the second other die 334 , the third other die 336 , and the fourth other die 338 are located outside the central region 360 of the integrated circuit product 300 . The first other chip 332 , the second other chip 334 , the third other chip 336 , and the fourth other chip 338 each have only one side adjacent to one side of the integrated circuit product 300 . More specifically, one side of the first other wafer 332, the second other wafer 334, the third other wafer 336, and the fourth other wafer 338 are connected to the first side 302, the second side 304, the third side 306, and the first side, respectively. The four sides 308 are adjacent, while the other three sides of the first other chip 332 , the second other chip 334 , the third other chip 336 , and the fourth other chip 338 are not adjacent to the sides of the integrated circuit product 300 .

The first logic chip 312 , the second logic chip 314 , the third logic chip 316 , and the fourth logic chip 318 are respectively located at four corners of the integrated circuit product 300 . That is, the first vertex 313 of the first logic chip 312 is aligned with the first vertex 303 of the integrated circuit product 300 , the second vertex 315 of the second logic chip 314 is aligned with the second vertex 305 of the integrated circuit product 300 , The third apex 317 of the third logic die 316 is aligned with the third apex 307 of the IC product 300 , and the fourth apex 319 of the fourth logic die 318 is aligned with the fourth apex 309 of the IC product 300 .

If the first logic die 312, the second logic die 314, the third logic die 316, and the fourth logic die 318 are rotated 180 degrees relative to the center 301, the first logic die 312 and the third logic die 316 substantially overlap, and The second logic chip 314 and the fourth logic chip 318 substantially overlap. 318 exhibits point symmetry. Similarly, the first memory chip 322 and the third memory chip 326 are point-symmetrical to the center 301 , and the second memory chip 324 and the fourth memory chip 328 are point-symmetrical to the center 301 . Similarly, the first other wafer 332 and the third other wafer 336 are point-symmetrical to the center 301 , and the second other wafer 334 and the fourth other wafer 338 are point-symmetrical to the center 301 . In other words, the first logic chip 312, the second logic chip 314, the third logic chip 316, the fourth logic chip 318, the first memory chip 322, the second memory chip 324, the third memory chip 326, the fourth memory chip The overall arrangement of the bulk chip 328 , the first other chip 332 , the second other chip 334 , the third other chip 336 , and the fourth other chip 338 is point-symmetrical with respect to the center 301 of the integrated circuit product 300 .

In other embodiments, the integrated circuit product 300 is a square.

The first logic chip 312 is adjacent to the first memory chip 322, the second memory chip 324, and the first other chip 332, and the relative position between the first logic chip 312 and the first memory chip 322 is substantially equal to that of the second memory chip 322. The relative position between the logic die 314 and the second memory die 324 . More specifically, please refer to FIG. 5 and FIG. 8 at the same time. The first logic die 312, the first memory die 322, and the first other die 332 form the first polygon 132, and the second logic die 314, the second memory die 324, and the second other die 334 form the second polygon 132. 134 , and if the first polygon 132 is rotated 90 degrees clockwise relative to the center 301 of the integrated circuit product 300 , it will completely overlap the second polygon 134 . Similarly, the third logic chip 316 is adjacent to the third memory chip 326, the fourth memory chip 328, and the third other chip 336, and the relative position between the third logic chip 316 and the third memory chip 326 is substantially It is equal to the relative position between the fourth logic die 318 and the fourth memory die 328 . In other words, in some embodiments, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 can respectively access or be coupled to the first memory chip 322, the second logic chip The second memory chip 324 , the third memory chip 326 , and the fourth memory chip 328 .

From another point of view, the first other chip 332 is adjacent to the first logic chip 312, the fourth logic chip 318, and the first memory chip 322, and the relative position between the first logic chip 312 and the second memory chip 324 is substantially is equal to the relative position between the fourth logic die 318 and the first memory die 322 . More specifically, please refer to FIG. 6 and FIG. 8 at the same time. The fourth logic chip 318, the first memory chip 322, and the fourth other chip 338 form the third polygon 136, and the first logic chip 312, the second memory chip 324, and the first other chip 332 form the fourth polygon 136. 138 , and if the third polygon 136 is rotated 90 degrees clockwise relative to the center 301 of the integrated circuit product 300 , it will completely overlap the fourth polygon 138 . Similarly, the third other chip 336 is adjacent to the second logic chip 314, the third logic chip 316, and the third memory chip 326, and the relative position between the third logic chip 316 and the fourth memory chip 328 is substantially equal to The relative position between the second logic die 314 and the third memory die 326 . In other words, in other embodiments, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 can respectively access or be coupled to the second memory chip 324, The third memory chip 326 , the fourth memory chip 328 , and the first memory chip 322 .

The first memory chip 122, the second memory chip 124, the third memory chip 126, the fourth memory chip 128, the first memory chip 222, and the second memory chip in Fig. 1, Fig. 7 and Fig. 8 224, the third memory chip 226, the fourth memory chip 228, the first memory chip 322, the second memory chip 324, the third memory chip 326, and the fourth memory chip 328 are the third generation high-bandwidth memory Body (high bandwidth memory generation 3, HBM3), its shape is square. However, the above-mentioned memory chips can also be second-generation high bandwidth memory generation 2 (HBM2), as shown in FIGS. 9-11 . The first memory chip 422, the second memory chip 424, the third memory chip 426, the fourth memory chip 428 of the integrated circuit product 400, the first memory chip 522, the second memory chip of the integrated circuit product 500 Body chip 524, third memory chip 526, fourth memory chip 528, and first memory chip 622, second memory chip 624, third memory chip 626, fourth memory chip of integrated circuit product 600 Die 628 is second generation high bandwidth memory. The center 401 of the IC product 400, the center 501 of the IC product 500, and the center 601 of the IC product 600 are not covered by the memory chip because the second generation HBDMA is not square. The descriptions of FIG. 9 , FIG. 10 and FIG. 11 may correspond to the descriptions of FIG. 1 , FIG. 7 and FIG. 8 respectively, so details are not repeated here.

To sum up, since the logic circuit usually generates more heat than the memory chip, the heat dissipation performance of the integrated circuit product can be improved by arranging the logic chip around the integrated circuit product. Furthermore, since the logic chips usually need to receive signals and transmit signals, arranging the logic chips around the integrated circuit product can reduce the difficulty of output and/or input routing. In addition, the chip arrangement proposed in this case can make the chips closely arranged in the integrated circuit product, so the substrate area can be fully utilized to improve the competitiveness of the integrated circuit product. Furthermore, arranging the chips on the integrated circuit product in a point-symmetrical manner not only avoids waste of pins, but also facilitates the use of the same photomask to manufacture different parts of the integrated circuit product, thus simplifying the complexity of the photomask. Spend.

From another point of view, by arranging the chips on the integrated circuit products in the aforementioned point-symmetric manner, semiconductor manufacturers can use the same set of photomasks to manufacture integrated circuit products whose area is nearly four times the size, so it can Significantly reduce the manufacturing cost of integrated circuit products.

Please note that the arrangement of chips on the aforementioned integrated circuit product is only an exemplary embodiment, and does not limit the actual implementation of the present invention. For example, in some embodiments, the aforementioned first to fourth memory chips can be changed to be arranged on the product in a line-symmetrical manner with respect to the central axis of the integrated circuit product (passing through the center and perpendicular to any side). The central area of the integrated circuit product, and the aforementioned first to fourth logic chips are changed to be line-symmetrical with respect to the central axis of the integrated circuit product, and are respectively arranged on the periphery of the central area of the integrated circuit product.

Certain words are used to refer to specific elements in the specification and scope of claims, but those skilled in the art may use different terms to refer to the same element. This specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of components as a basis for differentiation. The "comprising" mentioned in the specification and scope of patent application is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means is indirectly electrically or signally connected to the second element.

The description of "and/or" used in the specification includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes a plural meaning.

The dimensions and relative sizes of some elements in the drawings will be exaggerated, or the shapes of some elements will be simplified in order to express the contents of the embodiments more clearly. Therefore, unless otherwise specified by the applicant, the shapes, dimensions, relative sizes and relative positions of the elements in the drawings are only for illustration purposes only, and should not be used to limit the patent scope of the present invention. In addition, the present invention can be embodied in many different forms, and when explaining the present invention, it should not be limited only to the embodiments presented in this specification.

For the convenience of description, some descriptions related to relative positions in space may be used in the description to describe the function of a certain component in the drawings or the relative spatial relationship between the component and other components. For example, "on," "above," "below," "below," "above," "below," "up," "down," and the like. Those with ordinary knowledge in the technical field should understand that these descriptions related to relative positions in space not only include the orientation of the described components in the drawings, but also include the use and operation of the described components. , or various pointing relationships during assembly. For example, if the drawing is turned upside down, the element originally described as "on" will become "below". Therefore, the description of "on" used in the specification includes two different pointing relationships of "below" and "on". In the same way, the term "upward" used here includes two different pointing relationships of "upward" and "downward".

In the description and scope of the patent application, if it is described that the first element is located on the second element, above the second element, connected, bonded, coupled to the second element, or in contact with the second element, it means that the first element can directly Located on the second element, directly connected, directly bonded, or directly coupled to the second element may also mean that there are other elements between the first element and the second element. In contrast, if it is described that the first element is directly on the second element, directly connected, directly bonded, directly coupled, or directly connected to the second element, it means that there are no other elements between the first element and the second element .

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100, 200, 300, 400, 500, 600. ． ． Integrated circuit product

112, 212, 312. ． ． first logic chip

114, 214, 314. ． ． second logic chip

116, 216, 316. ． ． third logic chip

118, 218, 318. ． ． fourth logic chip

122, 222, 322, 422, 522, 622. ． ． first memory chip

124, 224, 324, 424, 524, 624. ． ． second memory chip

126, 226, 326, 426, 526, 626. ． ． third memory chip

128, 228, 328, 428, 528, 628. ． ． fourth memory chip

150． ． ． Substrate

152． ． ． Micro bump

154． ． ． Bump (bump)

140． ． ． interposer

102, 202, 302. ． ． first side

104, 204, 304. ． ． second side

106, 206, 306. ． ． third side

108, 208, 308. ． ． fourth side

101, 201, 301, 401, 501, 601. ． ． center

160, 260, 360. ． ． central region

d1, d2, d3, d4. ． ． distance

132． ． ． first polygon

134． ． ． second polygon

136． ． ． third polygon

138． ． ． fourth polygon

232, 332． ． ． first other chip

234, 334． ． ． second other chip

236, 336． ． ． third other chip

238, 338． ． ． Fourth other chip

233, 203, 313, 303. ． ． first vertex

235, 205, 315, 305. ． ． second vertex

237, 207, 317, 307. ． ． third vertex

239, 209, 319, 309. ． ． fourth vertex

FIG. 1 is a schematic diagram of a simplified chip layout of an integrated circuit product according to an embodiment of the present invention.

FIG. 2 shows a simplified side view of an integrated circuit product according to an embodiment of the present invention.

FIG. 3 shows a simplified side view of an integrated circuit product according to another embodiment of the present invention.

FIG. 4 shows the relationship between the central area and the edge of the integrated circuit product of the present invention.

FIG. 5 shows the constituent units of an integrated circuit product according to an embodiment of the present invention.

FIG. 6 shows the constituent units of an integrated circuit product according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

FIG. 9 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

FIG. 10 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

FIG. 11 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

100． ． ． Integrated circuit products 101． ． ． center 102． ． ． first side 104． ． ． second side 106． ． ． third side 108． ． ． fourth side 112． ． ． first logic chip 114． ． ． second logic chip 116． ． ． third logic chip 118． ． ． fourth logic chip 122． ． ． first memory chip 124． ． ． second memory chip 126． ． ． third memory chip 128． ． ． fourth memory chip

Claims (22)

An integrated circuit product (100; 200; 300) comprising: a first wafer (112; 212; 312); a second chip (114; 214; 314); a third chip (116; 216; 316); a fourth chip (118; 218; 318); a fifth chip (122; 222; 322); a sixth wafer (124; 224; 324); a seventh chip (126; 226; 326); and an eighth chip (128; 228; 328); Wherein, the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are substantially the same in area and composition; Areas of the fifth wafer (122; 222; 322), the sixth wafer (124; 224; 324), the seventh wafer (126; 226; 326), and the eighth wafer (128; 228; 328) and its constituent elements are substantially the same; The first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are located at The four sides of the integrated circuit product (100; 200; 300); and The fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328) are located on the The central area (160; 260; 360) of one of the integrated circuit products (100; 200; 300). The integrated circuit product (100; 200; 300) according to claim 1, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip ( 116; 216; 316), and any one of the fourth chip (118; 218; 318), will be coupled to the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and one of the eighth chip (128; 228; 328). The integrated circuit product (100; 200; 300) according to claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip ( 116; 216; 316), and the arrangement of the fourth chip (118; 218; 318) is point-symmetrical with respect to a center (101; 201; 301) of the integrated circuit product (100; 200; 300) , and the fifth wafer (122; 222; 322), the sixth wafer (124; 224; 324), the seventh wafer (126; 226; 326), and the eighth wafer (128; 228; 328) The arrangement is point-symmetrical with respect to the center (101; 201; 301). The integrated circuit product (100; 200; 300) according to claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip ( 116; 216; 316), and the arrangement of the fourth chip (118; 218; 318) presents a ring shape. The integrated circuit product (100) according to claim 2, wherein the first chip (112) is adjacent to the fourth chip (118) and the second chip (114), and the second chip (114) is adjacent to the The first wafer (112) and the third wafer (116), the third wafer (116) is adjacent to the second wafer (114) and the fourth wafer (118), and the fourth wafer (118) is adjacent to the first wafer (118) Three chips (116) and the first chip (112). The integrated circuit product (100; 200; 300) according to claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip ( 116; 216; 316), and the fourth chip (118; 218; 318) is a logic chip, and the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the The seven chips (126; 226; 326) and the eighth chip (128; 228; 328) are memory chips. The integrated circuit product (100) according to claim 2, wherein the first chip (112) and the fifth chip (122) form a first polygon (132), and the second chip (114) and the sixth chip (124) forms a second polygon (134), if the first polygon (132) is rotated ninety degrees relative to a center (101) of the integrated circuit product (100) , will completely overlap this second polygon (134). The integrated circuit product (100) according to claim 2, wherein the fourth chip (118) and the fifth chip (122) form a third polygon (136), and the first chip (112) and the sixth chip (124) forms a fourth polygon (138), if the third polygon (136) is rotated ninety degrees relative to a center (101) of the integrated circuit product (100) , will completely overlap the fourth polygon (138). The integrated circuit product (100; 200; 300) according to claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip ( 116; 216; 316), and the fourth wafer (118; 218; 318), which together surround the central area (160; 260; 360). The integrated circuit product (100; 200) according to claim 9, wherein the first chip (112; 212), the second chip (114; 214), the third chip (116; 216), and The fourth wafer (118; 218) completely surrounds the central region (160; 260). The integrated circuit product (200; 300) described in claim 2 further includes: a ninth chip (232; 332); a tenth chip (234; 334); an eleventh chip (236; 336); and a twelfth wafer (238; 338); Wherein, the ninth wafer (232; 332), the tenth wafer (234; 334), the eleventh wafer (236; 336), and the twelfth wafer (238; 338) are located in the central area (260 ;360). The integrated circuit product (200) as claimed in claim 11, wherein the ninth chip (232), the tenth chip (234), the eleventh chip (236), and the twelfth chip (238 ) are located at the four corners of the integrated circuit product (200). The integrated circuit product (300) as claimed in claim 11, wherein the first chip (312), the second chip (314), the third chip (316), and the fourth chip (318) are located at The four corners of the integrated circuit product (300). The integrated circuit product (200; 300) of claim 11, wherein the first die (212; 312), the fifth die (222; 322), and the ninth die (232; 332) form A first polygon (132), the second wafer (214; 314), the sixth wafer (224; 324), and the tenth wafer (234; 334) form a second polygon (134) , and if the first polygon (132) is rotated ninety degrees relative to one of the centers (201; 301) of the integrated circuit product (200; 300), then the second polygon (134) fully overlapped. The integrated circuit product (200; 300) according to claim 11, wherein the fourth chip (218; 318), the fifth chip (222; 322), and the twelfth chip (238; 338) forming a third polygon (136), the first wafer (212; 312), the sixth wafer (224; 324), and the ninth wafer (232; 332) forming a fourth polygon (138 ), and if the third polygon (136) is rotated ninety degrees relative to one of the centers (201; 301) of the integrated circuit product (200; 300), it will be the same as the fourth polygon (138 ) completely overlap. An integrated circuit product (100; 200; 300), having a first side (102; 202; 302), a second side (104; 204; 304), a third side (106; 206; 306), and a fourth side (108; 208; 308), including: a first logic die (112; 212; 312), located on the first side (102; 202; 302); a second logic die (114; 214; 314) located on the second side (104; 204; 304); a third logic die (116; 216; 316) on the third side (106; 206; 306); a fourth logic die (118; 218; 318) located on the fourth side (108; 208; 308); a first memory chip (122; 222; 322); a second memory chip (124; 224; 324); a third memory chip (126; 226; 326); and a fourth memory chip (128; 228; 328); Wherein, the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) is arranged point-symmetrically with respect to one center (101; 201; 301) of the integrated circuit product (100; 200; 300), and the first memory chip (122; 222; 322) , the arrangement of the second memory chip (124; 224; 324), the third memory chip (126; 226; 326), and the fourth memory chip (128; 228; 328), relative to the The center (101; 201; 301) is point-symmetric. The integrated circuit product (100; 200; 300) according to claim 16, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third Any one of the logic chip (116; 216; 316) and the fourth logic chip (118; 218; 318) is coupled to the first memory chip (122; 222; 322), the second One of the memory chip (124; 224; 324), the third memory chip (126; 226; 326), and the fourth memory chip (128; 228; 328). The integrated circuit product (100; 200; 300) according to claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third Areas of the logic chip (116; 216; 316) and the fourth logic chip (118; 218; 318) are substantially the same. The integrated circuit product (100; 200; 300) according to claim 17, wherein the first memory chip (122; 222; 322), the second memory chip (124; 224; 324), the Areas of the third memory chip (126; 226; 326) and the fourth memory chip (128; 228; 328) are substantially the same. The integrated circuit product (100; 200; 300) according to claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third The logic chip (116; 216; 316) and the fourth logic chip (118; 218; 318) are arranged in a ring shape. The integrated circuit product (100; 200; 300) according to claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third The logic chip (116; 216; 316) and the fourth logic chip (118; 218; 318) jointly surround a central area (160; 260; 360) of the integrated circuit product (100; 200; 300). The integrated circuit product (100; 200) according to claim 21, wherein the first logic chip (112; 212), the second logic chip (114; 214), the third logic chip (116; 216 ), and the fourth logic chip (118; 218) completely surrounds the central area (160; 260).

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