TW202345328A - Microelectronic die including swappable phy circuitry and semiconductor package including same - Google Patents

Abstract

A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

Description

Microelectronic chips containing removable PHY circuits and semiconductor packages containing the same

The present invention generally relates to in-package die-to-die (D2D) interconnect technologies, such as interconnect fast (CXi) interconnects. [ Comparison of related applications ]

This application claims the rights and priority of Indian Patent Application No. 202141061702 filed on December 30, 2021, and the entire disclosure of the application is incorporated into this article by reference.

In-package die-to-die (D2D) interconnect technology includes standard interconnect mechanisms and advanced interconnect mechanisms at a high level to provide signal connections between two dies configured on the top surface of the package substrate. Standard interconnect mechanisms involve the provision of signal routing traces, usually within organic build-up layers of the packaging substrate, to couple two dies to each other. Advanced interconnect mechanisms provide a silicon bridge structure embedded within a package substrate, where the silicon bridge structure includes signal routing traces therein to couple two dies to each other. Examples of silicon bridge structures used in advanced packaging interconnect mechanisms include embedded multi-die interconnect bridges (EMIB), or chip-on-wafer-on-substrate (CoWoS). A given D2D interconnect technology or mechanism may be selected based on a number of factors, such as, for example, bandwidth density requirements (e.g., bandwidth per millimeter (BW/mm) and/or BW/ ), die/package required layout planning, and available form factors.

and

The following description and drawings illustrate specific embodiments sufficiently to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, processing, and other changes. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The embodiments set forth in the claimed claims encompass available equivalents within the claimed claims. In the following description, various aspects of the exemplary embodiments will be described using terminology commonly used by those skilled in the art in order to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced in only some of the described viewpoints. For purposes of illustration, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the exemplary embodiments.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like characters refer to like parts throughout, and therein are shown by way of example embodiments in which the subject matter of the invention may be practiced. things. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following description should not be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technology described herein include any kind of mobile device and/or stationary device, such as microelectromechanical systems (MEMS) based electrical systems, gyroscopes, advanced driver assistance systems (ADAS) , 5G communication system, camera, mobile phone, computer terminal, desktop computer, e-reader, fax machine, information station, small laptop, notebook computer, Internet device, payment terminal, personal digital assistant, media player and/or recorders, servers (e.g., blade servers, rack-mounted servers, combinations thereof, etc.), set-top boxes, smartphones, tablets, ultra-portable PCs, wired phones, etc. combination, etc. Such devices may be portable or fixed. In some embodiments, the techniques described herein may be used in desktop computers, laptops, smartphones, tablets, laptops, notebooks, personal digital assistants, servers, combinations thereof, etc. More generally, the techniques described herein may be used in any of a variety of electronic devices, including semiconductor packages having passive heat sinks, interface layers, TIMs, top dies, side dies, substrates, and packaging substrates.

As used herein, the terms "top," "bottom," "upper," "lower," "lower" and "uppermost" when used in connection with one or more elements are intended to convey a relationship. Non-absolute entity configuration. Thus, elements described as the "uppermost" or "top" elements of the device could alternatively form the "lowermost" or "bottom" elements of the device when the device is inverted. Similarly, elements described as the "lowermost element" or "bottom element" of the device could alternatively form the "uppermost element" or "top element" of the device when the device is inverted.

Microelectronic assemblies that include standard interconnect technologies tend to suffer from lower interconnect wire densities compared to advanced packaging interconnect technologies. The use of silicon bridges in advanced interconnect mechanisms allows for the provision of closer pitch interconnects, thereby allowing for greater signal bandwidth by providing a higher density of closely spaced conductive structures under each die (e.g., C4 bumps, smaller solder bumps, or Cu-Cu connections) are possible.

Existing technologies envision D2D physical layer configurations (PHYs) that are suitable for in-package interconnection mechanisms on standard and advanced packaging substrates due to a variety of factors, including bump pitch differences and connections for a given PHY area.

As used herein, the term "PHY" may refer to the physical layer architecture within a die, including the circuitry therein, such as receive (RX) and transmit (TX) circuitry. That is, "PHY" can mean the logic and circuit architecture within a given die.

As used herein, references to "die" are intended to refer broadly to a die, wafer, or any other integrated circuit structure that includes circuitry therein and is supported on a substrate.

According to current technology, the PHY within a given die is configured differently depending on whether the die is to be coupled to another die on the package using standard interconnect mechanisms or advanced interconnect mechanisms. According to the current technology, the PHY used for standard interconnection mechanisms in the die is different from the PHY used for advanced interconnection mechanisms. Therefore, according to the prior art, a die coupled to another die with in-package interconnects has a PHY configuration such that each different PHY circuit (eg, each RX or TX circuit of the die) is connected to One or more electrical contact structures at the bottom region of the die (facing the package).

Some embodiments herein advantageously provide for a plurality of dies (including dielets) having the same PHY circuit design as one another, wherein one of the plurality of dies may have a standard thereon corresponding to the receiving package. electrical contact structures for package interconnects (e.g., for controlled collapse of die attach (C4) bumps), and another of the plurality of dies may have a structure thereon that corresponds to that on the receiving package Electrical contact structures for advanced packaging interconnects. Embodiments advantageously make it possible to provide the same die for D2D signal interconnect through packaging, where any given die may be equipped with conductive structures corresponding to standard package interconnects or to advanced package interconnects. Conductive structure. According to some embodiments, a die according to embodiments is configured to allow mapping of signal paths (ie, traces or vias) therein to fit standard or advanced bump configurations, including bump pitches.

The prior art will now be explained below with respect to the situations of FIGS. 1 and 2 .

FIG. 1 is a cross-sectional view of an example microelectronic assembly or semiconductor package 100 including a packaging substrate 104 and two dies 108 and 116 supported on a top surface 112 of the packaging substrate 104 . In FIG. 1 , package substrate 104 is shown including signal routing traces 136 therein coupling die 108 to die 116 . Substrate 104 may include a core layer including sub-layers of non-conductive material such as glass, silicon, or organic materials, and traces 136 extending through the sub-layers to conduct electrical signals therethrough. Dies 108 and 116 are each electrically coupled to the package substrate via electrical contact structures or tabs 156, such as C4 bumps, connected to die conductive contacts of the respective die and substrate conductive contacts (not shown). 104 on top 112. The C4 bump couples the dies 108 and 116 together via traces 136 that extend through the package substrate 104 and provide conductive paths between the dies 108 and 116 . Additional conductive structures 159 are provided at the bottom surface of the packaging substrate.

2 is a cross-section of an example microelectronic assembly or semiconductor package 200 including an interconnect bridge 222 embedded within a package substrate 204 and two dies 208 and 216 supported on a top surface 212 of the package substrate 204 view. In FIG. 2 , the combination of packaging substrate 204 and interconnect bridge 222 will be referred to together as microelectronic structure 201 . Substrate 204 may include a core layer including sub-layers of non-conductive material such as glass, silicon, or organic materials, and conductive traces 244 extending through the sub-layers to conduct electrical signals therethrough. The first integrated circuit die 208 is attached to the top surface 212 of the package substrate 204 via electrical contact structures or contacts 256 connected to the die conductive contacts 264 and the substrate conductive contacts 210 . The second integrated circuit die 216 is attached to the face 212 via a coupling component 260 connected to the die conductive contacts 266 and the substrate conductive contacts 220 .

Bridge conductive contacts 224 and 226 are located on face 228 of bridge 222 . Bridging vias 232 and bridging conductive traces 236 provide a conductive path between conductive contacts 224 and 226 . Substrate vias 240 and substrate conductive traces 244 provide conductive paths from substrate conductive contacts 210 to bridge conductive contacts 224 , and substrate vias 248 and substrate conductive traces 244 provide conductive paths from the substrate conductive contacts 210 to bridge conductive contacts 224 . 220 conductive path to bridge conductive contact 226. Together, conductive contacts 210, 220, 224, 226, vias 232, 240, 248, and conductive traces 236, 244 provide conductive paths between integrated circuit dies 208 and 216, allowing them to Communicatively coupled.

Although the embedded interconnect bridge 222 is shown fully embedded within the substrate assembly 204 , in some embodiments it may be partially embedded, with the bridge face 228 being a portion of the face 212 of the first substrate assembly 204 . In such embodiments, bridging conductive contacts 224 and 226 may be located at face 212 of substrate assembly 204, and integrated circuit dies 208 and 216 may be connected to the bridging conductive contacts via coupling assemblies 256 and 260, respectively. Contacts 224 and 226.

Many elements of the semiconductor package 100 or 200 of Figure 1 or Figure 2 are included in other figures associated with certain embodiments, such as Figures 3, 4A, and 4B. Accordingly, when discussing the drawings to be described below, descriptions of some elements may not be repeated, and any of these elements may take any form disclosed herein.

Additionally, in the following description of FIGS. 3, 4A, and 4B, although references to C4 bumps are intended to refer to electrical contact structures that couple the die to the package substrate, embodiments are not so limited and are included within their scope. Provide an electrical contact structure that does not include C4 bumps or bumps, such as in the form of contact pads, pins, or wire bonds, depending on application needs.

Figure 3 is a cross-sectional view of an example microelectronic assembly or semiconductor package 300 in accordance with some embodiments. In the embodiment of Figure 3, the dies on the package all include the same set of PHY circuits, but still allow mapping of the signal paths (i.e., traces or vias) therein to suit standard or advanced electrical The electrical contact structure of the contact structure configuration.

In Figure 3, microelectronic assembly 300 includes a packaging substrate 304 that includes electrical contact structures 359 on its underside for contacting a motherboard or larger system (in the example shown, electrical contact structures 359). Contact structure 359 is implemented as a C4 bump, although other examples are within the scope of the embodiments), and four dies 308a, 316a, 308b, 316b are supported on the top surface of package substrate 304, with pairs of The four dies are coupled to each other through in-package D2D interconnects arranged in package substrate 304 in a manner that includes corresponding bumps of C4 bumps 356a and 356b. Package substrate 304 may include a core layer including a sub-layer of non-conductive material such as glass, silicon, or organic materials. As far as the PHY circuit set is concerned, the four dies 308a, 316a, 308b, 316b are identical to each other because they each contain the same RX and TX circuit set, as will be further explained below. However, although dies 308a and 316a include electrical contact structures 356a (such as C4 bumps) at their bottom surfaces and are configured to be coupled to each other through signal routing paths including traces 336a that extend through the material of package substrate 304 (standard interconnect mechanism), but on the other hand, dies 308b and 316b are configured to be coupled to each other through a signal routing path including trace 33bb extending through a silicon bridge embedded in package substrate 304 (Advanced interconnection mechanism).

Thus, microelectronic assembly 300 includes standard interconnect portion 301a and advanced interconnect portion 301b. Standard interconnect portion 301a includes first die 308a and second die 316a supported on top surface 312a of package substrate 304 in addition to underlying corresponding portions of package substrate 304. Dies 308a and 316a are coupled to each other in the same manner as die 108 and 116 of Figure 1, that is, using standard interconnect mechanisms. Advanced interconnect portion 301b includes first and second dies 308b 316b supported on top surface 312b of package substrate 304 in addition to underlying corresponding portions of package substrate 304. Dies 308b and 316b are coupled to each other in the same manner as die 208 and 216 of Figure 2, that is, using advanced interconnect mechanisms.

For standard interconnect portion 301a, package substrate 304 is shown with a signal routing path therein including traces 336a that couple die 308a to die 316a and extend through a sub-layer of the substrate to conduct electrical signals therein. . Dies 308a and 316a are each electrically coupled to the package substrate via electrical contact structures or tabs 356a, such as C4 bumps, connected to the respective die's die conductive contacts and substrate conductive contacts (not shown). Top surface 312a of 304. Dies 308a and 316a each include a set of PHY circuits.

The first die of the standard interconnect portion, die 308a, contains the PHY circuitry including RX circuitry 309a and TX circuitry 311a. RX circuit 309a includes a separate RX circuit 309a', and TX circuit 311a includes a separate TX circuit 311a'. The second die of the standard interconnect portion, die 316a, contains the PHY circuitry including RX circuitry 317a and TX circuitry 319a. RX circuit 317a includes a separate RX circuit 317a', and TX circuit 319a includes a separate TX circuit 319a'. Dies 308a and 316a are identical to each other in terms of their respective PHY circuits (as shown in Figure 3), although the depiction shown shows the TX circuitry of die 308a towards the left side of the figure, and the TX circuitry of die 316a Turn and face the right side of the diagram.

In the standard interconnect portion 301a, each die 308a and 316a includes at least PHY circuitry (RX circuitry and/or TX circuitry) that is not coupled to any C4 bump. Thus, each die 308a and 316a has at least one PHY circuit from which it is not electrically coupled to the C4 bump. Therefore, in the standard interconnect portion 301a, there are redundant or non-functional PHY circuits.

For advanced interconnect portion 301b, package substrate 304 is shown including interconnect bridges 322 that include signal routing paths that include coupling die 308b to die 316b and extend through the bridges for transmitting signals therein. Conductivity signal trace 336b. Dies 308b and 316b are each electrically coupled to the package substrate via electrical contact structures or tabs 356b, such as C4 bumps, connected to the die conductive contacts of the respective die and substrate conductive contacts (not shown). Top surface 312b of 304. Dies 308b and 316b each include a set of PHY circuits.

Although the embedded interconnect bridge 322 is shown as being fully embedded within the base package 304, in some embodiments it may be partially embedded, with the upper surface of the bridge 322 being substantially identical to the upper surface 312 of the base package 304. extend together.

The first die of the advanced interconnect portion, die 308b, contains PHY circuitry including RX circuitry 309b and TX circuitry 311b. RX circuit 309b includes a separate RX circuit 309b', and TX circuit 311b includes a separate TX circuit 311b'. The second die of the advanced interconnect portion, die 316b, contains PHY circuitry including RX circuitry 317b and TX circuitry 319b. RX circuit 317b includes a separate RX circuit 317b', and TX circuit 319b includes a separate TX circuit 319b'. Dies 308b and 316b are identical to each other in terms of their respective PHY circuits (as shown in Figure 3), although the depiction shown shows the TX circuitry of die 308b toward the left side of the figure, and the TX circuitry of die 316b Turn and face the right side of the diagram.

In advanced interconnect section 301b, all PHY circuits in each die 308b and 316b are connected to corresponding C4 bumps. Thus, each die 308b and 316b includes all electrical couplings between its PHY circuitry and the corresponding C4 bump. Therefore, there are no redundant or non-functional PHY circuits in the advanced interconnect section 301b.

In the microelectronic assembly of FIG. 3 in which the first die and the second die are coupled to each other through an in-package interconnect, each active RX circuit of the first die is coupled through an in-package D2D interconnect. is connected to the corresponding active TX circuit of the second die, and each active TX circuit of the first die is coupled to the corresponding active RX circuit of the second die through an in-package D2D interconnect.

Figure 4A is a bottom plan view of die, including bumps, corresponding to die 308a/316a (hereinafter referred to as 308a since die 308a and 316a are the same), while Figure 4B is a bottom plan view of die , including bumps, corresponds to grain 308b/316b (hereinafter referred to as 308b, because grains 308b and 316b are the same). Thus, FIG. 4A is a bottom plan view of die 308a including C4 bumps on its bottom surface, where the C4 bumps correspond to standard electrical contact structure configurations comparable to the standard interconnect portion 301a of FIG. contact structure configuration, and Figure 4B is a bottom plan view of die 308b having predetermined PHY circuitry and including C4 bumps on its bottom surface, where the C4 bumps correspond to the standard interconnect portion 301a shown in Figure 3 or an advanced electrical contact structure configuration equivalent to a standard or advanced electrical contact structure configuration.

In Figures 4A and 4B, portions of die 308a and 308b corresponding to locations within the die for RX circuitry 309a/309b are shown as solid shaded areas, while those corresponding to TX circuitry 311a/311b are shown Portions of die 308a and 308b are shown as striped shaded areas. Because dies 308a and 308b are identical, they include the same RX circuitry and TX circuitry architecture as mentioned above.

In Figures 4A and 4B, for the embodiment shown, the bumps for the C4 bumps at the bottom surfaces of dies 308a and 308b are appropriately depicted as having some labeled and some unlabeled circular areas. Circular areas, where the unmarked circular areas correspond to the C4 bumps for the VCC (power) or VSS (ground) signals of that die, and the marked circular areas correspond to the C4 bumps, which C4 bumps The block will provide the signal path to and from the PHY circuitry within the die. In the example shown, TX circuits 311a/311b coincide with (ie, physically overlap) their corresponding C4 bumps, as shown by the complete overlap between TX circuits 311a/311b and C4 bump 356b, while RX circuit 309a /309b and its corresponding C4 bump appear partially overlapping. The RX circuits do not exhibit significant sensitivity to distance relative to their C4 bumps, so there is the possibility of configurations such as those shown in Figures 4A and 4B, although embodiments are not limited to this and can be used in any manner as the application requires. Modes include within their scope the positioning of RX or TX circuits relative to their corresponding conductive structures (e.g., C4 bumps). The die shown may further include non-PHY circuitry, such as non-PHY logic circuitry, which in the example shown in FIGS. 4A and 4B may be located in unshielded areas of the die.

According to an embodiment, the die includes enable/disable electrical paths connected to the PHY circuit such that enable/disable signals input to the die are used to enable the enable/disable electrical paths to enable/disable the Disable at least one RX circuit or a portion of the TX circuit (ie, a portion (ie, not all) of the RX circuit and/or a portion (ie, not all) of the TX circuit) in the die. Therefore, for a die having a predetermined configuration of RX circuits and TX circuits in accordance with embodiments, the electrical pathways are such that an enable signal input to the die can cause a portion of the RX circuit and/or the TX circuit to be enabled. Similarly, for the same die, the electrical path system allows a disable signal input to the die to cause some but not all of the RX circuits and/or TX circuits to be disabled. For example, the electrical paths may include electrical paths extending to each RX circuit and each TX circuit. In this case, the enable signal or the disable signal can be input into a part of the electrical path to enable or disable the corresponding RX circuit or TX circuit. Alternatively, the electrical paths can be extended to different RX circuit groups and different TX circuit groups, in which case each group can be enabled/disabled simultaneously. In this case, an enable signal or a disable signal can be input into the electrical path corresponding to the RX circuit or TX circuit group to enable/disable the corresponding RX circuit or TX circuit of the group. Regardless of the configuration of the enable/disable conductive paths, a die according to embodiments may be further configured such that an enable/disable signal input into the die enables/disables all PHY circuitry of the die . Enabling one portion of the PHY circuit and disabling another portion of the PHY circuit is consistent with the die being bumped or bumped according to a standard interconnect mechanism, such as that shown in standard interconnect portion 301a of FIG. 3 . Enabling all PHY circuits is consistent with the die being bumped or bumped according to advanced interconnect mechanisms, such as that shown in Figure 3 labeled advanced interconnect portion 301b.

According to one embodiment, the enable/disable conductive paths of the die according to the embodiment may include respective fuses or registers that are burned to disable or enable a corresponding one of the conductive paths. connected PHY circuit.

Depending on the embodiment, the boot logic configuration may determine how many PHY circuits are enabled or disabled.

Embodiments herein can implement superset PHY circuit designs (e.g., a PHY with 64 transmitters (TX) and 64 receivers (RX)) on the same die that contains all signaling and logic to support advanced package interconnects circuits) and use the same PHY circuit design with some de-energized RX circuits and TX circuits, and die bumping (e.g., upper metal changes and bump changes only) to support standard package interconnects (e.g. : PHY circuit with 16 TX+16 RX), thereby disabling unused channels.

In some embodiments, in addition to the presence of enable/disable conductive paths in the die that allow for enabling/disabling only a portion of the PHY circuitry, if the bump layer and overlying redistribution layer (RDL) of the die are Stripped back, as already suggested above, it is possible to observe separate TX and RX PHY circuits (one for each bump). When assembled in an advanced package, a 1:1 connection with respect to the signaling bump may be observed between the TX/RX circuits (or circuit blocks). When assembled in a standard package (e.g., in the x64 vs. One of every four PHY circuits is connected to the bump.

The embodiments of this article propose to provide a common PHY circuit in the die, and then configure the electrical contact structure through the packaging substrate that is compatible with standard interconnection mechanisms, or with advanced interconnection mechanisms (such as EMIB, CoWoS, etc. ) compatible electrical contact structure to provide D2D interconnection. The electrical contact structures may include bumps such as C4 bumps, although other electrical contact structure configurations are within the scope of the embodiments.

As an example, referring again to Figures 4A and 4B, standard package bumps used for signaling may have pitches on the order of approximately 110 microns (μm or "microns"), and advanced package bumps may have pitches on the order of approximately 45 microns to approximately 55 microns. level spacing. With this example, an advanced interconnect mechanism might have approximately four bumps in the same area as one bump of a standard interconnect mechanism.

It should be noted that the pitch values used for standard and advanced packaging, as well as the ratio between the two, may differ in different embodiments. For example, the spacing may be higher or lower than above. In one embodiment, the pitch of standard packages may be between about 110 microns and about 130 microns, and the pitch of advanced packages may be between about 36 microns and about 55 microns. This can result in a ratio of standard package pitch to advanced package pitch of approximately 2:1, although in some real-world embodiments it may be on the order of 2.4:1. As noted, other embodiments may exhibit higher or lower ratios between the pitch of advanced packages and the pitch of standard packages.

Additionally, as bump pitch shrinks (eg, to the order of 25 microns or 16 microns or less), the ratio of bumps for standard packages to those for advanced packages may change. For example, an advanced package may have 64 bumps in a given area, while a standard package may only have 4 bumps in that area. Or, a standard package might have 16 bumps in a given area, while an advanced package might have 128 bumps in that area, 256 bumps in that area, and so on. In other words, the 16 standard bump to 64 advanced bump swappable ratio can be a suitable value for a range of bump pitches, and as the pitch ratio gets wider, the scalar ratio can similarly track that change.

Embodiments can provide many advantages. One such advantage is that embodiments allow the use of the same die or die base (only a new bump layer, bump via layer, and one or two underlying metal layers need to be flowed out for attachment, depending on the exact implementation) for reuse in advanced and standard packages. Embodiments may also allow common logical interfaces and I/O protocols to work in advanced and standard packages. Embodiments increase die reusability and lifetime/endurance by designing PHY circuits on the die so that the die can be swapped between various in-package interconnection mechanisms. The grains are technically more advantageous than the grains of previous technologies. This reusability can further save significant pre-silicon and post-silicon development costs and allow for faster time-to-market customization of different mix-and-match chiplets/system-on-chips (SOCs) for different market segments.

5 illustrates an example layout 500 of bumps for a data rate of 16 gigabits per second (GT/s) on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments. . Specifically, Figure 5 depicts two example bumps. The bump on the left (shown in Figure 5) may be suitable for use with 4 encapsulation routing layers, while the bump on the right (shown in Figure 5) may be suitable for use with 2 encapsulation routing layers (so the signal only half of the left bump).

6 illustrates an example layout 600 of bumps for a data rate of 32 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments. Specifically, Figure 6 depicts two example bumps. The bump on the left (shown in Figure 6) may be suitable for use with 4 encapsulation routing layers, while the bump on the right (shown in Figure 6) may be suitable for use with 2 encapsulation routing layers (so the signal only half of the left bump).

7 illustrates an example layout 700 of bumps for a data rate of 16 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments. Figure 7 depicts two example bumps in particular. The bottom bump (shown in Figure 7) may be suitable for use with 4 package routing layers, while the top bump (shown in Figure 7) may be suitable for use with 2 package routing layers (so only the bottom half signal of the bump).

8 illustrates an example layout 800 of bumps for a data rate of 32 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments. Figure 8 depicts two example bumps in particular. The bottom bump (shown in Figure 8) may be suitable for use with 4 package routing layers, while the top bump (shown in Figure 8) may be suitable for use with 2 package routing layers (so only the bottom half signal of the bump).

The difference between the embodiments shown in Figures 5 and 6 on the one hand and Figures 7 and 8 on the other hand is that the paired diagrams show the implementation of extractables with a different set of constraints on the encapsulated routing. Different ways to change PHY. The pairing in Figures 7 and 8 is better for intra-channel channel-to-channel skew because the lengths match better and all signals for TX and RX are on the same layer, but for on-die clock distribution and power Conveyance is poor.

9 illustrates an example layout 900 of bumps for an advanced package (eg, in an EMIB or some other similar package with approximately 45 micron pitch) in accordance with various embodiments. It should be noted that one can start with the bump of Figure 9 and convert that bump to work on organic traces (e.g., standard package bumps) as described herein. Alternatively, one can start with the bumps in any of Figures 5-8 and convert those bumps to work on advanced packaging bumps, as described in this article.

Typically, for bumps described in advanced packaging, the lower left corner of the bump map can be considered the "origin" or starting point of the bump matrix. The following rules can be applied to advanced package bump matrices: • In-line signals can be preserved. For example, row 0 can contain the signals: txdataRD0, txdata0, txdata1, txdata2, txdata3, txdata4, txdata5, rxdata58, rxdata59, rxdata60, rxdata61, rxdata62, rxdata63, rxdataRD3, and txdatasb; and • Can implement the power and VSS patterns shown in the bump matrix. Sufficient VSS and power bumps will be configured to meet channel characteristics (FEXT and NEXT) and power delivery requirements.

For one module or two module standard packages, different bump matrices can be configured as described in this article. The lower left corner of the bump map can be thought of as the "origin" or starting point of the bump matrix. The signal exit sequence for x16 and x32 standard package bump matrices can be as shown in this article.

The following rules can be implemented for standard package bump matrices: • In-line signals can be preserved. For example, for x16 (a module standard package interface) shown in Figure 7, row 1 could contain the signals: txdata0, txdata1, txdata9, txdata9, and txdatasb1. • Signals can exit the bump field. Layer 1 and Layer 2 are two different signal routing layers in standard packaging. • Can follow the power and VSS patterns shown in the bump matrix. What is ensured is that sufficient VSS and power bumps will be configured to meet the channel characteristics (FEXT and NEXT) and power delivery requirements.

Figure 10 illustrates an example layout 1000 for bumps on advanced package traces (eg, on packages with approximately 45 micron pitch) in accordance with various embodiments.

For packages with standard pitch (e.g., the packages of Figures 7 or 8, or others such as those of Figures 5 or 6), this can be achieved by placing TX on one side of the package and RX on the other side to create a one-way PHY. This embodiment is possible if it is known that the data always passes through the package in one direction. As a result, for embodiments such as those described in Figures 7 or 8 (or other embodiments herein), such embodiments can operate on a single layer of packaging, thereby optimizing bandwidth, area, and/or cost . Corresponding removable advanced packages may include only TX or RX, thus unidirectional data flow with optimized cost, area, and/or bandwidth.

Figure 11 illustrates a method 1100 of fabricating a microelectronic device, such as a die, in accordance with some embodiments. In operation 1102, processing includes providing a substrate. In operation 1104, processing includes providing physical layer (PHY) circuitry on the substrate, the physical layer (PHY) circuitry including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits. In operation 1106, processing includes providing electrical contact structures at a bottom surface of the device. In operation 1108, processing includes providing signal routing paths extending between the electrical contact structures, on the one hand, and at least some of the RX circuits, or at least some of the TX circuits, on the other hand. In operation 1110, processing includes providing electrical access to the PHY circuit. In operation 1112, processing includes at least one of the following: providing an enable signal into the device through at least some of the electrical pathways to enable a portion of the PHY circuit; or providing a disable signal into the device through at least some of the electrical pathways. The electrical paths are used to enable corresponding parts of the PHY circuit.

Figures 12 and 13 show some examples of an architecture that may include one or more microelectronic assemblies similar to those described above in the context of the embodiments described by way of example in Figures 3, 4A and 4B. Electronic assembly.

12 is a cross-sectional side view of an integrated circuit device assembly 1200 that may include one or more integrated circuit structures, each including any MCP package of embodiments described herein. Integrated circuit device assembly 1200 includes a number of components disposed on a circuit board 1202 (which may be a motherboard, a system board, a motherboard, etc.). The integrated circuit device assembly 1200 includes components disposed on a first side 1240 of the circuit board 1202 and an opposing second side 1242 of the circuit board 1202; generally, the components may be disposed on one or both of the sides 1240 and 1242. above. Any integrated circuit assembly discussed below with reference to integrated circuit device assembly 1200 may include an integrated circuit structure including cascaded MCPs as disclosed herein.

In some embodiments, circuit board 1202 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from each other by layers of dielectric material and by conductive interconnected by sexual through holes. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern for routing electrical signals between components coupled to circuit board 1202 (optionally in combination with other metal layers). In other embodiments, circuit board 1202 may be a non-PCB substrate. The integrated circuit device assembly 1200 shown in FIG. 12 includes a package-on-interposer structure 1236 that is coupled to the first side 1240 of the circuit board 1202 via a coupling component 1216 . The coupling components 1216 may electrically and mechanically couple the package-on-interposer structure 1236 to the circuit board 1202 and may include solder balls (as shown in FIG. 12 ), pins (e.g., as a pin grid array (part of a PGA), contacts (e.g., as part of a ground grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1236 may include an integrated circuit component 1220 coupled to the interposer 1204 via a coupling component 1218 . The coupling components 1218 may take any suitable form for the application, such as those discussed above with reference to the coupling components 1216. Although a single integrated circuit component 1220 is shown in FIG. 12 , multiple integrated circuit components may be coupled to interposer 1204 ; indeed, additional interposers may be coupled to interposer 1204 . Interposer 1204 may provide an intermediate substrate to bridge circuit board 1202 and integrated circuit assembly 1220 .

Integrated circuit assembly 1220 may be a packaged or unpackaged integrated circuit product including one or more integrated circuit dies. Packaged integrated circuit assemblies include one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit dies and the packaging substrate are encapsulated in a cast material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit assembly 1220, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be attached directly to the interposer 1204 . Integrated circuit components 1220 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SOC), processor core, graphics processor unit (GPU), accelerator, chipset processing processor), I/O controller, memory, or network interface controller. In some embodiments, integrated circuit assembly 1220 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, Electrostatic discharge (ESD) devices, and memory devices.

In embodiments in which integrated circuit device 1220 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit device) or two or more different types (Heterogeneous multi-die integrated circuit components). Multi-die integrated circuit components may be referred to as multi-chip packages (MCP) or multi-chip modules (MCM).

In addition to including one or more processor units, integrated circuit component 1220 may include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache, input/output (I/O) O) controller, or memory controller. Any such additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These individual integrated circuit dies may be referred to as "dielets." In embodiments where the integrated circuit device includes multiple integrated circuit dies, interconnections between the dies may be through the packaging substrate, one or more silicon interposers, or one or more silicon interposers embedded in the packaging substrate. Silicon bridges such as the Intel® Embedded Multi-Die Interconnect Bridge (EMIB), or combinations thereof.

Generally, the interposer 1204 can extend the connection to a wider spacing or reroute the connection to a different connection. For example, interposer 1204 may couple integrated circuit component 1220 to a set of ball grid array (BGA) conductive contacts used to couple coupling component 1216 of circuit board 1202 . In the embodiment shown in Figure 12, integrated circuit assembly 1220 and circuit board 1202 are attached to opposite sides of interposer 1204; in other embodiments, integrated circuit assembly 1220 and circuit board 1202 may be attached to the same side of interposer 1204. In some embodiments, three or more components may be interconnected by interposer 1204 .

In some embodiments, interposer 1204 may be formed as a PCB that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 1204 may be formed of epoxy, fiberglass reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, interposer 1204 may be formed from alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III -Group V and IV materials. Interposer 1204 may include metal interconnects 1208 and vias 1210 , including but not limited to through-hole vias 1210 - 1 (extending from first side 1250 of interposer 1204 to second side 1254 of interposer 1204 ), blind vias 1210 -2 (extending from the first or second side 1250 or 1254 of the interposer 1204 to the inner metal layer), and buried via 1210-3 (connecting the inner metal layer).

In some embodiments, interposer 1204 may include a silicon interposer. A through-silicon via (TSV) extending through the silicon interposer may connect a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, an interposer 1204 including a silicon interposer may further include one or more routing layers for routing connections on a first side of the interposer 1204 to an opposite second side of the interposer 1204 .

The interposer 1204 may also include embedded devices 1214 including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any package-on-interposer structure known in the art. In embodiments, the interposer is not a printed circuit board.

The integrated circuit device assembly 1200 may include an integrated circuit component 1224 coupled to the first side 1240 of the circuit board 1202 by a coupling component 1222 . Coupling component 1222 may take the form of any of the embodiments discussed above with reference to coupling component 1216 , and integrated circuit component 1224 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1220 .

The integrated circuit device assembly 1200 shown in FIG. 12 may include a stack-up structure 1234 coupled to the second side 1242 of the circuit board 1202 by a coupling component 1228. The stack-up structure 1234 may include an integrated circuit component 1226 and an integrated circuit component 1232 coupled together by a coupling component 1230 such that the integrated circuit component 1226 is disposed between the circuit board 1202 and the integrated circuit component 1232 . Coupling components 1228 and 1230 may take the form of any embodiment of coupling component 1216 discussed above, and integrated circuit components 1226 and 1232 may take the form of any embodiment of integrated circuit component 1220 discussed above. The stack structure 1234 may be configured in the form of any stack structure known in the art.

13 is a block diagram of an example electrical device 1300 that may include one or more embodiment MCPs disclosed herein. For example, any suitable components of computing device 1300 may include one or more of the integrated circuit device assembly 1200, integrated circuit components 1220, and/or embodiment MCPs disclosed herein. A number of components are shown in Figure 13 as included in electrical device 1300, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1300 may be attached to one or more motherboards, motherboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-chip (SoC) die.

Additionally, in various embodiments, the electrical device 1300 may not include one or more components shown in FIG. 13 , but the electrical device 1300 may include interface circuitry to couple to the one or more components. For example, electrical device 1300 may not include display device 1306 but may include display device interface circuitry (eg, connector and driver circuitry) that may couple to display device 1306 . In another set of examples, electrical device 1300 may not include audio input device 1324 or audio output device 1308, but may include audio input or audio output device interface circuitry that may couple audio input device 1324 or audio output device 1308 (e.g., , connectors and supporting circuits).

Electrical device 1300 may include one or more processor units 1302 (eg, one or more processor units). As used herein, the terms "processor unit", "processing unit" or "processor" may mean the processing of electronic data from a register and/or memory to convert the electronic data into a form that can be stored in a temporary store. Any device or part of a device that contains other electronic data in the device and/or memory. Processor unit 1302 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APU), field programmable gate array (FPGA), neural network processing unit (NPU), data processor unit (DPU), accelerator (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controlled cryptographic processor (a special-purpose processor that executes cryptographic algorithms in hardware), server processor, controller, or any other suitable type of processing unit. Because of this, the processor unit may be called an XPU (or xPU).

Electrical device 1300 may include memory 1304, which may itself include one or more memory devices, such as volatile memory (eg, dynamic random access memory (DRAM), static random access memory (SRAM)) , non-volatile memory (eg, read-only memory (ROM), flash memory, chalcogen phase change-based non-voltage memory), solid-state memory, and/or hard disk. In some embodiments, memory 1304 may include memory located on the same integrated circuit die as processor unit 1302 . This memory can be used as cache memory (for example, level one (L1) cache, level two (L2) cache, level three (L3) cache, level four (L4) cache, last level cache (LLC) )), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device 1300 may include one or more processor units 1302 that are heterogeneous or asymmetrical to another processor unit 1302 in the electrical device 1300 . There are various differences between the processor units 1302 in the system in terms of a range of merit measures including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between processor units 1302 in electrical device 1300 .

In some embodiments, electrical device 1300 may include communication component 1312 (eg, one or more communication components). For example, communications component 1312 may manage wireless communications for the transmission of data to and from electrical device 1300 . The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that use modulated electromagnetic radiation to convey information through non-solid-state media. The term "wireless" does not imply that the associated device does not contain any wires, although in some embodiments they may not be included.

Communications component 1312 may implement any of a variety of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment ), the Long Term Evolution (LTE) project, and any amendments, updates, and/or revisions (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks, an acronym that stands for Worldwide Microwave Access Interoperability, which is the standard used for conformance and interoperability of the IEEE 802.16 standard. Certification mark for products tested for safety. The communication component 1312 may be based on Global System for Mobile communications (GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network to operate. The communications component 1312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communications component 1312 may be based on Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimized (EV-DO), and derivatives thereof, as well as technologies designated as Operates on any other wireless protocol from 3G, 4G, 5G and beyond. In other embodiments, communications component 1312 may operate in accordance with other wireless protocols. Electrical device 1300 may include one or more antennas 1322 to facilitate wireless communications and/or to receive other wireless communications (eg, AM or FM radio transmissions).

In some embodiments, communications component 1312 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (eg, IEEE 802.3 Ethernet standard). As mentioned above, communication component 1312 may include multiple communication components. For example, the first communication component 1312 may be dedicated to shorter range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1312 may be dedicated to wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE , EV-DO, etc. for longer distance wireless communication. In some embodiments, the first communication component 1312 may be dedicated to wireless communications and the second communication component 1312 may be dedicated to wired communications.

Electrical device 1300 may include a battery/power circuit 1314. Battery/power circuitry 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or be used to couple components of electrical device 1300 to an energy source separate from electrical device 1300 (e.g., AC line power ) circuit.

Electrical device 1300 may include display device 1306 (or corresponding interface circuitry, as discussed above). For example, display device 1306 may include one or more embedded or wired or wirelessly connected visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display , or flat panel display.

Electrical device 1300 may include audio output device 1308 (or corresponding interface circuitry, as discussed above). For example, audio output device 1308 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as speakers, headphones, or earphones.

Electrical device 1300 may include audio input device 1324 (or corresponding interface circuitry, as discussed above). For example, audio input device 1324 may include any embedded or wired or wirelessly connected device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., with a Musical Instrument Digital Interface (MIDI) output). instrument). Electrical device 1300 may include a global navigation satellite system (GNSS) device 1318 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. As is known in the art, GNSS device 1318 can communicate with satellite-based systems and can determine the geographic location of electrical device 1300 based on information received from one or more GNSS satellites.

Electrical device 1300 may include additional output devices 1310 (or corresponding interface circuitry, as discussed above). Examples of additional output devices 1310 may include audio codecs, video codecs, printers, wired or wireless transmitters to provide information to other devices, or additional storage devices.

Electrical device 1300 may include additional input devices 1320 (or corresponding interface circuitry, as discussed above). Examples of additional input devices 1320 may include an accelerometer, a gyroscope, a compass, an image capture device (eg, a monoscopic or stereo camera), a trackball, a trackpad, a trackpad, a keyboard, a cursor control device such as a mouse, Pen, touch screen, proximity sensor, microphone, barcode reader, quick response (QR) code reader, electrocardiogram sensor (ECG), PPG (photoplethysmogram) sensor, skin Current response sensor, any other sensor, or radio frequency identification (RFID) reader.

Electrical device 1300 may have any desired form factor, such as a handheld or portable electronic device (e.g., cell phone, smartphone, mobile Internet device, music player, tablet, laptop, 2-in-1 Switch computers, portable all-in-ones, small notebooks, ultra notebooks, personal digital assistants (PDAs), ultra mobile PCs, portable game consoles, etc.), desktop electrical devices, servers, rack-level computing solutions Solutions (e.g., blade, tray, or slide computing systems), workstations or other network computing components, printers, scanners, monitors, set-top boxes, game control units, stationary game consoles, smart TVs, vehicles Control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (for example, computing systems that are part of vehicles, smart home appliances, consumer electronics products or equipment, and manufacturing equipment). In some embodiments, the electrical device 1300 may be any other electronic device that processes data. In some embodiments, electrical device 1300 may include multiple discrete physical components. Given the range of devices that electrical device 1300 may manifest in various embodiments, electrical device 1300 may be referred to as a computing device or computing system in some embodiments.

Figure 10 is a flow diagram of a process 1000 in accordance with some embodiments. In operation 1002, the process includes providing a plurality of first dies. In operation 1004, the process includes providing an encapsulation layer on the first dies to form a first layer of the semiconductor subassembly. In operation 1006, the process includes providing a first dielectric layer over the first layer to form a first layer and a first dielectric layer subassembly. In operation 1008, the process includes providing a passive heat sink interposer. In operation 1010, the process includes providing a second dielectric layer over the passive heat spreader interposer to form a passive heat spreader interposer and second dielectric layer subassembly. In operation 1012 , the process includes forming an interface layer between the passive heat spreader interposer and the first layer and mechanically coupling the passive heat spreader interposer and the first layer, the interface layer providing direct dielectric to dielectric bonding. , including a first dielectric sublayer directly adjacent to the first layer and formed from the first dielectric layer, and a second dielectric sublayer directly adjacent to the first dielectric sublayer, formed from the second dielectric layer, and including an amorphous material. layer. In operation 1014, the process includes providing a second layer including a substrate. In operation 1016, processing includes electrically coupling the substrate to the first dies.

Throughout this specification, multiple instances may implement components, operations, or structures that are described as a single instance. Although individual operations of one or more methods are illustrated and described as individual operations, the individual operations or operations may be performed concurrently and need not be performed in the order shown. Structures and functionality presented as separate components in example configurations may be implemented as combined structures or components. Similarly, structure and functionality presented as a single component may be implemented as separate components. Such and other changes, modifications, additions, and improvements fall within the scope of the subject matter hereof.

Although an overview of the embodiments has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of the embodiments of the invention. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term "invention" for convenience only and without intention to voluntarily limit the scope of this application to any single disclosure or The concept of invention, if in fact more than one is revealed.

The embodiments shown herein are described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present invention. Therefore, the detailed description is not to be regarded in a limiting sense, and the scope of various embodiments is defined only by the scope of the appended claims together with the full scope of equivalents to which such claims are entitled.

It should also be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the scope of the present example embodiment. The first contact point and the second contact point are both contacts, but they are not the same contact point.

As used in the description of example embodiments and additional examples, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein means and encompasses any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms "comprising" and/or "including", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements, and/or components but do not exclude one or more The presence or addition of other features, integers, steps, operations, elements, components, and/or groups thereof.

For the purposes of this invention, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of this invention, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

In embodiments, the phrase "A is on B" means that at least a portion of A is in direct physical contact or in indirect physical contact with at least a portion of B (having one or more other features between A and B).

In this specification, "A and B are adjacent" means that at least a part of A and at least a part of B are in direct physical contact.

In this specification, "B is between A and C" means that at least a part of B is in or along the space that separates A and C, and at least a part of B is directly or indirectly connected to A and C. get in touch with.

In this specification, "A is attached to B" means that at least a portion of A is mechanically attached to at least a portion of B, either directly or indirectly (with one or more other features between A and B ).

The use of reference numbers separated by "/", such as, for example, "102/104", means 102 or 104 as applicable. Otherwise, a forward slash ("/") as used herein means "and/or".

The use of the techniques and structures presented in this article can be detected using tools such as: electron microscopy, including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nanobeam electron microscopy (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffractometer (XRD); energy dispersive x-ray spectrometer (EDX); secondary ion mass spectrometer (SIMS); flight Temporal SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; high-resolution physical or chemical analysis, to name just a few suitable example analysis tools. In particular, such tools may refer to integrated circuits including at least one MCP including an interposer bonded to the MCP sub-assembly via direct dielectric-to-dielectric bonding as described above.

In some embodiments, the techniques, processes, and/or methods described herein may be examined based on the structures formed therein. Furthermore, in some embodiments, the techniques and structures described herein may be examined in terms of the benefits derived therefrom. Many configurations and variations will be apparent in view of the present invention.

The description may use perspective-based descriptions such as top/bottom, inside/outside, above/below, etc. Such descriptions are provided merely to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular direction.

The description may use the phrases "in one embodiment," "according to some embodiments," "according to an embodiment," or "in an embodiment," which may each mean one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc., as used with respect to embodiments of the present invention, are synonymous.

As used herein, "coupled" means that two or more elements are in direct physical contact, or that two or more elements are in indirect physical contact with each other but still cooperate or interact with each other (i.e., One or more other elements are coupled or connected between elements that are said to be mutually coupled to each other). The term "directly coupled" means that two or more elements are in direct contact.

As used herein, the term "module" means being part of, or including the following: ASIC, electronic circuit, system-on-chip, processor (shared, dedicated, or grouped), solid-state device, execution One or more software or firmware programs, memory (shared, dedicated, or grouped), combinational logic, and/or other suitable components that provide the functionality described.

As used herein, the term "conductivity" in some examples may mean having a conductivity greater than or equal to one meter per meter at 20 degrees Celsius. Siemens (S/m) electrical conductivity is a property of materials. Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

As used herein, an "integrated circuit structure" may include one or more microelectronic dies.

In corresponding drawings of embodiments, signals, currents, electrical biases, or magnetic or electrical polarities may be represented as lines. Some lines may be thicker to indicate multiple component signal paths and/or have arrows at one or more ends to indicate the main direction of information flow. Such instructions are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic element. Any representation of signals, polarity, current, voltage, etc., as design needs or preferences dictate, may actually include one or more signals that may travel in either direction and may be of any suitable type. Signal scheme implementation.

Throughout this specification, and within the scope of the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection between the elements being connected, without any intervening means. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected elements, or an indirect connection through one or more passive or active intervening devices. The term "signal" may mean at least one current signal, voltage signal, magnetic signal, or data/clock signal. "a", "an", and "the" are intended to include plural references. The meaning of "in" includes "in" and "on top".

The terms "substantially," "nearly," "approximately," "nearly," and "approximately" generally mean within +/-10% of the target value (unless specifically stated). Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc., to describe common objects only indicates that they refer to different instances of similar objects and does not mean that all The objects described must be in a given sequence, whether in time, space, ranking, or in any other way.

For purposes of the examples, the transistors in the various circuits and logic blocks described herein are metal oxide semiconducting (MOS) transistors or derivatives thereof, where MOS transistors include drains, sources, gates, and bodies. terminal. Transistors and/or MOS transistor derivatives also include triple-gate and FinFET transistors, wrap-gate cylindrical transistors, tunneling FETs (TFETs), square wire or rectangular strip transistors, ferroelectric FETs (FeFETs) ), or other devices that perform transistor functions, such as carbon nanotubes or spintronic devices. The MOSFET's symmetrical source and drain terminals, that is, are the same terminals and are used interchangeably here. TFET devices, on the other hand, have asymmetric source and drain terminals. It will be understood by those skilled in the art that other transistors may be used without departing from the scope of the present invention, for example, bipolar junction transistors - BJT PNP/NPN, BiCMOS, CMOS, eFET, etc. wait. The term "MN" represents an n-type transistor (eg, nMOS, NPN BJT, etc.), and the term "MP" represents a p-type transistor (eg, pMOS, PNP BJT, etc.).

For purposes of illustration, the foregoing description has been described with reference to specific example embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and its practical application, thereby enabling others skilled in the art to best utilize the various examples with various modifications as are suited to the particular use contemplated. Example.

Example

Some non-limiting example embodiments are set forth below.

Example 1 includes a microelectronic device, which includes a substrate; a physical layer (PHY) circuit including a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits on the substrate; and an electrical contact structure on the device. at the bottom surface; signal routing paths extending between the electrical contact structures on the one hand and at least some of the RX circuits or at least some of the TX circuits on the other hand; The PHY circuit is configured to meet at least one of the following conditions; the enable signal input to the device passes through at least some of the electrical paths for enabling a part of the PHY circuit; and the disable signal input to the device passes through At least some of the electrical paths are used to disable corresponding parts of the PHY circuit.

Example 2 includes the subject matter of Example 1, wherein the electrical paths include at least one fuse or register for at least one of enabling or disabling the corresponding portion of the PHY circuit.

Example 3 includes the subject matter of Example 1, wherein the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths, using To enable 1/2 of the RX circuits and 1/2 of the TX circuits; and the disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1/2 of the RX circuits and 1/2 of such TX circuits.

Example 4 includes the subject matter of Example 1, wherein the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths, using To enable 1/4 of the RX circuits and 1/4 of the TX circuits; and the disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3/4 of the RX circuits and 3/4 of such TX circuits.

Example 5 includes the subject matter of Example 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between all such TX circuits.

Example 6 includes the subject matter of Example 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between portions of the TX circuits.

Example 7 includes the subject matter of Example 6, wherein: the portion of the RX circuits includes 1/2 of the RX circuits and the portion of the TX circuits includes 1/2 of the TX circuits; or the portion of the TX circuits includes The RX circuits include 1/4 of the RX circuits and the portion of the TX circuits includes or 1/4 of the TX circuits.

Example 8 includes the subject matter of Example 1, wherein the RX circuits are in a first region of the device and the TX circuits are in a second region of the device that is different from the first region.

Example 9 includes the subject matter of Example 1, wherein the signal routing paths include conductive traces and vias of the device.

Example 10 includes the subject matter of Example 1, wherein the electrical contact structures include bumps.

Example 11 includes the subject matter of Example 10, wherein the bumps include C4 bumps.

Example 12 includes the subject matter of Example 1, wherein the spacing between the electrical contact structures is between about 110 microns and about 130 microns.

Example 13 includes the subject matter of Example 1, wherein the spacing between the electrical contact structures is between about 36 microns and about 55 microns.

Example 14 includes a semiconductor package, the semiconductor package includes: a packaging substrate; two pairs of dies, on the packaging substrate, including a first pair of dies and a second pair of dies, the first pair of dies including a first die and a second die, and the second pair of die includes a third die and a fourth die, wherein: individual die of the die include: die substrate; physical layer (PHY) circuit, on the die The chip substrate includes a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits; an electrical contact structure is at the bottom surface of the chip; the individual chips of the first chip and the second chip include The signal routing path extends between the electrical contact structures on the one hand and all the RX circuits and all the TX circuits on the other hand; the third die and the fourth die Individual dies of the die include signal routing paths extending between the electrical contact structures thereof on the one hand, and a portion of the RX circuits and a portion of the TX circuits thereof on the other hand; wherein the packaging substrate Includes a first packaged signal routing path and a second packaged signal routing path extending between the first die and the second die to provide device-to-device (D2D) therebetween signal interconnection, and the second package signal routing path extends between the first die and the second die to provide device-to-device (D2D) signal interconnection therebetween.

Example 15 includes the subject matter of Example 14, wherein the portion of the RX circuits includes 1/2 of the RX circuits, and the portion of the TX circuits includes 1/2 of the TX circuits.

Example 16 includes the subject matter of Example 14, wherein the portion of the RX circuits includes 1/4 of the RX circuits, and the portion of the TX circuits includes 1/4 of the TX circuits.

Example 17 includes the subject matter of Example 14, wherein for an individual die of the die, the RX circuits are on a first region of the die, and the TX circuits are on a different region of the die than the first region of the die. A second area of one area.

Example 18 includes the subject matter of Example 14, wherein, for an individual die of the die, the signal routing paths include conductive traces and vias of the die.

Example 19 includes the subject matter of Example 14, wherein for individual dies of the dies, the electrical contact structures include bumps.

Example 20 includes the subject matter of Example 19, wherein the electrical contact structures include controlled collapse wafer collection bumps for individual dies of the dies.

Example 21 includes the subject matter of Example 14, wherein the spacing between the electrical contact structures is between about 110 microns and about 130 microns for individual dies of the first die and the second die. , and for each of the third die and the fourth die, the spacing between the electrical contact structures is between about 36 microns and about 55 microns.

Example 22 includes the subject matter of Example 14, wherein at least one of the first package signal routing paths and the second package signal routing paths extend through and contact a layer of material of the package substrate.

Example 23 includes the subject matter of Example 22, wherein the material layers include organic materials.

Example 24 includes the subject matter of Example 14, wherein the packaging substrate defines a cavity therein, the packaging substrate further includes an interconnect bridge within the cavity, the first package signal routing paths and the second package signals One of at least one of the routing paths extends within the interconnect bridge.

Example 25 includes the subject matter of Example 14, wherein the first, second, third, and fourth grains are identical to each other.

Example 26 includes the subject matter of Example 14, wherein individual dies of the dies include electrical vias leading to the PHY circuit and configured to satisfy at least one of the following conditions; input to the Enable signals of individual die of the die are used to enable a part of the PHY circuit through at least some of the electrical paths; or disable signals of individual die input to the die pass through at least some of the electrical paths. Path, used to disable the corresponding part of the PHY circuit.

Example 27 includes the subject matter of Example 26, wherein, for individual dies of the dies, the electrical paths include at least one fuse or register for enabling the corresponding portion of the PHY circuit or disabling the At least one of the corresponding portions of the PHY circuit.

Example 28 includes an integrated circuit (IC) device assembly including: a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board, each of the integrated circuit components including a or a plurality of semiconductor packages, each of which includes: a packaging substrate; a plurality of dies, on which the individual dies of the dies include: a die substrate; a physical layer (PHY) circuit , on the die substrate, including a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits; an electrical contact structure at the bottom surface of the die; a signal routing path, on the one hand, at the electrical contacts Extending between structures, on the other hand extending between at least some of the RX circuits or at least some of the TX circuits; an electrical path leading to the PHY circuit and configured to meet at least one of the following conditions; input to the The enable signal of the die passes through at least some of the electrical paths to enable a part of the PHY circuit; and the disable signal input to the die passes through at least some of the electrical paths to disable the PHY circuit. corresponding portions; and wherein the package substrate includes a package signal routing path extending between a first die of the plurality of dies and a second die of the plurality of dies to provide a device therebetween. Signal interconnection of devices (D2D).

Example 29 includes the subject matter of Example 28, wherein for individual dies of the dies, the electrical paths include at least one fuse or register for enabling the corresponding portion of the PHY circuit or disabling the At least one of the corresponding portions of the PHY circuit.

Example 30 includes the subject matter of Example 28, wherein, for an individual die of the die, the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: a cause input to the die. The enable signal passes through at least some of the electrical paths to enable 1/2 of the RX circuits and 1/2 of the TX circuits; and the disable signal input to the die passes through at least some of the electrical paths. , used to disable the remaining 1/2 of the RX circuits and 1/2 of the TX circuits.

Example 31 includes the subject matter of Example 28, wherein, for an individual die of the die, the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: a signal input to the die. The enable signal passes through at least some of the electrical paths to enable 1/4 of the RX circuits and 1/4 of the TX circuits; and the disable signal input to the die passes through at least some of the electrical paths. , used to disable the remaining 3/4 of the RX circuits and 3/4 of the TX circuits.

Example 32 includes the subject matter of Example 28, wherein for individual dies of the dies, some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the Signal routing paths extend between the corresponding electrical contact structures and all of the TX circuits.

Example 33 includes the subject matter of Example 28, wherein for individual dies of the dies, some of the signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuitry, and some of the Signal routing paths extend between corresponding electrical contact structures and portions of the TX circuits.

Example 34 includes the subject matter of Example 33, wherein for an individual die of the dies, the portion of the RX circuits includes 1/2 of the RX circuits and the portion of the TX circuits includes 1/2 of the the TX circuits; or the portion of the RX circuits includes 1/4 of the RX circuits and the portion of the TX circuits includes or 1/4 of the TX circuits.

Example 35 includes the subject matter of Example 28, wherein for an individual die of the die, the RX circuits are on a first region of the die and the TX circuits are on a first region of the die and the third region of the die. A second area that is different from the first area.

Example 36 includes the subject matter of Example 28, wherein, for an individual die of the die, the signal routing paths include conductive traces and vias of the die.

Example 37 includes the subject matter of Example 28, wherein for individual dies of the dies, the electrical contact structures include bumps.

Example 38 includes the subject matter of Example 37, wherein the electrical contact structures include controlled collapse wafer collection bumps for individual dies of the dies.

Example 39 includes the subject matter of Example 28, wherein the spacing between the electrical contact structures is between about 110 microns and about 130 microns for individual die of the die.

Example 40 includes the subject matter of Example 28, wherein the spacing between the electrical contact structures is between about 36 microns and about 55 microns for individual dies of the dies.

Example 41 includes the subject matter of Example 28, wherein the package signal routing paths extend through and contact a layer of material of the package substrate.

Example 42 includes the subject matter of Example 41, wherein the material layers include organic materials.

Example 43 includes the subject matter of Example 28, wherein the package substrate defines a cavity therein, the package further includes an interconnect bridge within the cavity, the package signal routing paths extending within the interconnect bridge.

Example 44 includes the subject matter of Example 28, wherein the first grain and the second grain are identical to each other.

Example 45 includes the subject matter of Example 28, wherein: the package signal routing paths are first package signal routing paths; the plurality of dies further include third dies and fourth dies disposed on the package substrate; The package substrate further includes a second package signal routing path extending between the third die and the second die to provide device-to-device (D2D) signal interconnection therebetween; for the first die With an individual die of the second die: the signal routing paths of the first group extend between the corresponding electrical contact structures and all of the RX circuits; and are different from the second group of the first group A set of the signal routing paths extends between the corresponding electrical contact structures and all of the TX circuits; and for individual dies of the third die and the fourth die: the first set of the The signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuits; and a second group of signal routing paths different from the first group are between the corresponding electrical contact structures. and extend between portions of such TX circuits.

Example 46 includes a method of manufacturing a microelectronic device, including: providing a substrate; providing a physical layer (PHY) circuit on the substrate, the physical layer (PHY) circuit including a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits. circuitry; providing electrical contact structures at the underside of the device; providing signal routing paths extending between the electrical contact structures on the one hand and at least some of the RX circuits or at least some of the TX circuits on the other hand extending between; and providing electrical paths to the PHY circuit; at least one of the following: providing an enable signal into the device to enable a portion of the PHY circuit through at least some of the electrical paths; and providing a disable signal into the device, through at least some of the electrical paths to disable corresponding portions of the PHY circuit.

Example 47 includes the subject matter of Example 46, wherein the electrical paths include at least one fuse or register for at least one of enabling or disabling the corresponding portion of the PHY circuit.

Example 48 includes the subject matter of Example 46, wherein the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths, using To enable 1/2 of the RX circuits and 1/2 of the TX circuits; and the disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1/2 of the RX circuits and 1/2 of such TX circuits.

Example 49 includes the subject matter of Example 46, wherein the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: enable signals input to the device pass through at least some of the electrical paths, using To enable 1/4 of the RX circuits and 1/4 of the TX circuits; and the disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3/4 of the RX circuits and 3/4 of such TX circuits.

Example 50 includes the subject matter of Example 46, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between all such TX circuits.

Example 51 includes the subject matter of Example 46, wherein some of the signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between portions of the TX circuits.

Example 52 includes the subject matter of Example 51, wherein: the portion of the RX circuits includes 1/2 of the RX circuits and the portion of the TX circuits includes 1/2 of the TX circuits; or the portion of the TX circuits includes The RX circuits include 1/4 of the RX circuits and the portion of the TX circuits includes or 1/4 of the TX circuits.

Example 53 includes the subject matter of Example 46, wherein the RX circuits are in a first region of the device and the TX circuits are in a second region of the device that is different from the first region.

Example 54 includes the subject matter of Example 46, wherein the signal routing paths include conductive traces and vias of the device.

Example 55 includes the subject matter of Example 46, wherein the electrical contact structures include bumps.

Example 56 includes the subject matter of Example 55, wherein the electrical contact structures include controlled collapse wafer collection bumps.

Example 57 includes the subject matter of Example 46, wherein the spacing between the electrical contact structures is between about 110 microns and about 130 microns.

Example 58 includes the subject matter of Example 46, wherein the spacing between the electrical contact structures is between about 36 microns and about 55 microns.

100,200,300:Microelectronics assembly 104,204,304:Package substrate 108,116,208,216,308a,308b,316a,316b: grains 112,212,312a,312b: top surface 136,336a,336b: trace 159: Conductive structure 204:Substrate assembly 210,220:Substrate conductive contact 222: Interconnect Bridge 224, 226: Bridge conductive contacts 228: Bridge surface 232: Bridge via 236:Bridge conductive traces 244: Conductive contact 256: Electrical contact structure or joint 260,1216,1218,1222,1228,1230: coupling components 264,266: Grain conductive contacts 301a: Standard interconnection part 301b: Advanced interconnection section 309a, 309a’, 317a, 317a’, 309b, 309b’, 317b, 317b’: RX circuit 311a, 311a’, 319a, 319a’, 311b, 311b’, 319b, 319b’: TX circuit 359: Electrical contact structure 356a,356b:C4 bump 500,600,700,800,900,1000: Example layout 1100: Manufacturing method 1102-1112: Operation 1200: Integrated circuit device assembly 1202:Circuit board 1204: Intermediary layer 1208:Metal interconnection 1210:Through hole 1220: Integrated circuit components 1234:Stacked structure 1236:Stacked structure 1300: Electrical devices 1302: Processor unit 1304:Memory 1306:Display device 1308:Audio output device 1310: Additional output device 1312: Communication component 1314:Battery/power circuit 1318:GNSS device 1320: Additional input device 1322:antenna 1324:Audio input device

Embodiments of the invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be construed as limiting the invention to specific embodiments. , but only for explanation and understanding.

[FIG. 1] is a cross-sectional view of a microelectronic assembly including an example of a standard interconnection mechanism.

[Figure 2] is a cross-sectional view of a microelectronic assembly including an example of an advanced interconnection mechanism.

[Fig. 3] is a cross-sectional view of the microelectronic assembly according to the embodiment.

[FIG. 4A] is a bottom plan view of a first die including C4 bumps according to an advanced interconnect mechanism, according to an embodiment.

[FIG. 4B] is a bottom plan view of a first die including C4 bumps according to an advanced interconnection mechanism, according to an embodiment.

[FIG. 5] illustrates an example of bumps for a data rate of 16 gigatransmissions per second (GT/s) on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments Layout 500.

[FIG. 6] illustrates an example layout 600 of bumps for a data rate of 32 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments.

[FIG. 7] illustrates an example layout 700 of bumps for a data rate of 16 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments.

[FIG. 8] illustrates an example layout 800 of bumps for a data rate of 32 GT/s on standard package traces (eg, on a package with approximately 110 micron pitch) in accordance with various embodiments.

[FIG. 9] illustrates example bumps for use in advanced packaging (eg, in an EMIB or some other similar package with approximately 45 micron pitch) in accordance with various embodiments.

[FIG. 10] illustrates example bumps on advanced package traces (eg, on a package with approximately 45 micron pitch) in accordance with various embodiments.

[Fig. 11] is a flowchart of processing according to some embodiments.

[FIG. 12] is a cross-sectional side view of an integrated circuit device assembly that may include microelectronic structures in accordance with any of the embodiments disclosed herein.

[FIG. 13] is a block diagram of an example electrical device that may include microelectronic structures in accordance with any of the embodiments disclosed herein.

100:Microelectronics assembly

104:Package substrate

108,116: grain

112:Top surface

156:Connector

159: Conductive structure

Claims (25)

A microelectronic device containing: substrate; The physical layer (PHY) circuit includes a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits on the substrate; electrical contact structure on the underside of the device; signal routing paths extending between the electrical contact structures on the one hand and at least some of the RX circuits or at least some of the TX circuits on the other hand; and An electrical path leading to the PHY circuit and configured to meet at least one of the following conditions; The enable signal input to the device is used to enable a portion of the PHY circuit through at least some of the electrical pathways; or The disable signal input to the device passes through at least some of the electrical paths to disable corresponding parts of the PHY circuit. The microelectronic device of claim 1, wherein the electrical paths include at least one fuse or register for at least one of enabling the corresponding part of the PHY circuit or disabling the corresponding part of the PHY circuit. The microelectronic device of claim 1, wherein the electrical paths leading to the PHY circuit are configured to meet at least one of the following conditions: The enable signal input to the device passes through at least some of the electrical paths to enable 1/2 of the RX circuits and 1/2 of the TX circuits; or The disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1/2 of the RX circuits and 1/2 of the TX circuits. The microelectronic device of claim 1, wherein the electrical paths leading to the PHY circuit are configured to meet at least one of the following conditions: The enable signal input to the device passes through at least some of the electrical paths to enable 1/4 of the RX circuits and 1/4 of the TX circuits; or The disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3/4 of the RX circuits and 3/4 of the TX circuits. The microelectronic device of claim 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between all such TX circuits. The microelectronic device of claim 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and part of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures. Contact structures extend between portions of the TX circuits. The microelectronic device of claim 6, wherein: The portion of the RX circuits includes 1/2 of the RX circuits and the portion of the TX circuits includes or 1/2 of the TX circuits; or The portion of the RX circuits includes 1/4 of the RX circuits and the portion of the TX circuits includes or 1/4 of the TX circuits. The microelectronic device of claim 1, wherein the electrical contact structures include bumps. The microelectronic device of claim 1, wherein the spacing between the electrical contact structures is between about 110 microns and about 130 microns. The microelectronic device of any one of claims 1 to 9, wherein the spacing between the electrical contact structures is between about 36 microns and about 55 microns. A semiconductor package containing: packaging substrate; Two pairs of die, on the packaging substrate, include a first pair of die and a second pair of die, the first pair of die includes a first die and a second die, and the second pair of die includes a The third grain and the fourth grain, among which: Individual dies of such dies include: grain substrate; The physical layer (PHY) circuit includes a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits on the die substrate; The electrical contact structure is on the bottom surface of the grain; Individual dies of the first die and the second die include signal routing paths extending between their electrical contact structures on the one hand, and all of their RX circuits and all of their RX circuits on the other hand. Extend between TX circuits; Individual dies of the third die and the fourth die include signal routing paths extending between the electrical contact structures thereof on the one hand, and a portion of the RX circuitry and a portion of the RX circuitry on the other hand. Extend between TX circuits; The packaging substrate includes a first packaging signal routing path and a second packaging signal routing path. The first packaging signal routing path extends between the first die and the second die to provide a device between them. Device-to-device (D2D) signal interconnection, and the second package signal routing path extends between the third die and the fourth die to provide device-to-device (D2D) signal interconnection therebetween. The semiconductor package of claim 11, wherein the portion of the RX circuits includes 1/2 of the RX circuits, and the portion of the TX circuits includes 1/2 of the TX circuits. The semiconductor package of claim 11, wherein the portion of the RX circuits includes 1/4 of the RX circuits, and the portion of the TX circuits includes 1/4 of the TX circuits. The semiconductor package of claim 11, wherein, for individual dies of the dies, the RX circuits are in a first region of the die, and the TX circuits are in a region of the die that is different from the first region of the die. The second area of the area. The semiconductor package of claim 11, wherein for an individual die of the die, the signal routing paths include conductive traces and vias of the die. The semiconductor package of claim 11, wherein for individual dies of the dies, the electrical contact structures include bumps. The semiconductor package of claim 16, wherein for individual dies of the dies, the electrical contact structures include controlled collapse die collection bumps. The semiconductor package of any one of claims 11 to 17, wherein, for individual dies of the first die and the second die, the spacing between the electrical contact structures is between about 110 microns and Between approximately 130 microns, and for individual dies of the third die and the fourth die, the spacing between the electrical contact structures is between approximately 36 microns and approximately 55 microns. The semiconductor package of claim 11, wherein at least one of the first package signal routing paths and the second package signal routing paths extends through and contacts a material layer of the packaging substrate. An integrated circuit (IC) device assembly including: printed circuit boards; and A plurality of integrated circuit components coupled to the printed circuit board, each of the integrated circuit components including one or more semiconductor packages, each of the individual semiconductor packages including: packaging substrate; A plurality of die, on the packaging substrate, individual die of the die include: grain substrate; The physical layer (PHY) circuit includes a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits on the die substrate; The electrical contact structure is on the bottom surface of the grain; a signal routing path extending between the electrical contact structures on the one hand and at least some of the RX circuits or at least some of the TX circuits on the other hand; An electrical path leading to the PHY circuit and configured to meet at least one of the following conditions; The enable signal input to the die passes through at least some of the electrical paths to enable a portion of the PHY circuit; or The disable signal input to the die passes through at least some of the electrical paths to disable the corresponding part of the PHY circuit; and Wherein the packaging substrate includes a packaging signal routing path extending between a first die of the plurality of dies and a second die of the plurality of dies to provide device-to-device (D2D) communication therebetween. Signal interconnection. The IC device assembly of claim 20, wherein, for individual dies of the dies, the electrical paths include at least one fuse or register for enabling or disabling the corresponding part of the PHY circuit. At least one of the corresponding portions of the PHY circuit. The IC device assembly of claim 20, wherein, for individual dies of the dies, the electrical paths leading to the PHY circuit are configured to meet at least one of the following conditions: The enable signal input to the die passes through at least some of the electrical paths to enable 1/2 of the RX circuits and 1/2 of the TX circuits; or The disable signal input to the die passes through at least some of the electrical paths to disable the remaining 1/2 of the RX circuits and 1/2 of the TX circuits. The IC device assembly of claim 20, wherein, for individual dies of the dies, the electrical paths leading to the PHY circuit are configured to meet at least one of the following conditions: The enable signal input to the die passes through at least some of the electrical paths to enable 1/4 of the RX circuits and 1/4 of the TX circuits; or The disable signal input to the die passes through at least some of the electrical paths to disable the remaining 3/4 of the RX circuits and 3/4 of the TX circuits. A method of manufacturing a microelectronic device, comprising: Provide substrate; Provide a physical layer (PHY) circuit on the substrate, the physical layer (PHY) circuit including a plurality of receiving (RX) circuits and a plurality of transmitting (TX) circuits; providing electrical contact structures on the bottom surface of the device; providing signal routing paths extending between the electrical contact structures on the one hand and at least some of the RX circuits or at least some of the TX circuits on the other hand; and Provide an electrical path leading to the PHY circuit; At least one of the following: Provide an enable signal into the device through at least some of the electrical pathways to enable a portion of the PHY circuitry; or A disable signal is provided into the device through at least some of the electrical pathways to disable corresponding portions of the PHY circuit. The method of claim 24, wherein the electrical paths leading to the PHY circuit are configured to meet at least one of the following conditions: The enable signal input to the device passes through at least some of the electrical paths to enable 1/2 of the RX circuits and 1/2 of the TX circuits; or The disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1/2 of the RX circuits and 1/2 of the TX circuits.

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