CN115132720A - Integrated circuit product and chip arrangement thereof - Google Patents
Integrated circuit product and chip arrangement thereof Download PDFInfo
- Publication number
- CN115132720A CN115132720A CN202110969044.5A CN202110969044A CN115132720A CN 115132720 A CN115132720 A CN 115132720A CN 202110969044 A CN202110969044 A CN 202110969044A CN 115132720 A CN115132720 A CN 115132720A
- Authority
- CN
- China
- Prior art keywords
- chip
- logic
- integrated circuit
- circuit product
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention provides an integrated circuit product and a chip arrangement thereof, the integrated circuit product comprises: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip; and an eighth chip. The areas and the components of the first chip, the second chip, the third chip and the fourth chip are substantially the same; the areas and the components of the fifth chip, the sixth chip, the seventh chip and the eighth chip are substantially the same; the first chip, the second chip, the third chip and the fourth chip are respectively positioned on four edges of the integrated circuit product; and the fifth chip, the sixth chip, the seventh chip and the eighth chip are located in a central region of the integrated circuit product. The integrated circuit product of the invention can improve the heat dissipation efficiency of the integrated circuit product, reduce the difficulty of output and/or input routing, improve the competitiveness of the integrated circuit product and simplify the manufacturing process.
Description
Technical Field
The present invention relates to a package of an Integrated Circuit (IC), and more particularly, to an arrangement (floorplan arrangement) of chips (chips) and/or chiplets (chips) (hereinafter, collectively referred to as chips) of an IC package.
Background
Advanced packaging is a current trend for integrated circuits. However, poor chip layout may have the following disadvantages: wasted area (resulting in an oversized finished product and lack of competitiveness), poor heat dissipation of the chip (reducing chip performance), difficulty in routing output and/or input (increasing packaging difficulty), and/or undesirable relative positions of the chips (resulting in wasted chip pins). Therefore, a chip arrangement is needed to address at least one of the above problems.
Disclosure of Invention
In view of the above, how to reduce or eliminate the above-mentioned deficiency of chip arrangement in the related art is a problem to be solved.
An embodiment of an integrated circuit product is provided, comprising: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip; and an eighth chip. The areas and the components of the first chip, the second chip, the third chip and the fourth chip are substantially the same; the areas and the components of the fifth chip, the sixth chip, the seventh chip and the eighth chip are substantially the same; the first chip, the second chip, the third chip and the fourth chip are respectively positioned on four edges of the integrated circuit product; and the fifth chip, the sixth chip, the seventh chip and the eighth chip are located in a central region of the integrated circuit product.
The invention also provides an embodiment of an integrated circuit product, which has a first side, a second side, a third side and a fourth side. The integrated circuit product comprises: the first logic chip is positioned on the first edge; the second logic chip is positioned on the second edge; a third logic chip on the third side; the fourth logic chip is positioned on the fourth side; a first memory chip; a second memory chip; a third memory chip; and a fourth memory chip. The first logic chip, the second logic chip, the third logic chip and the fourth logic chip are arranged in point symmetry relative to the center of the integrated circuit product, and the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are arranged in point symmetry relative to the center.
One of the advantages of the above embodiments is that the heat dissipation efficiency of the integrated circuit product can be improved, the difficulty of routing the output and/or input lines can be reduced, and the competitiveness of the integrated circuit product can be improved.
Other advantages of the present invention will be described in more detail in conjunction with the following description and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.
Fig. 1 is a simplified chip layout diagram of an integrated circuit product according to an embodiment of the invention.
Fig. 2 illustrates a simplified side view of an integrated circuit product according to an embodiment of the present invention.
Fig. 3 shows a simplified side view of an integrated circuit product according to another embodiment of the invention.
Fig. 4 shows the relationship of the center region to the edge of the integrated circuit product of the present invention.
Fig. 5 shows the constituent elements of an integrated circuit product according to an embodiment of the invention.
Fig. 6 shows the constituent elements of an integrated circuit product according to another embodiment of the present invention.
Fig. 7 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the invention.
Fig. 8 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the present invention.
Fig. 9 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the invention.
Fig. 10 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the invention.
Fig. 11 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the invention.
Description of reference numerals:
100. 200, 300, 400, 500, 600 integrated circuit products
112. 212, 312 first logic chip
114. 214, 314 second logic chip
116. 216, 316 third logic chip
118. 218, 318 fourth logic chip
122. 222, 322, 422, 522, 622 first memory chip
124. 224, 324, 424, 524, 624 second memory chip
126. 226, 326, 426, 526, 626 third memory chip
128. 228, 328, 428, 528, 628 fourth memory chip
150 substrate
152 micro bump
154 bump
140 interposer
102. 202, 302 first side
104. 204, 304 second side
106. 206, 306 third side
108. 208, 308 fourth side
101. 201, 301, 401, 501, 601 center
160. 260, 360 central region
d1, d2, d3, d4 distances
132 first polygon
134 second polygon
136 third polygon
138 fourth polygon
232. 332 first other chip
234. 334 second other chip
236. 336 third other chip
238. 338 fourth and other chips
233. 203, 313, 303 first vertex
235. 205, 315, 305 second vertex
237. 207, 317, 307 third vertex
239. 209, 319, 309 fourth vertex
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar components or process flows.
Fig. 1 is a simplified chip layout diagram of an integrated circuit product according to an embodiment of the invention. The integrated circuit product 100 includes a first logic chip 112, a second logic chip 114, a third logic chip 116, a fourth logic chip 118, a first memory chip 122, a second memory chip 124, a third memory chip 126, and a fourth memory chip 128. Fig. 1 shows a top view of an integrated circuit product 100, and fig. 2 and 3 each show a simplified side view (cross-section along a-a' of fig. 1) of an integrated circuit product according to an embodiment of the invention. In the embodiment of fig. 2, the integrated circuit product 100 includes a substrate 150, and the logic chips and the memory chips shown in fig. 1 are disposed above the substrate 150. A plurality of micro bumps 152 are disposed between the substrate 150 and the logic chip and between the substrate 150 and the memory chip, and a plurality of bumps 154 are disposed under the substrate 150. In the embodiment of fig. 3, the integrated circuit product 100 includes an interposer (interposer)140, and the logic chips and the memory chips shown in fig. 1 are located above the interposer 140. A plurality of micro bumps 152 are formed between the interposer 140 and the substrate 150, and a plurality of bumps 154 are formed under the substrate 150. The first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 may be logic circuits with computing capability, such as a System on a chip (SoC). The logic chip may access the memory chip to perform a particular function, for example, by reading and executing program code or program instructions stored in the memory chip.
Returning to fig. 1. The integrated circuit product 100 has a first side 102, a second side 104, a third side 106, and a fourth side 108. The four sides of the integrated circuit product 100 may be the four sides of the substrate 150. The integrated circuit product 100 also has a center 101. The first logic chip 112 is disposed on the first side 102, that is, the first logic chip 112 is located on the first side 102, meaning that the first logic chip 112 is adjacent (adjacent) to the first side 102 (i.e., one side of the first logic chip 112 is substantially aligned with the first side 102, or the first logic chip 112 is substantially aligned with the substrate 150). Similarly, a second logic chip 114 is located on (equivalently arranged on, abutting) the second side 104, a third logic chip 116 is located on the third side 106, and a fourth logic chip 118 is located on the fourth side 108.
The first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are arranged in a ring shape at four edges of the integrated circuit product 100. The first logic chip 112 is adjacent to the fourth logic chip 118 and the second logic chip 114; the second logic chip 114 is adjacent to the first logic chip 112 and the third logic chip 116; the third logic chip 116 is adjacent to the second logic chip 114 and the fourth logic chip 118; and a fourth logic chip 118 is adjacent to the third logic chip 116 and the first logic chip 112.
The first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 do not adjoin any side of the integrated circuit product 100, but are commonly surrounded by the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118. More specifically, as shown in FIG. 4, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are located in a central region 160 of the integrated circuit product 100, and distances between the central region 160 and the first side 102, the second side 104, the third side 106, and the fourth side 108 are d1, d2, d3, and d4, respectively (d1, d2, d3, d4 are substantially equal). As shown in fig. 1, the central region 160 is completely surrounded by the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118, that is, four sides of the central region 160 are completely adjacent to the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118, respectively.
In some embodiments, the areas of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially the same, and the areas of the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are substantially the same.
In some embodiments, the components of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially identical, and the components of the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are substantially identical. The aforementioned components include, but are not limited to, transistors, resistors, capacitors, and/or inductors. In other embodiments, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 have the same number and type of components, and the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 have the same number and type of components.
The first logic chip 112 is adjacent to the first memory chip 122, the second memory chip 124 and the second logic chip 114, and the relative position between the first logic chip 112 and the first memory chip 122 is substantially equal to the relative position between the second logic chip 114 and the second memory chip 124. More specifically, please refer to fig. 1 and 5 simultaneously. The first logic chip 112 and the first memory chip 122 form a first polygon 132, the second logic chip 114 and the second memory chip 124 form a second polygon 134, and if the first polygon 132 is rotated 90 degrees clockwise with respect to the center 101 of the integrated circuit product 100, it will completely overlap the second polygon 134; that is, the first polygon 132 and the second polygon 134 are rotationally symmetric (the center of rotational symmetry is the center 101, and the rotation angle is 90 degrees). Similarly, the third logic chip 116 abuts the third memory chip 126, the fourth memory chip 128 and the fourth logic chip 118, and the relative position between the third logic chip 116 and the third memory chip 126 is substantially equal to the relative position between the fourth logic chip 118 and the fourth memory chip 128. In other words, in some embodiments, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 form a unit with the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128, respectively, in the integrated circuit product 100, that is, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can access or be coupled to the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128, respectively. One advantage of such an arrangement is that the outward (i.e., external to the integrated circuit product 100) pins of the first logic chip 112 (second logic chip 114, third logic chip 116, or fourth logic chip 118) may be arranged on the first side 102 (second side 104, third side 106, or fourth side 108), while the inward (e.g., pins in communication with the first memory chip 122, second memory chip 124, third memory chip 126, or fourth memory chip 128) pins may be arranged on the side adjacent to the memory chips. Thus, because the chip layout of the integrated circuit product 100 is simple (only the first polygon needs to be rotated by 90 degrees, 180 degrees, and 270 degrees), different areas of the integrated circuit product 100 can be manufactured by using the same mask, thereby greatly simplifying the manufacturing process and avoiding wasting pins.
In another aspect, the first logic chip 112 is adjacent to the first memory chip 122, the second memory chip 124, and the fourth logic chip 118, and the relative position between the first logic chip 112 and the second memory chip 124 is substantially equal to the relative position between the fourth logic chip 118 and the first memory chip 122. More specifically, please refer to fig. 1 and fig. 6 simultaneously. The fourth logic chip 118 and the first memory chip 122 form a third polygon 136, the first logic chip 112 and the second memory chip 124 form a fourth polygon 138, and the third polygon 136 completely overlaps the fourth polygon 138 if rotated 90 degrees clockwise with respect to the center 101 of the integrated circuit product 100; that is, the third polygon 136 and the fourth polygon 138 are rotationally symmetric (the center of rotational symmetry is the center 101, and the rotation angle is 90 degrees). Similarly, the third logic chip 116 is adjacent to the third memory chip 126, the fourth memory chip 128 and the second logic chip 114, and the relative position between the third logic chip 116 and the fourth memory chip 128 is substantially equal to the relative position between the second logic chip 114 and the third memory chip 126. In other words, in other embodiments, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 form a unit with the second memory chip 124, the third memory chip 126, the fourth memory chip 128, and the first memory chip 122, respectively, in the integrated circuit product 100, that is, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can be accessed or coupled to the second memory chip 124, the third memory chip 126, the fourth memory chip 128, and the first memory chip 122, respectively. The advantages of such an arrangement are similar or identical to those described in the preceding paragraph and are therefore not described in further detail.
If the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are rotated 180 degrees relative to the center 101, the first logic chip 112 and the third logic chip 116 substantially overlap, and the second logic chip 114 and the fourth logic chip 118 substantially overlap, in other words, the first logic chip 112 and the third logic chip 116 are point symmetric (point symmetry) (the center of symmetry is the center 101), and the second logic chip 114 and the fourth logic chip 118 are point symmetric. Similarly, first memory chip 122 and third memory chip 126 exhibit point symmetry with respect to center 101, and second memory chip 124 and fourth memory chip 128 exhibit point symmetry with respect to center 101. In other words, the overall arrangement of the first logic chip 112, the second logic chip 114, the third logic chip 116, the fourth logic chip 118, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 is point-symmetric with respect to the center 101.
In other embodiments, the integrated circuit product 100 is a square.
Fig. 7 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the present invention. Fig. 7 shows a top view of an integrated circuit product 200. Integrated circuit product 200 includes first logic chip 212, second logic chip 214, third logic chip 216, fourth logic chip 218, first memory chip 222, second memory chip 224, third memory chip 226, fourth memory chip 228, first other chip 232, second other chip 234, third other chip 236, and fourth other chip 238. Similar to the integrated circuit product 100, the integrated circuit product 200 includes a substrate and may or may not include an interposer (see fig. 2 and 3).
In some embodiments, first further chip 232, second further chip 234, third further chip 236, and fourth further chip 238 are input/output chips including input/output circuits by which first logic chip 212, second logic chip 214, third logic chip 216, and fourth logic chip 218 transmit or receive signals. In other embodiments, first further chip 232, second further chip 234, third further chip 236, and fourth further chip 238 are silicon chips that do not include any circuitry.
In some embodiments, the areas of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are substantially the same; the areas of the first memory chip 222, the second memory chip 224, the third memory chip 226, and the fourth memory chip 228 are substantially the same; and first further chip 232, second further chip 234, third further chip 236, and fourth further chip 238 have substantially the same area.
In some embodiments, the components of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are substantially the same, the components of the first memory chip 222, the second memory chip 224, the third memory chip 226, and the fourth memory chip 228 are substantially the same, and the components of the first other chip 232, the second other chip 234, the third other chip 236, and the fourth other chip 238 are substantially the same. The aforementioned components include, but are not limited to, transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are the same in type and number, the components of the first memory chip 222, the second memory chip 224, the third memory chip 226, and the fourth memory chip 228 are the same in type and number, and the components of the first other chip 232, the second other chip 234, the third other chip 236, and the fourth other chip 238 are the same in type and number.
Similar to the embodiment of fig. 1, the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 collectively surround a central region 260 of the integrated circuit product 200. More specifically, four sides of the central region 260 completely adjoin the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218, respectively, that is, the central region 260 of the integrated circuit product 200 is completely surrounded by the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218.
First further chip 232, second further chip 234, third further chip 236, and fourth further chip 238 are located outside of central region 260 of integrated circuit product 200. More specifically, the first additional chip 232, the second additional chip 234, the third additional chip 236, and the fourth additional chip 238 are respectively located at four corners of the integrated circuit product 200. That is, first vertex 233 of first other chip 232 is aligned with first vertex 203 of integrated circuit product 200, second vertex 235 of second other chip 234 is aligned with second vertex 205 of integrated circuit product 200, third vertex 237 of third other chip 236 is aligned with third vertex 207 of integrated circuit product 200, and fourth vertex 239 of fourth other chip 238 is aligned with fourth vertex 209 of integrated circuit product 200.
If the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 are rotated 180 degrees with respect to the center 201, the first logic chip 212 and the third logic chip 216 substantially overlap, and the second logic chip 214 and the fourth logic chip 218 substantially overlap, in other words, the first logic chip 212 and the third logic chip 216 are point-symmetric (the center of symmetry is the center 201), and the second logic chip 214 and the fourth logic chip 218 are point-symmetric. Similarly, the first memory chip 222 and the third memory chip 226 exhibit point symmetry with respect to the center 201, and the second memory chip 224 and the fourth memory chip 228 exhibit point symmetry with respect to the center 201. Similarly, first further chip 232 and third further chip 236 exhibit point symmetry with respect to center 201, and second further chip 234 and fourth further chip 238 exhibit point symmetry with respect to center 201. In other words, the overall arrangement of the first logic chip 212, the second logic chip 214, the third logic chip 216, the fourth logic chip 218, the first memory chip 222, the second memory chip 224, the third memory chip 226, the fourth memory chip 228, the first other chip 232, the second other chip 234, the third other chip 236, and the fourth other chip 238 is point-symmetric with respect to the center 201.
In other embodiments, the integrated circuit product 200 is a square.
The first logic chip 212 is adjacent to the first memory chip 222, the second memory chip 224, and the first other chip 232, and a relative position between the first logic chip 212 and the first memory chip 222 is substantially equal to a relative position between the second logic chip 214 and the second memory chip 224. More specifically, please refer to fig. 5 and fig. 7 simultaneously. The first logic chip 212, the first memory chip 222, and the first further chip 232 form a first polygon 132, the second logic chip 214, the second memory chip 224, and the second further chip 234 form a second polygon 134, and if the first polygon 132 is rotated 90 degrees clockwise with respect to the center 201 of the integrated circuit product 200, it completely overlaps the second polygon 134. Similarly, the third logic chip 216 is adjacent to the third memory chip 226, the fourth memory chip 228, and the third other chip 236, and the relative position between the third logic chip 216 and the third memory chip 226 is substantially equal to the relative position between the fourth logic chip 218 and the fourth memory chip 228. In other words, in some embodiments, the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 may access or be coupled to the first memory chip 222, the second memory chip 224, the third memory chip 226, and the fourth memory chip 228, respectively.
In other words, the first logic chip 212 is adjacent to the first memory chip 222, the second memory chip 224, the first other chip 232 and the fourth other chip 238, and the relative position between the first logic chip 212 and the second memory chip 224 is substantially equal to the relative position between the fourth logic chip 218 and the first memory chip 222. More specifically, please refer to fig. 6 and fig. 7 simultaneously. The fourth logic chip 218, the first memory chip 222, and the fourth other chip 238 form the third polygon 136, the first logic chip 212, the second memory chip 224, and the first other chip 232 form the fourth polygon 138, and if the third polygon 136 is rotated 90 degrees clockwise with respect to the center 201 of the integrated circuit product 200, it completely overlaps the fourth polygon 138. Similarly, the third logic chip 216 is adjacent to the third memory chip 226, the fourth memory chip 228, the second additional chip 234, and the third additional chip 236, and the relative position between the third logic chip 216 and the fourth memory chip 228 is substantially equal to the relative position between the second logic chip 214 and the third memory chip 226. In other words, in other embodiments, the first logic chip 212, the second logic chip 214, the third logic chip 216, and the fourth logic chip 218 may access or be coupled to the second memory chip 224, the third memory chip 226, the fourth memory chip 228, and the first memory chip 222, respectively.
Fig. 8 is a simplified chip layout diagram of an integrated circuit product according to another embodiment of the invention. Fig. 8 illustrates a top view of an integrated circuit product 300. Integrated circuit product 300 includes a first logic chip 312, a second logic chip 314, a third logic chip 316, a fourth logic chip 318, a first memory chip 322, a second memory chip 324, a third memory chip 326, a fourth memory chip 328, a first other chip 332, a second other chip 334, a third other chip 336, and a fourth other chip 338. Similar to the integrated circuit product 100, the integrated circuit product 300 includes a substrate and may or may not include an interposer (see fig. 2 and 3).
In some embodiments, first other chip 332, second other chip 334, third other chip 336, and fourth other chip 338 are input/output chips, including input/output circuits. In other embodiments, first further chip 332, second further chip 334, third further chip 336, and fourth further chip 338 are silicon chips that do not include any circuitry.
In some embodiments, the areas of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are substantially the same; the areas of first memory chip 322, second memory chip 324, third memory chip 326, and fourth memory chip 328 are substantially the same; and first other chip 332, second other chip 334, third other chip 336, and fourth other chip 338 are substantially the same in area.
In some embodiments, the components of first logic chip 312, second logic chip 314, third logic chip 316, and fourth logic chip 318 are substantially the same, the components of first memory chip 322, second memory chip 324, third memory chip 326, and fourth memory chip 328 are substantially the same, and the components of first other chip 332, second other chip 334, third other chip 336, and fourth other chip 338 are substantially the same. The aforementioned components include, but are not limited to, transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are the same in type and number, the components of the first memory chip 322, the second memory chip 324, the third memory chip 326, and the fourth memory chip 328 are the same in type and number, and the components of the first other chip 332, the second other chip 334, the third other chip 336, and the fourth other chip 338 are the same in type and number.
In the embodiment of fig. 8, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 collectively surround the central region 360 of the integrated circuit product 300. More specifically, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 do not completely surround the central area 360 of the integrated circuit product 300 because four sides of the central area 360 of the integrated circuit product 300 are not completely contiguous with the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318.
First other chip 332, second other chip 334, third other chip 336, and fourth other chip 338 are located outside of central region 360 of integrated circuit product 300. First additional chip 332, second additional chip 334, third additional chip 336, and fourth additional chip 338 each have only one side adjacent to one side of integrated circuit product 300. More specifically, one side of the first other chip 332, the second other chip 334, the third other chip 336 and the fourth other chip 338 is adjacent to the first side 302, the second side 304, the third side 306 and the fourth side 308, respectively, while the other three sides of the first other chip 332, the second other chip 334, the third other chip 336 and the fourth other chip 338 are not adjacent to the sides of the integrated circuit product 300.
The first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are respectively located at four corners of the integrated circuit product 300. That is, first vertex 313 of first logic chip 312 is aligned with first vertex 303 of integrated circuit product 300, second vertex 315 of second logic chip 314 is aligned with second vertex 305 of integrated circuit product 300, third vertex 317 of third logic chip 316 is aligned with third vertex 307 of integrated circuit product 300, and fourth vertex 319 of fourth logic chip 318 is aligned with fourth vertex 309 of integrated circuit product 300.
If the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are rotated 180 degrees with respect to the center 301, the first logic chip 312 and the third logic chip 316 substantially overlap, and the second logic chip 314 and the fourth logic chip 318 substantially overlap, in other words, the first logic chip 312 and the third logic chip 316 are point-symmetric (the center of symmetry is the center 301), and the second logic chip 314 and the fourth logic chip 318 are point-symmetric. Similarly, first memory chip 322 and third memory chip 326 exhibit point symmetry with respect to center 301, and second memory chip 324 and fourth memory chip 328 exhibit point symmetry with respect to center 301. Similarly, the first other chip 332 and the third other chip 336 exhibit point symmetry with respect to the center 301, and the second other chip 334 and the fourth other chip 338 exhibit point symmetry with respect to the center 301. In other words, the overall arrangement of the first logic chip 312, the second logic chip 314, the third logic chip 316, the fourth logic chip 318, the first memory chip 322, the second memory chip 324, the third memory chip 326, the fourth memory chip 328, the first other chip 332, the second other chip 334, the third other chip 336, and the fourth other chip 338 is point-symmetric with respect to the center 301 of the integrated circuit product 300.
In other embodiments, the integrated circuit product 300 is a square.
The first logic chip 312 is adjacent to the first memory chip 322, the second memory chip 324, and the first other chip 332, and the relative position between the first logic chip 312 and the first memory chip 322 is substantially equal to the relative position between the second logic chip 314 and the second memory chip 324. More specifically, please refer to fig. 5 and 8. The first logic chip 312, the first memory chip 322, and the first other chip 332 form a first polygon 132, the second logic chip 314, the second memory chip 324, and the second other chip 334 form a second polygon 134, and if the first polygon 132 is rotated 90 degrees clockwise with respect to the center 301 of the integrated circuit product 300, it completely overlaps the second polygon 134. Similarly, third logic chip 316 abuts third memory chip 326, fourth memory chip 328, and third other chip 336, and the relative position between third logic chip 316 and third memory chip 326 is substantially equal to the relative position between fourth logic chip 318 and fourth memory chip 328. In other words, in some embodiments, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 can access or be coupled to the first memory chip 322, the second memory chip 324, the third memory chip 326, and the fourth memory chip 328, respectively.
In another aspect, the first other chip 332 is adjacent to the first logic chip 312, the fourth logic chip 318, and the first memory chip 322, and the relative position between the first logic chip 312 and the second memory chip 324 is substantially equal to the relative position between the fourth logic chip 318 and the first memory chip 322. More specifically, please refer to fig. 6 and 8. The fourth logic chip 318, the first memory chip 322, and the fourth other chip 338 form the third polygon 136, the first logic chip 312, the second memory chip 324, and the first other chip 332 form the fourth polygon 138, and if the third polygon 136 is rotated 90 degrees clockwise with respect to the center 301 of the integrated circuit product 300, it completely overlaps the fourth polygon 138. Similarly, a third other chip 336 abuts second logic chip 314, third logic chip 316, and third memory chip 326, and the relative position between third logic chip 316 and fourth memory chip 328 is substantially equal to the relative position between second logic chip 314 and third memory chip 326. In other words, in other embodiments, the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 can access or be coupled to the second memory chip 324, the third memory chip 326, the fourth memory chip 328, and the first memory chip 322, respectively.
The first memory chip 122, the second memory chip 124, the third memory chip 126, the fourth memory chip 128, the first memory chip 222, the second memory chip 224, the third memory chip 226, the fourth memory chip 228, the first memory chip 322, the second memory chip 324, the third memory chip 326, and the fourth memory chip 328 in fig. 1, 7, and 8 are third-generation high bandwidth memory (HBM 3), and are square in shape. However, the memory chip described above may also be a second generation high bandwidth memory (HBM 2) as shown in fig. 9 to 11. First memory chip 422, second memory chip 424, third memory chip 426, fourth memory chip 428 of integrated circuit product 400, first memory chip 522, second memory chip 524, third memory chip 526, fourth memory chip 528 of integrated circuit product 500, and first memory chip 622, second memory chip 624, third memory chip 626, fourth memory chip 628 of integrated circuit product 600 are second generation high bandwidth memories. Because the second generation high bandwidth memory is not square, center 401 of integrated circuit product 400, center 501 of integrated circuit product 500, and center 601 of integrated circuit product 600 are not covered by memory chips. The descriptions of fig. 9, 10, and 11 may correspond to the descriptions of fig. 1, 7, and 8, respectively, and thus are not repeated.
In summary, since the logic circuit generally generates more heat than the memory chip, the heat dissipation efficiency of the integrated circuit product can be improved by arranging the logic chip around the integrated circuit product. In addition, since logic chips are usually required to receive signals and transmit signals, arranging logic chips around an integrated circuit product can reduce the difficulty of routing output and/or input signals. In addition, the chip arrangement provided by the invention can enable the chips to be tightly arranged in the integrated circuit product, thereby fully utilizing the area of the substrate to improve the competitiveness of the integrated circuit product. In addition, the chips on the integrated circuit product are arranged in a point-symmetric mode, so that pin waste can be avoided, the same photomask can be used for manufacturing different parts of the integrated circuit product, and the complexity of the photomask can be simplified.
On the other hand, the chips on the integrated circuit product are arranged in the point symmetry manner, so that a semiconductor manufacturer can manufacture the integrated circuit product with an area close to 4 times that of the integrated circuit product by using the same set of photomask, thereby greatly reducing the manufacturing cost of the integrated circuit product.
It should be noted that the chip layout on the integrated circuit product is only an exemplary embodiment and is not limited to the actual implementation of the invention. For example, in some embodiments, the first to fourth memory chips may be arranged in a central region of the integrated circuit product in a manner of being line-symmetrical with respect to a central axis of the integrated circuit product (passing through the center and being perpendicular to either side), and the first to fourth logic chips may be arranged in a periphery of the central region of the integrated circuit product in a manner of being line-symmetrical with respect to the central axis of the integrated circuit product.
Certain terms are used throughout the description and following claims to refer to particular components, and those skilled in the art may refer to the same components by different names. In the present specification and claims, the difference in name is not used as a means for distinguishing between components, but a difference in function of a component is used as a reference for distinguishing between components. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if the first component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection such as wireless transmission or optical transmission, or indirectly connected to the second component through other components or connection means.
The description of "and/or" as used in this specification is inclusive of any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The dimensions and relative sizes of some of the elements in the figures may be exaggerated or the shapes of some of the elements may be simplified to help to improve clarity of presentation of the embodiments. Therefore, unless otherwise specified by the applicant, the shapes, sizes, relative positions and the like of the components in the drawings are merely for convenience of description, and should not be used to limit the scope of the present invention. Furthermore, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
For convenience in explanation, the description may use some statements related to relative positions in space to describe the function of a certain element or the relative spatial relationship of that element to other elements in the drawings. For example, "on …," "above …," "below …," "below …," "above …," "below …," "up," "down," and the like. It will be understood by those skilled in the art that these descriptions relating to the relative positions in space include not only the orientation of the components illustrated in the drawings, but also the various orientations of the components as they are used, operated, or assembled. For example, if the figure is turned upside down, the element originally described as "at …" will become "at …". Therefore, the expression "under …" used in the specification should be interpreted to include two different orientations "under …" and "under …". Similarly, the term "upwardly" as used herein is to be interpreted to encompass both the different directional relationships of "upwardly" and "downwardly".
In the specification and claims, the description that a first element is located on, above, connected to, coupled to, or connected to a second element means that the first element can be directly on, connected, coupled to, or coupled to the second element, and that other elements may be present between the first element and the second element. In contrast, if a first element is described as being directly on, directly connected to, directly engaged with, directly coupled to, or directly connected to a second element, that means that there are no other elements present between the first and second elements.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should be included in the scope of the present invention.
Claims (22)
1. An integrated circuit product (100; 200; 300) comprising:
a first chip (112; 212; 312);
a second chip (114; 214; 314);
a third chip (116; 216; 316);
a fourth chip (118; 218; 318);
a fifth chip (122; 222; 322);
a sixth chip (124; 224; 324);
a seventh chip (126; 226; 326); and
an eighth chip (128; 228; 328);
wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) have substantially the same area and component;
the areas and the components of the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328) are substantially the same;
the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are located at four sides of the integrated circuit product (100; 200; 300), respectively; and is
The fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328) are located in a central region (160; 260; 360) of the integrated circuit product (100; 200; 300).
2. The integrated circuit product (100; 200; 300) of claim 1, wherein any one of the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) is coupled to one of the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328).
3. The integrated circuit product (100; 200; 300) of claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are arranged in point symmetry with respect to a center (101; 201; 301) of the integrated circuit product (100; 200; 300), and the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328) are arranged in point symmetry with respect to the center (101; 201; 301).
4. The integrated circuit product (100; 200; 300) of claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are arranged in a ring.
5. The integrated circuit product (100) of claim 2, wherein the first chip (112) abuts the fourth chip (118) and the second chip (114), the second chip (114) abuts the first chip (112) and the third chip (116), the third chip (116) abuts the second chip (114) and the fourth chip (118), and the fourth chip (118) abuts the third chip (116) and the first chip (112).
6. The integrated circuit product (100; 200; 300) of claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) are logic chips, and the fifth chip (122; 222; 322), the sixth chip (124; 224; 324), the seventh chip (126; 226; 326), and the eighth chip (128; 228; 328) are memory chips.
7. The integrated circuit product (100) of claim 2, wherein the first chip (112) and the fifth chip (122) form a first polygon (132), the second chip (114) and the sixth chip (124) form a second polygon (134), and the first polygon (132) completely overlaps the second polygon (134) if rotated ninety degrees relative to the center (101) of the integrated circuit product (100).
8. The integrated circuit product (100) of claim 2, wherein the fourth chip (118) and the fifth chip (122) form a third polygon (136), the first chip (112) and the sixth chip (124) form a fourth polygon (138), and the third polygon (136) completely overlaps the fourth polygon (138) if rotated ninety degrees relative to the center (101) of the integrated circuit product (100).
9. The integrated circuit product (100; 200; 300) of claim 2, wherein the first chip (112; 212; 312), the second chip (114; 214; 314), the third chip (116; 216; 316), and the fourth chip (118; 218; 318) collectively surround the central region (160; 260; 360).
10. The integrated circuit product (100; 200) of claim 9, wherein the first chip (112; 212), the second chip (114; 214), the third chip (116; 216), and the fourth chip (118; 218) completely surround the central region (160; 260).
11. The integrated circuit product (200; 300) of claim 2, further comprising:
a ninth chip (232; 332);
a tenth chip (234; 334);
an eleventh chip (236; 336); and
a twelfth chip (238; 338);
wherein the ninth chip (232; 332), the tenth chip (234; 334), the eleventh chip (236; 336), and the twelfth chip (238; 338) are located outside the central region (260; 360).
12. The integrated circuit product (200) of claim 11, wherein the ninth chip (232), the tenth chip (234), the eleventh chip (236), and the twelfth chip (238) are located at four corners of the integrated circuit product (200).
13. The integrated circuit product (300) of claim 11, wherein the first chip (312), the second chip (314), the third chip (316), and the fourth chip (318) are located at four corners of the integrated circuit product (300).
14. The integrated circuit product (200; 300) of claim 11, wherein the first chip (212; 312), the fifth chip (222; 322), and the ninth chip (232; 332) form a first polygon (132), the second chip (214; 314), the sixth chip (224; 324), and the tenth chip (234; 334) form a second polygon (134), and the first polygon (132) completely overlaps the second polygon (134) if rotated ninety degrees relative to a center (201; 301) of the integrated circuit product (200; 300).
15. The integrated circuit product (200; 300) of claim 11, wherein the fourth chip (218; 318), the fifth chip (222; 322), and the twelfth chip (238; 338) form a third polygon (136), the first chip (212; 312), the sixth chip (224; 324), and the ninth chip (232; 332) form a fourth polygon (138), and the third polygon (136) completely overlaps the fourth polygon (138) if rotated ninety degrees relative to the center (201; 301) of the integrated circuit product (200; 300).
16. An integrated circuit product (100; 200; 300) having a first side (102; 202; 302), a second side (104; 204; 304), a third side (106; 206; 306), and a fourth side (108; 208; 308), comprising:
a first logic chip (112; 212; 312) located on the first side (102; 202; 302);
a second logic chip (114; 214; 314) located at the second edge (104; 204; 304);
a third logic chip (116; 216; 316) located on the third side (106; 206; 306);
a fourth logic chip (118; 218; 318) located on the fourth side (108; 208; 308);
a first memory chip (122; 222; 322);
a second memory chip (124; 224; 324);
a third memory chip (126; 226; 326); and
a fourth memory chip (128; 228; 328);
the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) are arranged in point symmetry with respect to a center (101; 201; 301) of the integrated circuit product (100; 200; 300), and the first memory chip (122; 222; 322), the second memory chip (124; 224; 324), the third memory chip (126; 226; 326), and the fourth memory chip (128; 228; 328) are arranged in point symmetry with respect to the center (101; 201; 301).
17. The integrated circuit product (100; 200; 300) of claim 16, wherein any one of the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) is coupled to one of the first memory chip (122; 222; 322), the second memory chip (124; 224; 324), the third memory chip (126; 226; 326), and the fourth memory chip (128; 228; 328).
18. The integrated circuit product (100; 200; 300) of claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) are substantially the same area.
19. The integrated circuit product (100; 200; 300) of claim 17, wherein the areas of the first memory chip (122; 222; 322), the second memory chip (124; 224; 324), the third memory chip (126; 226; 326), and the fourth memory chip (128; 228; 328) are substantially the same.
20. The integrated circuit product (100; 200; 300) of claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) are arranged in a ring.
21. The integrated circuit product (100; 200; 300) of claim 17, wherein the first logic chip (112; 212; 312), the second logic chip (114; 214; 314), the third logic chip (116; 216; 316), and the fourth logic chip (118; 218; 318) collectively surround a central region (160; 260; 360) of the integrated circuit product (100; 200; 300).
22. The integrated circuit product (100; 200) of claim 21, wherein the first logic chip (112; 212), the second logic chip (114; 214), the third logic chip (116; 216), and the fourth logic chip (118; 218) completely surround the central region (160; 260).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/572,382 US11973059B2 (en) | 2021-03-26 | 2022-01-10 | Integrated circuit product and chip floorplan arrangement thereof |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163166703P | 2021-03-26 | 2021-03-26 | |
| US63/166,703 | 2021-03-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115132720A true CN115132720A (en) | 2022-09-30 |
Family
ID=83375397
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110969044.5A Pending CN115132720A (en) | 2021-03-26 | 2021-08-23 | Integrated circuit product and chip arrangement thereof |
| CN202110967790.0A Pending CN115132719A (en) | 2021-03-26 | 2021-08-23 | Integrated circuit product and chip arrangement thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110967790.0A Pending CN115132719A (en) | 2021-03-26 | 2021-08-23 | Integrated circuit product and chip arrangement thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN115132720A (en) |
| TW (3) | TWI776648B (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7353077B2 (en) * | 2005-07-29 | 2008-04-01 | Taiwan Semiconductor Manufacturing Company | Methods for optimizing die placement |
| TWI409917B (en) * | 2009-01-23 | 2013-09-21 | Himax Tech Ltd | Chip layout for reducing warpage and method thereof |
| US8946868B2 (en) * | 2009-09-30 | 2015-02-03 | Silicon Laboratories Inc. | Multiple die layout for facilitating the combining of an individual die into a single die |
| US8901747B2 (en) * | 2010-07-29 | 2014-12-02 | Mosys, Inc. | Semiconductor chip layout |
| TWI420614B (en) * | 2011-05-10 | 2013-12-21 | Po Cheng Hsueh | A die detection method for 3d die stacking |
| US9159716B2 (en) * | 2013-08-30 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked chip layout having overlapped active circuit blocks |
| US9349710B2 (en) * | 2013-10-07 | 2016-05-24 | Xintec Inc. | Chip package and method for forming the same |
| TWI777225B (en) * | 2019-08-29 | 2022-09-11 | 台灣積體電路製造股份有限公司 | Integrated chip and method of forming the same |
-
2021
- 2021-08-23 TW TW110131167A patent/TWI776648B/en active
- 2021-08-23 CN CN202110969044.5A patent/CN115132720A/en active Pending
- 2021-08-23 CN CN202110967790.0A patent/CN115132719A/en active Pending
- 2021-08-23 TW TW111123117A patent/TWI790977B/en active
- 2021-08-23 TW TW110131168A patent/TWI780870B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI776648B (en) | 2022-09-01 |
| TWI790977B (en) | 2023-01-21 |
| TWI780870B (en) | 2022-10-11 |
| TW202238434A (en) | 2022-10-01 |
| CN115132719A (en) | 2022-09-30 |
| TW202238908A (en) | 2022-10-01 |
| TW202249232A (en) | 2022-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4078332B2 (en) | Integrated circuit interconnection method | |
| JP2008515202A (en) | Face-to-face bonded I / O circuit die and functional logic circuit system | |
| US7434189B2 (en) | I/O driver power distribution method for reducing silicon area | |
| US20060175637A1 (en) | Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh | |
| CN115132720A (en) | Integrated circuit product and chip arrangement thereof | |
| KR20020023147A (en) | Multi-chip module | |
| US11973059B2 (en) | Integrated circuit product and chip floorplan arrangement thereof | |
| JP5548342B2 (en) | Semiconductor device | |
| US11830850B2 (en) | Integrated circuit product and chip floorplan arrangement thereof | |
| US20060261847A1 (en) | Semiconductor integrated circuit device | |
| US7768138B2 (en) | Semiconductor device | |
| CN115954337A (en) | Mirror image chip on common substrate | |
| US20060284310A1 (en) | Offset via on pad | |
| US20110233772A1 (en) | Semiconductor element and semiconductor device using the same | |
| US5945696A (en) | Silicon chip having mixed input/output slot structure | |
| JP2011176011A (en) | Semiconductor integrated circuit device | |
| US7298036B2 (en) | Scaling of functional assignments in packages | |
| US20020130424A1 (en) | Semiconductor integrated circuit | |
| KR100359591B1 (en) | Semiconductor device | |
| KR20070053660A (en) | Single row bond pad arrangement of an integrated circuit chip | |
| CN111508942B (en) | Signal processing circuit capable of avoiding performance degradation of collocated memory chip | |
| JP5275308B2 (en) | Semiconductor integrated circuit and I / O block arrangement method | |
| US8912656B2 (en) | Integrated circuit package and physical layer interface arrangement | |
| JP2007335511A (en) | Design method for semiconductor integrated circuit device, semiconductor integrated circuit device and manufacturing method therefor | |
| JP4859470B2 (en) | Semiconductor device design method and apparatus, and program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |