JP4859470B2 - Semiconductor device design method and apparatus, and program - Google Patents

Description

  The present invention relates to a semiconductor device design method and apparatus, and a program, and more particularly, a structured ASIC (Application Specific Integrated Circuit) including a hard macroblock (functional block) such as an analog macroblock, a digital macroblock, and a high-speed interface macroblock. The present invention relates to a method and apparatus for designing a semiconductor device composed of the semiconductor integrated circuit device called a single chip module device or the like, and a program for causing a computer to design such a semiconductor device. The present invention also relates to a computer-readable storage medium storing a program.

  In semiconductor devices used for core communication devices, high-end computers, and the like, demands for higher speed and higher performance are increasing year by year. In order to meet these demands, it is necessary to increase the number of pins of a semiconductor device and realize excellent electrical characteristics, and one solution is FCBGA (Flip Chip Ball Grid Array).

  As a method for electrically connecting a semiconductor chip (bare chip) and a semiconductor substrate (package substrate), a wire bonding method is generally used in which the circuit surface of the chip is faced up and wires and terminals are wired using fine gold wires. However, the FCBGA employs a flip chip system in which electrical connection is made by connecting a chip to a semiconductor substrate using solder or gold terminals (bumps) with the circuit surface of the chip facing down. For this reason, FCBGA is electrically superior because the length of the wiring is shorter than that of the wire bonding method, and can cope with higher speed and higher density. Also, since the pins can be two-dimensionally arranged just below the chip, it is easy to increase the number of pins to several thousand pins. Furthermore, according to the FCBGA, heat can be released from the back surface of the chip due to the structure of the chip, so that heat dissipation is excellent.

  However, on the other hand, there is a problem that it is difficult to manufacture an FCBGA semiconductor device. By increasing the number of pins, the distance between the pins becomes very narrow. In FCBGA, when connecting the chip and the semiconductor substrate, all the pins are connected to each other as to how to connect without affecting the adjacent pins. It is important to make an electrical connection without affecting the pins.

  Therefore, in the conventional FCBGA package structure and capacitor arrangement method, there is a method in which a decoupling capacitor is arranged in the vicinity of the power supply pad of the chip without changing the BGA arrangement of the FCBGA package. In addition, the capacitor mounting substrate, the chip and the package substrate are fixed, the side surface of the chip and the capacitor mounting substrate and the upper surface of the capacitor are covered with a mold resin, and the external terminal for solder terminals arranged on the back side of the package substrate. A semiconductor device having a structure including a BGA is also proposed in Patent Document 1, for example.

  Since the conventional chip has a small number of signal input / output (I / O) and the external dimensions of the semiconductor substrate are relatively small, the pin assignment and net assignment of the semiconductor substrate are enclosed in a diagonal direction from one of the four sides of the chip. When fanning out to a specified area, a pin assignment or net assignment that does not intersect with a ratness that connects the start point and the end point with a straight line, for example, as proposed in Patent Document 2, a net assignment is made to a W shape. There was a method of wiring.

  Moreover, the maze method, the line segment search method, the line segment search method, etc. were used for the conventional automatic wiring method.

  In recent chips, the gate dimensions of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) have been miniaturized, the integration scale has been increased, and the density and miniaturization of wiring have also been advanced. The number of signal I / Os is increasing in a high-end ASIC of 5 million gate scale SOC (System On Chip) of 90 nm CMOS technology used for a mainframe class that can be applied to a core business. The bump pitch of C4 (Controlled Collapsed Chip Connection) bumps used as bonding bumps for high-end ASICs, etc. is up to 176 μm, and there is a tendency for narrow bump pitches.

  For this reason, semiconductor substrates tend to have high-density wiring and ultra-high pin count, and the external dimensions have been enlarged.

  In addition, in the case of a chip equipped with an ultra-high-speed I / O interface circuit, ultra-high-speed inter-chip synchronous transmission at 800 MHz or 1.33 GHz is adopted between chips on the system board, and it operates with an ultra-high-speed clock on the order of GHz. There are also things.

Patent Document 3 proposes a semiconductor device configured to guarantee a wide operating temperature range even when a plurality of hard macro cores coexist. Patent Document 4 proposes a semiconductor device configured to efficiently dissipate heat from a high-frequency semiconductor element.
JP 2004-214509 A JP 2005-515612 A JP 2000-269417 A JP 2000-31374 A

  In the conventional FCBGA design method, the design is performed with a planar two-dimensional element, and the design is performed while considering the three-dimensional thinking in the designer's own head. Moreover, since the wiring design was performed manually, a long design time was required. In addition, when designing with a two-dimensional planar element, if a three-dimensional element such as a via is added, it is difficult for a beginner to design, and it is difficult for a beginner to design.

  The ultra-high-speed clock requires a wiring design such as differential wiring other than single-ended wiring, and correction after wiring increases depending on how the power / ground (GND) pin is assigned. In this case, since the wiring is often redesigned manually, a long design time is required. In addition, it is difficult to transfer a signal operating with an ultra-high-speed clock on the order of GHz on a semiconductor substrate with little loss and timing.

  In addition, if one wiring is manually designed as the number of chip I / Os increases, it is difficult to estimate the number of wirings and substrate layers in a short time. Further, since the wiring design is performed manually, the design work time increases in proportion to the number of signal I / Os. Furthermore, as the number of signal I / Os on the chip increases, the distance between bumps (= vias) becomes very narrow by increasing the number of pins and decreasing the bump pitch, so when connecting the chip and the semiconductor substrate It was difficult to connect adjacent bumps without affecting them, and to design high-density wiring between vias with narrow bump pitch and vias with pad pitch. Further, in order to convert the pitch of the bump on the chip side to the pitch of the BGA on the semiconductor substrate, it is necessary to design the high-density wiring in the semiconductor substrate at high speed and accurately according to the design rule.

  On the other hand, the decoupling capacitor needs to be arranged in the vicinity of the hard macro block of the chip, and the BGA pin assignment of the power supply and the GND pin needs to correspond according to the design change. However, with the conventional design method, it has been difficult to design high-density wiring at high speed so as to satisfy physical and electrical constraints on the wiring due to the structure of the semiconductor device.

  As described above, in the conventional design method, there is a problem that it is difficult to efficiently design a semiconductor device having stable performance even at a configuration in which many pins are provided.

  Therefore, the present invention efficiently designs a semiconductor device having a structure for supplying stable power to a semiconductor chip having an ultra-multi-pin high-density multi-layer wiring board structure and a multi-function, multi-function macroblock. An object of the present invention is to provide a method and apparatus for designing a semiconductor device, and a program.

  The above-mentioned problem is that a semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent to each other in the Z direction are insulated via an insulating layer, and a plurality of pads and lands. A semiconductor device design method including a semiconductor chip provided on an XY plane on a substrate, wherein the semiconductor substrate is obtained by aligning the center coordinate of the semiconductor chip on the XY plane with the center coordinate of the semiconductor substrate on the XY plane. An overlaying step of overlaying the semiconductor chip on the substrate; and vias connected to the wiring layer of the power supply layer / ground layer / wiring layer from the starting point of the wiring of the semiconductor chip in the Z direction; A wiring layer number setting step for setting the number of wiring layers of the power supply layer / ground layer / wiring layer, and a grid in the XY direction and the XZ direction based on the start point and end point of the wiring in the two-dimensional coordinate system of the XY plane and the XZ plane A power supply layer / ground layer specified by arranging vias in the XZ direction based on the via matrix, obtaining a via matrix having XYZ coordinates in a three-dimensional orthogonal coordinate system in which vias at intersections of the grid lines are arranged A connection step of connecting to the wiring layer. This can be achieved by a method for designing a semiconductor device.

  The above object can also be achieved by a program characterized by including a procedure for causing a computer to execute each step of the design method of the semiconductor device.

  The above object can also be achieved by a computer-readable storage medium characterized by storing the above program.

  The above-mentioned problem is that a semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent to each other in the Z direction are insulated via an insulating layer, and a plurality of pads and lands. An apparatus for designing a semiconductor device comprising a semiconductor chip provided on an XY plane on a substrate, wherein the center coordinates of the semiconductor chip on the XY plane are matched with the center coordinates on the XY plane of the semiconductor substrate. An overlaying means for superimposing the semiconductor chip on the substrate; and vias connected to the wiring among the power supply layer / ground layer / wiring layer from the starting point of the wiring of the semiconductor chip in the Z direction; Wiring layer number setting means for setting the number of power layers / ground layers / wiring layers, and grid lines in the XY and XZ directions with the wiring start and end points as the base points in the two-dimensional coordinate system of the XY and XZ planes Draw A via matrix having XYZ coordinates in a three-dimensional orthogonal coordinate system in which vias are arranged at the intersections of the grid lines is obtained, and vias are arranged in the XZ direction based on the via matrix to the specified power supply layer / ground layer / wiring layer. This can also be achieved by a method for designing a semiconductor device, characterized by comprising a connection means for connection.

  According to the present invention, it is possible to realize a semiconductor device design method, apparatus, and program capable of relatively easily designing a semiconductor device having stable performance even in a configuration in which a large number of pins are provided. .

  Embodiments of a semiconductor device design method and apparatus and a program according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a first comparative example of a semiconductor device. A semiconductor device 101 shown in FIG. 1 includes a semiconductor substrate 31, a decoupling capacitor 32 provided on the upper surface of the semiconductor substrate 31, and a semiconductor integrated circuit device (chip) 30 provided on the upper surface of the semiconductor substrate 31 via solder bumps 34. The heat spreader 28 provided on the upper surface of the semiconductor substrate 31 via the adhesive sheet 33, the heat conductive adhesive 29 provided between the upper surface of the chip 30 and the heat spreader 28, and the solder provided on the lower surface of the semiconductor substrate 31. It consists of a ball pin 35. An underfill resin 36 is provided in a portion other than the solder bump between the chip 30 and the semiconductor substrate 31. Each decoupling capacitor 32 is disposed in a space provided between the heat spreader 28 and the semiconductor substrate 31.

  For example, the external dimensions of the chip 30 are 14.0 mm × 15.3 mm, the minimum bump pitch (pad pitch) is 176 μm, the bump arrangement is a full matrix, the peripheral peripheral columns of the I / O section are 17, the peripheral rows are 15, A staggered core has a bump pitch of 352 μm, a bump pitch of 176 μm (78 bumps) in the horizontal direction, and 176 μm (86 bumps) in the vertical direction for a total of 5,132 bumps.

  The macro blocks in the peripheral hard macro block area other than the core area at the center of the chip 30 are composed of a total of 12 blocks and one block of the PLL control circuit. Within each of the 12 blocks other than the PLL control circuit, one set of differential clocks for output signals (two negative / positive pairs / set) and one set of differential clocks for input signals (negative and positive 2) There are 2 sets (4 sets) of (book / set), and as an electrical constraint condition, the clock signal is equally delayed in the differential set. In other words, the electrical constraint condition is such that it can operate even with an ultra-high-speed clock of 800 MHz or 1.33 GHz.

  The external dimensions of the semiconductor substrate 31 are 47.5 mm × 47.5 mm (JEDEC Standard), the pin arrangement is full matrix, the pin pitch is 1.0 mm in the horizontal direction (46 pins), and 1.0 mm in the vertical direction (46 pins). A total of 2,116 pins has a BGA configuration.

  For example, the decoupling capacitor 32 includes three types. One type of decoupling capacitor 32 has an outer dimension of 1.6 mm × 1.85 mm, a pin arrangement of a full matrix, a pin pitch of 0.4 mm (four pins) in the horizontal direction, and 0.4 mm (pins) in the vertical direction. A total of 16 pins (4) are provided from 5 to a maximum of 10 pins. The external dimensions of the second type decoupling capacitor 32 are 2.5 mm x 2.0 mm, the pin pitch is 0.25 mm (8 pins) in the horizontal direction, and 0.5 mm (2 pins) in the vertical direction. Up to four are provided. The external dimensions of the third type decoupling capacitor 32 are 2.5 mm × 1.75 mm, and a total of 10 pins are provided from 8 to a maximum of 20.

  The chip 30 and the capacitor 32 are mounted on the semiconductor substrate 31, and the number of signal I / Os from the bumps to the pins = 1196 (including 34 sets of differential wirings) is composed of five wiring layers, power supply / ground. (GND) The semiconductor device (semiconductor package) 101 having a total number of layers including a solid plane layer = 19 layers and a multi-pin, high-density wiring exceeding 2,000 can be designed.

  Further, by providing the heat spreader 28 on the upper surface of the chip 30, it is possible to provide the FCBGA structure semiconductor device 101 having a high performance package with good heat dissipation.

  Next, a method for designing the semiconductor device 101 will be described.

  FIG. 2 is a flowchart for explaining an embodiment of a method for designing the semiconductor device 101 of the present invention.

  First, in step S1, component information, a net list, and the like are input. In step S2, the bump coordinates of the chip 30, that is, the wiring start point 4 shown in FIG. In step S3, an XY grid line composed of a grid vertical line 1 in the Y-axis direction and a grid horizontal line 2 in the X-axis direction is drawn based on the center coordinate point of all the bumps 34 of the chip 30 that has been input. Pin numbers 3 are assigned to the vertical and horizontal axes of the grid lines as shown in FIG.

  In step S4, the pin coordinates of the semiconductor substrate 31 are input as shown in FIG. Also here, the input pin coordinates of the semiconductor substrate 31, that is, the end point 5 of the wiring is input. In step S5, an XY grid line composed of a grid vertical line 1 in the Y-axis direction and a grid horizontal line 2 in the X-axis direction is drawn based on the input center coordinate points of all the pins of the semiconductor substrate 31. Pin numbers 3 are assigned to the vertical and horizontal axes of the grid lines.

  In step S6, the chip 30 is overlaid on the semiconductor substrate 31 having the maximum outer dimensions as shown in FIG. At this time, the center coordinates of the chip 30 are aligned with the center coordinates of the semiconductor substrate 31. Details of step S6 will be described later. In step S <b> 7, if the end point 5 of the semiconductor substrate 31 and the start point 4 of the chip 30 can be shared, a first via coordinate sharing process for rearranging to a shareable position is performed. FIG. 5 shows the outline 6 of the semiconductor substrate and the outline 7 of the semiconductor integrated circuit device, and 9 shows the reference line of the layout division region. The XY plane area 8 indicated by hatching will be described later.

  FIG. 6 shows an XY plan view of the chip 30. A land 10 is created at the start point 4 in the XY plane of FIG. FIG. 7 shows an XY plan view of the semiconductor substrate 31. A land 10 is created at the end point 5 in the XY plane of FIG.

  Next, in step S8, the coordinates of the heat spreader 28 are input as constraints for the arrangement of the capacitors 12, and in step S9, physical constraints (layout rules) for the arrangement range of the capacitors 12 that are passive elements are input. FIG. 8 is an XY plan view showing the arrangement of the heat spreader 28 and the capacitor 12 with the mounted components seen through. In FIG. 8, when the outer dimension D5 of the semiconductor substrate 31 is 1.00, the ratio of the outer dimension D4 of the heat spreader 28 to the dimension D5 is 0.91 to 0.87.

  In step S10, as shown in FIG. 9, a second via coordinate sharing process is performed in which the center coordinates of the bumps (terminals) of the capacitor 12 as a passive element can be shared with the coordinates of the end point 5 of the semiconductor substrate 31. Then, vias 11 are generated in the vertical Z direction at the start point 4 and the end point 5, which are the intersections of the XY grid lines of the component. FIG. 9 is an XY plan view showing the placement of the mounted components in a state where the mounted components are seen through. Here, the capacitor 12 is arranged in the vicinity of the macro block of the chip 30. This capacitor 12 is connected between the macro power supply and the GND plane via the via 11 to reduce the inductance, thereby reducing the power supply noise by reducing the power supply noise to the minimum loop area with the minimum impedance. ing. Similarly to the capacitor 12, the PLL macro power supply capacitor 13 is also arranged in the vicinity of the PLL macro provided in the chip 30. These capacitors 12 and 13 correspond to the capacitor 32 shown in FIG.

  FIG. 10 is a flowchart for explaining the process of step S6 in more detail. When the macroblock and net assignment process shown in FIG. 10 is started, the number and type of macroblocks of the chip 30 are confirmed in step S61, and the number of I / O bumps for each macroblock is confirmed in step S62. . FIG. 11 is a diagram showing a macro arrangement of the chip 30. In this case, the chip 30 includes 13 macro blocks C-1 to C-13. The bump pitch of the macroblocks C-1 to C-12 is 176 μm, and the bump pitch of the macroblock C-13 is 352 μm.

  In step S63, the ratio of the total number of I / O pins and the number of power supply / GND pins of the semiconductor substrate 31 is confirmed. In this case, since the number of I / O pins is 1,196 and the total number of pins is about 2,116, the 920 pin, which is the difference between these pins, is assigned to the power supply / GND pin. .

  In step S64, it is determined whether or not the JEDEC standard BGA. If the determination result is NO, the process returns to step S62. In this case, the number of I / O pins is 1,196, the number of power supply pins is 460, the number of GND pins is 460, and the total is 2,116 pins. Since this is a JEDEC standard BGA, the determination result in step S64 Is YES, and the process proceeds to step S65.

  In step S65, the number of BGA pins is determined as shown in FIG. FIG. 12 is a diagram showing the pin arrangement on the semiconductor substrate 31, and shows a case where the semiconductor substrate 31 is composed of macroblocks B-1 to B-13. Macro blocks C-1 to C-13 of the chip 30 shown in FIG. 11 are arranged in the macro blocks B-13 of the semiconductor substrate 31 shown in FIG. The core power supply / GND pin of the semiconductor substrate 31 is housed in the macro block B-13. In step S66, the basic structure of the semiconductor device 101 is determined as shown in FIG. FIG. 13 is a diagram illustrating a macro arrangement and a pin arrangement of the semiconductor device 101. As shown in FIG. 13, the outer dimensions of the chip 30 are within the core power supply / GND pin area in the macro block B-13 of the semiconductor substrate 31, that is, the center coordinates of the chip 30 and the semiconductor substrate 31. The chip 30 and the semiconductor substrate 31 are overlapped with each other in a state in which the center coordinates are aligned.

  In step S67, for example, as shown in FIG. 14, from the intersection (start point) of the lattice line of the macroblock C-2 of the chip 30 to the intersection (endpoint) of the macroblock B-9 of the semiconductor substrate 31 according to the via matrix. Net assignment is performed, the process ends, and the process proceeds to step S7 shown in FIG. FIG. 14 is a diagram for explaining net assignment to the macroblock of the chip 30 and the macroblock of the semiconductor substrate 31.

  Up to the above processing is the processing content in two dimensions on the XY plane. Next, the processing content in the two-dimensional XZ plane will be described.

  In step S11 shown in FIG. 2, a wiring layer number setting process in which the wiring layer number 14 of the wiring layer 16 of the semiconductor substrate 31 is set is performed. FIG. 15 is a flowchart for explaining the process of step S11 in more detail. In FIG. 15, in step S111, as shown in FIG. 16, the number of wiring layers 14 of the semiconductor substrate 31 is set. FIG. 16 is an XZ plan view (cross-sectional view of the semiconductor substrate 31) showing only the wiring layer 16 of the semiconductor substrate 31, and the number of wiring layers 14 is 5, that is, when five wiring layers 16 are provided. Indicates.

  In step S112, XZ lattice lines are drawn based on the wiring layer 16 of the semiconductor substrate 31 and the pin center coordinates of the semiconductor substrate 31, as shown in FIG. As a result, XZ lattice lines are drawn from the XZ plane in the same manner as described above for the start point 4 and the end point 5, which are the intersections of the XY lattice lines on the XY plane. Here, pin numbers 3 are assigned to the vertical and horizontal axes of the grid lines. In step S113, as shown by a thick solid line in FIG. 16, the via 11 is generated in a V-shaped pattern in the vertical and vertical direction from the starting point of the chip 30 to the wirings WL1 to WL5 of each wiring layer 16. As a result, the bumps of the chip 30 are connected in order from the bumps WL1 to WL5. In step S114, it is determined whether the number of wiring layers 14 is sufficient. If the determination result is NO, the process returns to step S111, and the total number of wirings 14 is increased in step S111 as necessary. On the other hand, if the decision result in the step S114 is YES, the process ends and proceeds to a step S12 shown in FIG.

  In step S12 shown in FIG. 2, a power supply / GND connection setting process is performed. FIG. 17 is a flowchart for explaining the process of step S12 in more detail. 17, in step S121, the power supply / GND plane layer 18 shown in FIG. 18 is defined, and the number of substrate layers 17 of the semiconductor substrate 31 is set. FIG. 18 is an XZ plan view showing the number of layers of the semiconductor substrate 31. Specifically, in step S121, 1.2V and 2.5V I / O macroblock power supplies and their GNDs, 1.2V core power supplies and their GNDs, PLL power supplies, and PLL GNDs are set. Is done. 18, L1 is a C4 (Controlled Collapsed Chip Connection) pad layer, L2 is a 2.5V power plane layer, L3 is a GND plane layer, L4 is a 1.2V power plane layer, and L5 is a GND plane. Layer, PLL power supply wiring and PLL GND wiring, L6 is a 1.2V power supply plane layer, L7 is a wiring WL1 layer, L8 is a GND plane layer, L9 is a wiring WL2 layer, L10 is a 1.2V power supply plane layer, L11 is a wiring WL3 layer, L12 is a GND plane layer, L13 is a wiring WL4 layer, L14 is a 1.2V power plane layer, L15 is a wiring WL5 layer and a GND plane layer, L16 is a 1.2V power plane layer, and L17 is GND. The plane layer, the PLL power supply wiring and the PLL GND wiring, L18 is a 1.2 V power supply plane layer, and L19 is a pad layer. That is, the number of substrate layers 17 in this case is 19. In FIG. 18, the wirings WL1 to WL5 layers L7, L9, L11, L13, and L15 are indicated by thick solid lines.

  As will be described later, among the conductor layers made of Cu or the like constituting each power supply / GND plane layer 18, two conductor layers adjacent in the vertical direction in FIG. 18 are insulated by an insulating layer made of, for example, glass ceramics or the like. Yes.

  Note that the thickness of the insulating layer, the thickness of the conductor layer, and the wiring rules enable impedance matching.

  In step S122, the power supply bump and the GND bump from the chip 30 are set as the starting point 4, the power supply terminal and the GND terminal of the capacitor 12 are also set as the starting point 4, and the specified layer is thick among the layers L1 to L19 defined as described above. Vias 11 are generated in the vertical and vertical directions as indicated by solid lines. When a power supply or GND is specified for the pin that is the end point 5 of the semiconductor substrate 31, the vias 11 are formed in the vertical and vertical directions from the respective power supply / GND plane layers 18 toward the end point 5 as indicated by thick solid lines. generate.

  FIG. 18 shows the case where the capacitors 12 and 13 have three terminals, but the number of terminals may be two or more. If capacitors 12 and 13 having a known configuration having three or more terminals are used, two or more types of capacitors can be realized using the same capacitors 12 and 13.

  In step S123, a collection of via tiles is verified using a two-dimensional XY plane coordinate system. An XY plane region 8 shown in FIG. 9 shows a part to be verified in this way. Here, when viewed in the XY plane coordinate system, there are 16 1 via tiles.

  In step S124, the via cubic aggregate is verified in a three-dimensional XYZ (orthogonal) coordinate system.

  FIG. 19 is a three-dimensional basic minimum unit XY / XZ plane extraction diagram surrounded by the lattice lines of the XY plane and the XZ plane. This is an excerpt from FIGS. 5, 7, 9, and 16, and corresponds to an example in which the XY plane region 8 and the XZ plane region 13 related to the wirings WL 3 and WL 4 are overlapped.

  FIG. 20 is obtained by replacing FIG. 19 with coordinate values (X, Y, Z). The X-axis and Y-axis indicate the pin number 3, and the Z-axis direction is 14 wiring layers or 17 substrate layers. Here, assuming that the power source and the GND pin are not determined, the number of wiring layers is 14.

  FIG. 21 is shown as a matrix expansion diagram in order to consider FIG. 20 more geometrically. When only the wiring layer 16 of the Z-axis wiring WL3 is viewed on a single layer plane, (X, Y, Z) = (C, 5, L11) = a11, (X, Y, Z) = (D, 5, L11) = a12, (X, Y, Z) = (C, 4, L11) = a21, (X, Y, Z) = (D, 4, L11) = a22. When only the wiring layer 16 of the Z-axis wiring WL4 is viewed as a single layer, (X, Y, Z) = (C, 5, L13) = a11, (X, Y, Z) = (D, 5 , L13) = a12, (X, Y, Z) = (C, 4, L13) = a21, and (X, Y, Z) = (D, 4, L13) = a22.

  In the matrix development diagram of FIG. 21, the result of showing the combination of the via matrix (matrix) with “1” when the via 11 is present and “0” when there is no via is shown in FIG. Thus, on the single-layer plane of the wiring WL3, 4 squares = 16 combinations are possible. Similarly, on the single-layer plane of the wiring WL4, 4 squares = 16 combinations are possible, and this is one of the minimum basic units. A BGA XYZ lattice in which wirings WL1 to WL5 are drawn in this minimum basic unit is combined to complete a via matrix of the XYZ coordinate system.

  In step S125, it is determined whether or not the generated via 11 is connected to the power supply / GND plane layer 18. If the determination result is NO, the process returns to step S123. On the other hand, if the decision result in the step S125 is YES, a step S126 decides whether or not the number of layers of the power / GND plane layer 18 is the number of layers that can be connected to all the pins of the semiconductor substrate 31. If the determination result of step S126 is NO, the process returns to step S121. If the determination result of step S126 is YES, the process ends and proceeds to step S13 shown in FIG.

  The via 11 generated in this way becomes an obstacle when the wiring is drawn by the wiring layer 16. In the wiring layer 16, while satisfying the clearance rule of the via 11 and the via 11 which is a physical constraint condition, We have made preparations to draw wiring.

  In step S13 shown in FIG. 2, a wiring design process is performed. FIG. 23 is a flowchart for explaining the process of step S13 in more detail. As shown in FIG. 24, the portion immediately below the land 10 at the end point 5 of the semiconductor substrate 31 overlaps with the land 10 at the start point 4 of the chip 30. In this case, the land 10 at the start point 4 has a bump pitch of 176 μm, but the land 10 at the end point 5 of the semiconductor substrate 31 has a pin pitch of 1.0 mm. Is the coordinate point of the start and end points. In FIG. 23, in step S131, wiring is drawn out from the starting point 4 of the chip 30 with 90-degree wiring (in parallel to the grid lines) as shown in FIG. In addition, since such 90 degree | times wiring satisfy | fills physical restrictions, wiring density becomes the maximum. In this manner, in step S131, the wiring is drawn out with the actual wiring. In this case, since the drawn wiring has the first configuration point where the first via 11 becomes an obstacle, in step S132, the wiring angle is changed at the first configuration point.

  From the first configuration point shown in FIG. 24, considering the crosstalk noise between the wirings, the wiring rule is converted into one that satisfies the electrical constraint condition as well as the wiring interval satisfies the physical constraint condition. 20 is performed.

  That is, in step S133, the wiring direction 26 is verified for each macroblock as shown in FIG. 25 and FIGS. 27 to 31, FIG. 33, and FIG. 37, which will be described later, the broken arrow indicates the wiring direction 26, and the wiring direction 26 can be set for each wiring direction 26 indicated by the broken arrow 90. A pair of solid arrows indicating the degree range are shown. FIG. 26 is a diagram illustrating an example of wiring angles θ1 to θ3 that can be fanned out. In FIG. 26, a pair of arrows shown by broken lines with respect to the vias 11-1 to 11-4 shown on the lower side, the vias 11-1 and 11-2 do not reverse the wiring direction (without detouring the wiring). A pair of arrows indicated by solid lines indicates a wiring angle θ2 that can be routed between the vias 11-2 and 11-3 without reversing the wiring direction, and a pair of dashed lines indicates The arrow indicates the wiring angle θ3 that allows wiring between the vias 11-3 and 11-4 without reversing the wiring direction.

  FIG. 27 is a diagram for explaining the number of wiring directions 26, which is the same as the number of macroblocks. The number of wiring directions 26 shown in FIG. 27 is larger than the number of conventional wiring directions shown in FIG. 28, and it can be seen that the degree of freedom of wiring is high. FIG. 29 is a diagram showing a wiring direction 26 in which fan-in is performed from both sides while making an angle to the next macroblock along the end face of the macroblock. The number of wiring directions 26 shown in FIG. 29 is larger than that of the conventional fan-out wiring direction shown in FIG.

  In step S134, the wiring area for each macroblock is verified. FIG. 31 is a diagram showing the arrangement of the macroblocks and the pin assignment area 27 of the semiconductor device 101. In step S135, the number of wirings between the vias 11 of the created via tile in FIG. 31 is verified. In this case, the differential wiring is verified as equivalent to a single wiring.

  In step S136, it is determined from the relationship of net assignment from the macro block of the chip 30 to the macro block of the semiconductor substrate 31 shown in FIG. If the decision result in the step S136 is NO, the process returns to the step S133. On the other hand, if the decision result in the step S136 is YES, in a step S137, whether or not the aggregate of the macroblocks B-1 to B-13 assigned to each macroblock of the semiconductor substrate 31 is a square (JEDEC Standard BGA). This is determined from the relationship of the net assignment from the macro block of the chip 30 to the macro block of the semiconductor substrate 31 shown in FIG. If the decision result in the step S137 is NO, the process returns to the step S133.

  32 and 33 show a case where the external dimensions of the semiconductor substrate 31 are larger than those shown in FIG.

  If the decision result in the step S137 is YES, in a step S138, it is judged whether or not connection to the end point has been made without detouring the wiring. If the decision result in the step S138 is NO, in a step S139, pin swapping, that is, net replacement is performed to prevent the detour of the wiring, and the process returns to the step S138. On the other hand, if the decision result in the step S138 is YES, in the step S140, as described with reference to FIGS. 19 to 22, when the via matrix is the minimum unit, any one of 16 combinations in a single layer is set. The

  In step S141, pin assignment is determined in the wiring direction 26 and the wiring area. The pin assignment can be determined based on FIGS. 25, 26, 31, and 34 to 36. That is, the wiring direction 26 and the wiring area can be determined as described with reference to FIGS. 25 and 26, and the pin assignment area 27 can be determined as described with reference to FIG. Further, single wiring / differential wiring can be determined as shown in FIG. 34, and wiring between vias 11 can be determined as shown in FIG. Furthermore, the enlargement of the wireable dimension between the vias 11 can be determined as shown in FIG. After step S141, the process ends and proceeds to step S14 shown in FIG.

  As described above, the coordinate values shown in FIG. 20 can be obtained from the XY plan view made of the XYZ lattice lines shown in FIG. 9 and the XZ plan view shown in FIG. 16, and the V-shaped pattern shown in FIG. 8 and the via 11 generated in the vertical and vertical directions for the power supply and GND shown in FIG. 8, the layout data is an assembly of any one of the minimum basic units of the via matrix. . 34 to 36 show a method of drawing single-ended wiring and differential wiring in this assembly.

  FIG. 34 shows a case where the distance between adjacent vias 11 is d, 2d, and √2d.

  FIG. 35 shows a wiring method between the vias 11. As a premise, two differential wirings are considered to be equivalent to a single-ended wiring. Considering physical constraints and electrical constraints, if there is only one wiring 22 between the vias 11 (case C1), physical constraints and electrical constraints between the vias 11 are doubled. In consideration of the design rule 21, four wires 22 can be passed through the routable area 23 (case C2). However, in this case, it is assumed that all the wirings 22 are 90 degree wirings and the wiring density is maximum. In FIG. 35, the routable dimension 23 of the case C1 is d1, and the routable dimension 23 of the case C2 is d2. In addition, DD1 and DD2 indicate intervals provided between the wiring 22 and the left and right vias 11 according to the design rule 21.

  If it is desired to enlarge the routable area 23 between the vias 11, the vias 11 are moved to perform wiring equalization 24 as shown in FIG. By performing the wiring equalization 24, there is an effect that the manufacturing margin of the semiconductor substrate 31 is widened and the manufacturability is improved. Further, without moving the via 11, the land 10 of the via 11 is moved to enlarge the wiring possible dimension 23, and the wiring equalization 24 is performed with the minimum wiring interval 25, whereby high-density wiring can be performed. In FIG. 36, in addition to the cases C1 and C2, a case C3 in which five wires 22 are passed with a wireable dimension 23 of d3, and a case in which six wires 33 are passed with a wireable size 23 of d4. C4 is shown.

  Next, a method for pin assignment of the semiconductor substrate 31 within the wiring direction 26 and the pin assignment region 27 will be described in more detail with reference to FIG. Conventionally, as shown in FIG. 37, the wiring 22 from one side of the chip 30 is drawn in the diagonal direction of the semiconductor substrate 31, and the wiring direction 26-1 is as shown in FIG. 1 was filled.

  However, as the integration of FETs (Field-Effect Transistors) in the chip 30 increases and the chip 30 becomes more sophisticated, the miniaturization of the wiring and the higher density of the wiring advance, and the number of signal I / Os increases. It is increasing. The bump pitch of the bumps 34 of the chip 30 is 176 μm, which tends to be a narrow bump pitch. For this reason, in the semiconductor substrate 31, it becomes a high-density wiring and a super many pin tendency, and the external dimension 6 of the semiconductor substrate 31 has expanded. Also, the pin pitch of the solder ball pins 36 is 1.0 mm. In order to change the pitch from 176 μm to 1.0 mm of BGA, the pin assignment must be performed without changing the wiring direction 26 or the pin assignment area 27 shown in FIG. Is no longer possible.

  FIG. 25 shows a schematic diagram of the wiring direction 26 and the pin assignment area 27 when the number of pins of the BGA is 2,116 and the number of signal I / Os is 1196. First, a region surrounded by a solid line arrow in the wiring direction 26 and a broken line arrow in the wiring direction 26 in a direction substantially perpendicular to the wiring direction 26 is a pin assign area 27.

  From the next macroblock of the chip 30, an angle is given in the direction of the solid arrow in the adjacent wiring direction 26. A region surrounded by a broken line arrow in the wiring direction 26 in a direction substantially perpendicular to the solid arrow direction is a pin assign region 27.

  In FIG. 31, the hard macroblock of the chip 30 is shown with a different background pattern. As can be seen from FIG. 31, the pin assignment of the signal in the macroblock of the chip 30 is on the side, and the via matrix extends inward from the 45 ° angle in the clockwise direction and the counterclockwise direction, so-called diagonal direction of the semiconductor substrate 31. The wiring is drawn within the combination, and the pin assignment is determined.

  At this time, the wiring is not a wiring that bends at 90 degrees and makes a detour as in the maze method, but is wired according to the combination of the via matrix from the start point 4 to the end point 5 according to the wiring direction. The wiring is connected from the coordinate point of the via 11 immediately below the start point 4 to the coordinate point of the via 11 immediately above the end point 5 without straddling the vertical layers. This is to prevent a parasitic capacitance from being formed between the wirings and between the vias 11 when the wirings straddle between the layers.

  In FIG. 2, in step S14, a connection table, a net list, and layout data are output. In other words, the netlist is output for those for which pin assignment has been completed and connections have been completed, and a comparison inspection is made to verify that the connections are correct, and the design is completed after verification. Also, if necessary, report LCR (inductance L, capacitance C, resistance R), create IBIS (Input / output Buffer Information Specification) data, extract SPICE (Simulation Program with Integrated Circuit Emphasis) net, etc. The design may be completed. In step S15, a drawing of the semiconductor layer device 101 is created based on the output data, and the process ends.

The design method has the following features (1) to (11).
(1) The combination of the two-dimensional via information on the XY plane and the XZ plane is expanded into a combination of via matrixes to obtain three-dimensional via information. As described above, since a semiconductor device can be designed by a combination of three-dimensional via matrices, it is possible to design a semiconductor device even for a beginner other than an expert.
(2) Superposition is performed using grid lines on the XY plane with the terminal coordinate point of the component (chip and semiconductor substrate) of the semiconductor device as a base point. As a result, vias can be shared (first via coordinate sharing process), the cost of via forming dies can be reduced, and unnecessary stub lines and parasitic capacitance can be reduced.
(3) The arrangement of vias is verified with a three-dimensional element made up of grid lines on the XY plane (two-dimensional) and grid lines on the XZ plane (two-dimensional). As a result, high-speed design and high-density wiring can be realized, and the number of semiconductor substrate layers can be reduced.
(4) Consider a combination of via matrixes on the XY plane and the XZ plane, and verify a wiring obstacle called a via in advance for the combination. Thereby, the wiring route can be searched efficiently at high speed, and the number of wiring layers can be estimated at high speed.
(5) Design by replacing the differential wiring as equivalent to the single-ended wiring. As a result, the wiring route can be searched efficiently at high speed, and the number of wiring layers can be estimated at high speed.
(6) When a signal in a macro block of a chip is net-assigned to the BGA side, the position of the macro block of the chip is first considered, and the signal is assigned to the BGA area in the vicinity thereof. Thereby, the wiring length can be shortened and the circuit load can be reduced.
(7) A decoupling capacitor is arranged in the BGA net assignment area near the hard macroblock area of the chip, and the macroblock power supply and the GND plane are connected via a plurality of vias. As a result, the inductance can be reduced, and the power supply noise can be reduced by making the minimum loop area with the minimum impedance, thereby stabilizing the power supply.
(8) The I / O signal of the hard macroblock of the chip is net-assigned in the vicinity thereof, and the upper and lower layers of the semiconductor substrate are constituted by the power supply plane and the GND plane of the drive power supply of the I / O macroblock. As a result, a combination in which the power plane layer and the GND plane layer paired with the wiring layer are provided in the upper part or the lower part can be combined, the signal integrity is improved, and high-density wiring can be realized.
(9) When assigning nets to pins on a semiconductor substrate, take the semiconductor substrate in a cross shape and fan inward from the center in the order of 45 degrees clockwise and counterclockwise, so-called diagonal direction of the semiconductor substrate Draw wiring within the via matrix combination and determine the net assignment. Thereby, it is possible to perform high-density wiring while reducing the waste of the area up to the corner area of the semiconductor substrate.
(10) The high-density wiring design of 90 degree wiring, which is the design rule of the board manufacturing limit of the physical constraint condition, is performed only in the wiring drawing portion, and wiring rule conversion is performed from the first component point. As a result, the wiring lead-out portion is configured to be wired in a layer in the semiconductor substrate having a pad-on-via structure, and thus the via portion becomes an impedance mismatching portion. Therefore, signal integrity is improved by achieving impedance matching which is an electrical constraint condition from the first configuration point onward, and high-density wiring can be realized. Moreover, pitch conversion can be performed effectively.
(11) Wiring between vias in a combined region of a via matrix of BGA lattice lines of a semiconductor substrate (that is, in a wiring region) is equalized (wiring equalization). Thereby, the manufacturability of the substrate can be improved and the yield can be improved.

  FIG. 38 is a cross-sectional view showing a second comparative example of the semiconductor device, and shows the semiconductor device 102. FIG. 39 is a cross-sectional view showing a third comparative example of the semiconductor device, and shows the semiconductor device 103. In FIGS. 38 and 39 and FIGS. 40 to 45 to be described later, the same parts as those in FIG.

  The semiconductor device 102 illustrated in FIG. 38 has the common via 11 as the semiconductor device 103 illustrated in FIG. 39, but the number of capacitors 32 is smaller in the semiconductor device 102 than in the semiconductor device 103. Also, the semiconductor device 103 shown in FIG. 39 has a larger number of vias 11 of the capacitor 32 than the semiconductor device 102. Each of the semiconductor devices 102 and 103 is configured to easily share the via 11 by configuring the power supply and the GND layer as upper layers.

  FIG. 40 is a cross-sectional view showing a fourth comparative example of the semiconductor device, and shows the semiconductor device 104. In the semiconductor device 104, the heat spreader 28, which is a heat radiating plate, is omitted.

  FIG. 41 is a cross-sectional view showing a fifth comparative example of the semiconductor device, which is the semiconductor device 105 and a comparative example in which the shape of the heat spreader 28 is changed.

  Each of the semiconductor devices 102 to 105 shown in FIGS. 38 to 41 has a structure capable of multi-pin high-density wiring.

  FIG. 42 is a cross-sectional view showing a sixth comparative example of the semiconductor device, and shows the semiconductor device 106. A recess 37 is provided below the chip 30 on the lower surface of the semiconductor substrate 31 of the semiconductor device 106, and the decoupling capacitor 32 is also disposed in the recess 37. Since the number of BGA solder ball pins 35 is small, it is not suitable for a multi-pin structure with single-ended wiring. However, in the future, when high-speed signal transmission in a macroblock advances, it will become a differential wiring. Is an effective structure. The decoupling capacitor 32 provided on the lower surface of the semiconductor substrate 31 may be provided in a region other than the lower side of the chip 30.

  FIG. 43 is a cross-sectional view showing a seventh comparative example of the semiconductor device and shows the semiconductor device 107. A recess 37 is provided below the chip 30 on the lower surface of the semiconductor substrate 31 of the semiconductor device 107, and all the decoupling capacitors 32 are disposed in the recess 37. In this case, the structure is effective in that the wiring density is maximized. The decoupling capacitor 32 may be provided on the lower surface of the semiconductor substrate 31 and in a region other than the lower side of the chip 30.

  FIG. 44 is a cross-sectional view showing an eighth comparative example of the semiconductor device, and shows the semiconductor device 108. FIG. 45 is a cross-sectional view showing a ninth comparative example of the semiconductor device and shows the semiconductor device 109. The semiconductor devices 108 and 109 are examples in which the heat dissipation structure is changed, the semiconductor device 108 is an example in which the heat spreader 28 is fixed to the semiconductor substrate 31 via the stiffener 38, and the semiconductor device 109 is made of mold resin 39. In this example, the surface of the semiconductor substrate 31 is sealed.

  Each of the semiconductor devices 106 to 109 shown in FIGS. 42 to 45 has a structure capable of multi-pin high-density wiring.

  Next, a structure for suppressing the package inductance of the semiconductor devices 101 to 109 will be described.

  In the first structure, in order to keep the package inductance of the semiconductor device low, a capacitor having a small equivalent series inductance effective for high-frequency signals and noise is placed near the chip 30 among the capacitors 12 and 13 (or 32). In addition, they are arranged at positions at equal distances from the chip 30. For example, capacitors having such a small equivalent series inductance are arranged along each side of the chip 30. FIG. 46 is an XZ plan view showing only the wiring layer 16 of the semiconductor substrate 31 taken out. In FIG. 46, the same parts as those of FIG. 16 are denoted by the same reference numerals, and the description thereof is omitted. In this example, among the dimensions D1 to D7, the dimension D6 between the mutually facing sides of the chip 30 and the capacitor 13 is 2 mm, and the dimension D7 between the mutually facing sides of the chip 30 and the capacitor 13 is 3 mm.

  In the second structure, in order to keep the sheet inductance low, the power supply layer and the GND layer are alternately arranged above the semiconductor substrate 31 in the power supply / GND plane layer 18 via an insulating layer. FIG. 47 is an XZ plan view showing the number of layers of the semiconductor substrate 31. 47, the same symbols are added to the same portions as FIG. 18, and the description thereof is omitted. In this example, the upper layers L2 to L6 of the semiconductor substrate 31 are alternately arranged via insulating layers. Since the sheet inductance can be reduced as the distance between the power supply layer and the GND layer is shorter, if the power supply layer and the GND layer are alternately arranged on the upper portion of the semiconductor substrate 31, the chip 30 through the via 11 in FIG. Thus, since it appears that there is a low-inductance power supply / GND sheet in the layer immediately after descending in the vertical and vertical direction, a path for high-frequency current flowing to the capacitors 12 and 13 can be secured.

  In the third structure, as shown by thick solid lines in FIGS. 46 and 47, the signal layer of the power supply / GND plane layer 18, specifically, from the starting point (bump 34) of the chip 30 provided on the upper side of the semiconductor substrate 31. The vias 11 are generated in a V-shaped pattern in the vertical and vertical direction up to the wiring layers L7 to L15 and the like provided in the middle portion of the upper semiconductor substrate 31 in the vertical and vertical direction. On the other hand, vias 11 are generated from the pins 35 on the lower side of the semiconductor substrate 31 to any layer of the power supply / GND plane layer 18 in an inverted V-shaped pattern in the vertical and vertical directions in accordance with the V-shaped pattern. Let Below the I / O bump (I / O macroblock) region of the chip 30, many vias 11 extend in the vertical and vertical directions, so that a current path in the vertical direction (vertical and vertical direction) of the semiconductor substrate 31 is secured. can do.

  In the semiconductor substrate 31, if there is a detour wiring under the I / O bump (I / O macroblock) area of the chip 30, the area where the via 11 connected to the power supply / GND plane layer 18 can be arranged is reduced. However, according to the third structure, such inconvenience does not occur. Also, if many via holes are open in the power supply / GND plane layer 18 in the power supply / GND plane layer, the return current of the signal cannot pass directly under the signal wiring, so that a detour wiring is required. As a result, the return path However, according to the third structure, such inconvenience does not occur.

  FIG. 48 is a cross-sectional view showing the layer structure of the semiconductor substrate 31. In FIG. 48, the same portions as those in FIG. 47 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 48, two conductor layers adjacent in the vertical direction are insulated by an insulating layer 501 made of glass ceramics. The insulating layer 501 is also provided on the upper surface of the C4 pad layer L1 and the lower surface of the pad layer L19.

  In the fourth structure, in the power supply / GND plane layer 18, the power supply layer and the GND layer are alternately arranged below the semiconductor substrate 31 via insulating layers. FIG. 49 is a cross-sectional view showing the film thicknesses of the layers L1 to L19 of the semiconductor substrate 31. FIG. As shown in FIG. 49, the distance between the upper surfaces of the layers L1 and L2 is 0.0762 mm, and the distance between the upper surfaces of the layers L2 and L6 is 0.0508 mm × 4 (the upper surfaces of two adjacent layers among the layers L2 to L6). The distance between the upper surfaces of the layers L6 and L16 is 0.1016 mm × 10 (the distance between the upper surfaces of two adjacent layers among the layers L6 to L16 is 0.1016 mm), the layers L16, The distance between the upper surfaces of L18 is 0.0508 mm × 2 (the distance between the upper surfaces of two adjacent layers among the layers L16 to L18 is 0.0508 mm), and the distance between the upper surfaces of the layers L18 and L19 is 0.2032 mm. . In this example, the lower layers L16 to L19 of the semiconductor substrate 31 are alternately arranged via insulating layers. Since the number of via holes is relatively small below the semiconductor substrate 31, a low-frequency current path can be secured. On the other hand, below the I / O bump (I / O macroblock) region of the chip 30, as in the third structure, many vias 11 can be configured to extend in the vertical and vertical directions. 31 current paths in the vertical direction (vertical vertical direction) can be secured.

  FIG. 50 is a perspective view showing the layer structure of the semiconductor substrate 31. FIG. 51 is a perspective view for explaining the upper layer and lower layer portions of the semiconductor substrate 31. 50 and 51, the same parts as those in FIGS. 1, 47 and 48 are denoted by the same reference numerals, and the description thereof is omitted. 50 and 51, the illustration of the insulating layer 501 is omitted for convenience of explanation. In FIG. 51, 34-1 is a signal bump, 34-2 is a power bump, 34-3 is a GND bump, 32-1 is a power bump of the decoupling capacitor 32, and 32-2 is a GND bump of the decoupling capacitor 32. . In the fifth structure, the decoupling capacitor 32 is provided with a plurality of vias 11 (two vias 11 in the example of FIG. 51) in one via region (one via hole). As described above, the bumps 32-1 and 32-2 of the decoupling capacitor 32 are connected to the lower power supply layer and the GND layer of the power supply / GND plane layer 18 of the semiconductor substrate 31 by the via 11 (see FIG. 18). As with the connection of the capacitor 12 on the left side), the sheet inductance can be kept low by paralleling the power supply surfaces in the XY directions. In addition, in the region below the chip 30, the vias 11 connected to the bumps 34 are arranged in parallel, so that the inductance of the vias 11 can be kept low. Note that the area under the chip 30 and the area under the decoupling capacitor 32 have different constraints on the pitch of the vias 11 provided in the semiconductor substrate 31 (via pitch), so the via pitch can be set as appropriate within each area. It is.

  Needless to say, two or more of the first to fifth structures can be appropriately combined.

  An embodiment of a semiconductor device designing apparatus of the present invention uses an embodiment of a semiconductor device designing method, an embodiment of a program according to the present invention, and an embodiment of a storage medium according to the present invention. . In this embodiment, the present invention is applied to a computer system. FIG. 52 is a perspective view showing a computer system such as a CAD apparatus to which the present invention is applied in this embodiment.

  A computer system 100 shown in FIG. 52 includes a main body 101 that includes a CPU, a disk drive, and the like, a display 102 that displays an image on a display screen 102 a according to instructions from the main body 101, and various information to the computer system 100. A keyboard 103, a mouse 104 for designating an arbitrary position on the display screen 102a of the display 102, and a modem 105 for accessing an external database or the like and downloading a program or the like stored in another computer system.

  The CAD system or at least the semiconductor device design of the CAD function is stored in the computer system 100 stored in a portable recording medium such as the disk 110 or downloaded from the recording medium 106 of another computer system using a communication device such as the modem 105. This embodiment of the program (CAD software or semiconductor device design software) that has a function is input to the computer system 100 and compiled. This embodiment of the program is operated as this embodiment of a design apparatus having a CAD function in the computer system 100 (that is, a CPU 201 described later). The present embodiment of the storage medium includes a computer-readable recording medium such as the disk 110 that stores the present embodiment of the program. This embodiment of the recording medium is not limited to a portable recording medium such as a disk 110, an IC card memory, a magnetic disk such as a floppy (registered trademark) disk, a magneto-optical disk, or a CD-ROM. Various recording media accessible by a computer system connected via a communication device such as a LAN or communication means are included.

  FIG. 53 is a block diagram illustrating a configuration of a main part in the main body 101 of the computer system 100. In FIG. 1, the main unit 101 includes a CPU 201 connected by a bus 200, a memory unit 202 including a RAM and a ROM, a disk drive 203 for the disk 110, and a hard disk drive 204. In this embodiment, the display 102, the keyboard 103, and the mouse 104 are also connected to the CPU 201 via the bus 200, but these may be directly connected to the CPU 201. The display 102 may be connected to the CPU 201 via a known graphic interface (not shown) that processes input / output image data.

  The configuration of the computer system 100 is not limited to the configuration shown in FIGS. 52 and 53, and various known configurations may be used instead.

  The semiconductor device design apparatus and program automatically design a semiconductor device to be designed by the CPU 201 according to the procedure shown in FIG.

In addition, this invention also includes the invention attached to the following.
(Supplementary Note 1) A semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent in the Z direction are insulated via an insulating layer, and a plurality of pads and lands. A method for designing a semiconductor device including a semiconductor chip provided on an XY plane above,
An overlaying step of superimposing the semiconductor chip on the semiconductor substrate by aligning the center coordinate on the XY plane of the semiconductor chip with the center coordinate on the XY plane of the semiconductor substrate;
Vias connected to the wiring among the power supply layer / ground layer / wiring layer from the starting point of the wiring of the semiconductor chip are arranged in the Z direction, and the number of wiring layers of the power supply layer / ground layer / wiring layer of the semiconductor substrate is set. A wiring layer number setting step to be set;
In the two-dimensional coordinate system of the XY plane and the XZ plane, the grid line is drawn in the XY direction and the XZ direction from the start point and the end point of the wiring, and vias are arranged at the intersections of the grid lines. And a connecting step of connecting vias to the designated power supply layer / ground layer / wiring layer by arranging vias in the XZ direction based on the via matrix. .
(Additional remark 2) After this superposition step, when the end point of the wiring of this semiconductor substrate and the starting point of the wiring of this semiconductor chip can be shared, it further includes the 1st via coordinate sharing step which rearranges to the position which can be shared. The method of designing a semiconductor device according to appendix 1, wherein:
(Supplementary note 3) The method further includes a constraint condition input step for inputting a constraint condition for disposing a plurality of passive elements provided on the semiconductor substrate in the periphery of the semiconductor chip after the superposition step. 3. A method for designing a semiconductor device according to 1 or 2.
(Supplementary note 4) The constraint condition input step inputs, as the constraint condition, XY coordinates of a heat spreader provided on the semiconductor substrate so as to cover the semiconductor chip and the plurality of passive elements. 3. A method for designing a semiconductor device according to 3.
(Supplementary Note 5) After the constraint condition input step, a second via coordinate sharing step is included in which the center coordinate of the terminal of any passive element is arranged at a position where it can be shared with the coordinate of the end point of the wiring of the semiconductor substrate. A method for designing a semiconductor device according to appendix 3 or 4, characterized by the above.
(Supplementary Note 6) In the wiring layer number setting step, vias are arranged in a V-shaped pattern on the XZ plane in the Z direction from the wiring starting point of the semiconductor chip to each wiring layer of the power supply layer / ground layer / wiring. A method for designing a semiconductor device according to any one of appendices 1 to 5, wherein the total number of wirings is increased if the number of wiring layers is not sufficient.
(Appendix 7) In the connection step, the upper and / or lower plane layers of the plurality of power supply layers / ground layers / wiring layers are used as power supply / ground plane layers. A method for designing a semiconductor device according to claim 1.
(Supplementary Note 8) Any one of Supplementary notes 1 to 7, wherein the wiring layer number setting step uses an intermediate layer as a wiring layer among the plurality of power supply layers / ground layers / wiring layers. The semiconductor device design method described.
(Supplementary note 9) The method for designing a semiconductor device according to any one of supplementary notes 1 to 8, wherein in the superimposing step, the input / output signal of the hard macroblock of the semiconductor chip is net-assigned in the vicinity thereof. .
(Supplementary Note 10) When the net is assigned to the pins on the semiconductor substrate after the connecting step, the semiconductor substrate is taken in a cross shape, and the fan-in is performed inward from 45 ° in the clockwise direction and the counterclockwise direction from the center. The semiconductor device according to any one of appendices 1 to 9, further comprising a wiring design step of drawing a wiring in a diagonal direction of the semiconductor substrate in accordance with a combination of via matrices and determining a net assignment. Design method.
(Supplementary Note 11) In the wiring design step, high-density wiring design of 90-degree wiring, which is a design rule of the board manufacturing limit of physical constraints only in the wiring drawing portion, is performed, and wiring rule conversion is performed from the first component point. The method for designing a semiconductor device according to appendix 10, wherein:
(Supplementary note 12) The semiconductor device design method according to supplementary note 10, wherein the wiring design step equalizes wiring between vias in a wiring region of the semiconductor substrate.
(Additional remark 13) The program characterized by including the procedure which makes a computer perform each step of the design method of the semiconductor device of any one of Additional remark 1-12.
(Supplementary note 14) A computer-readable storage medium storing the program according to supplementary note 13.
(Supplementary Note 15) A semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent in the Z direction are insulated via an insulating layer, and a plurality of pads and lands. A semiconductor device design apparatus comprising a semiconductor chip provided on an XY plane above,
Superimposing means for superimposing the semiconductor chip on the semiconductor substrate by aligning the central coordinate on the XY plane of the semiconductor chip with the central coordinate on the XY plane of the semiconductor substrate;
Vias connected to the wiring layer of the power supply layer / ground layer / wiring from the starting point of the wiring of the semiconductor chip are arranged in the Z direction, and the number of wiring layers of the power supply layer / ground layer / wiring layer of the semiconductor substrate is set. Wiring layer number setting means to be set;
In the two-dimensional coordinate system of the XY plane and the XZ plane, the grid line is drawn in the XY direction and the XZ direction from the start point and the end point of the wiring, and vias are arranged at the intersections of the grid lines. A semiconductor device design, comprising: a via matrix to be obtained; and connection means for arranging vias in the XZ direction based on the via matrix and connecting to a specified power supply layer / ground layer / wiring layer apparatus.
(Supplementary Note 16) In the wiring layer number setting step, vias are arranged in a V-shaped pattern on the XZ plane from the starting point of wiring of the semiconductor chip to each wiring layer of the power supply layer / ground layer / wiring in the Z direction. The semiconductor device design apparatus according to appendix 15, wherein the total number of wirings is increased if the number of wiring layers is not sufficient.
(Supplementary note 17) The supplementary note 15 or 16, wherein the connection step uses an upper and / or lower plane layer among the plurality of power supply layers / ground layers / wiring layers as a power supply / ground plane layer. Semiconductor device design equipment.
(Supplementary note 18) In any one of Supplementary notes 15 to 17, the wiring layer number setting step uses an intermediate layer as a wiring layer among the plurality of power supply layers / ground layers / wiring layers. The semiconductor device design apparatus described.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is sectional drawing which shows the 1st comparative example of a semiconductor device. 5 is a flowchart for explaining an embodiment of a semiconductor device design method of the present invention. It is a starting point lattice figure of a chip. It is an end point lattice figure of a semiconductor substrate. It is a figure which shows the superimposition of a chip | tip and a semiconductor substrate. It is a figure which shows XY top view of a chip | tip. It is a figure which shows XY top view of a semiconductor substrate. It is XY top view which shows arrangement | positioning of a heat spreader and a capacitor | condenser in the state by which the mounted component was seen through. It is XY top view which shows arrangement | positioning of a mounting component in the state by which the mounting component was seen through. It is a flowchart explaining the process of step S6 in detail. It is a figure which shows the macro arrangement | positioning of a chip | tip. It is a figure which shows the pin arrangement on a semiconductor substrate. It is a figure which shows the macro arrangement | positioning and pin arrangement | positioning of a semiconductor device. It is a figure explaining the net assignment to the macroblock of a chip | tip, and the macroblock of a semiconductor substrate. It is a flowchart explaining the process of step S11 in detail. It is a XZ top view which takes out and shows only a wiring layer of a semiconductor substrate. It is a flowchart explaining the process of step S12 in detail. It is XZ top view which shows the number of layers of a semiconductor substrate. It is an XY / XZ plane extraction diagram of a basic minimum unit in three dimensions surrounded by lattice lines of an XY plane and an XZ plane. FIG. 20 is a diagram in which FIG. 19 is replaced with coordinate values (X, Y, Z). FIG. 21 is a diagram illustrating FIG. 20 as a matrix development view. It is a figure which shows a via matrix. It is a flowchart explaining the process of step S13 in detail. It is a figure explaining a via shared coordinate and lead wiring rule conversion. It is a figure explaining a wiring direction and a wiring area | region. It is a figure which shows an example of the wiring angle which can be fanned out. It is a figure explaining the number of wiring directions. It is a figure explaining the conventional wiring direction. It is a figure which shows the wiring direction fanned in from both, giving an angle to the next macroblock along the end surface of a macroblock. It is a figure explaining the conventional wiring direction. It is a figure which shows arrangement | positioning and the pin assignment area | region of the macroblock of a chip | tip. It is a figure explaining the net assignment from the macroblock of a chip to the macroblock of a semiconductor substrate. It is a figure explaining the net assignment from the macroblock of a chip to the macroblock of a semiconductor substrate. It is a figure explaining the single wiring / differential wiring method. It is a figure explaining the wiring method between via | veer. It is a figure explaining the expansion method of the wiring possible dimension between via | veer. It is a figure explaining the conventional wiring direction and wiring area | region. It is sectional drawing which shows the 2nd comparative example of a semiconductor device. It is sectional drawing which shows the 3rd comparative example of a semiconductor device. It is sectional drawing which shows the 4th comparative example of a semiconductor device. It is sectional drawing which shows the 5th comparative example of a semiconductor device. It is sectional drawing which shows the 6th comparative example of a semiconductor device. It is sectional drawing which shows the 7th comparative example of a semiconductor device. It is sectional drawing which shows the 8th comparative example of a semiconductor device. It is sectional drawing which shows the 9th comparative example of a semiconductor device. It is a XZ top view which takes out and shows only a wiring layer of a semiconductor substrate. It is XZ top view which shows the number of layers of a semiconductor substrate. It is sectional drawing which shows the layer structure of a semiconductor substrate. It is sectional drawing which shows the film thickness of each layer of a semiconductor substrate. It is a perspective view which shows the layer structure of a semiconductor substrate. It is a perspective view explaining the upper layer and lower layer part of a semiconductor substrate. 1 is a perspective view showing a computer system to which the present invention is applied. FIG. 53 is a block diagram showing a main part of the computer system shown in FIG. 52.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lattice vertical line 2 Lattice horizontal line 3 Pin number 4 Start point 5 End point 6 Semiconductor substrate outline 7 Chip outline 8 XY plane area 9 Layout division area guide line 10 Land 11 Via 12 Capacitor 13 PLL power supply capacitor 14 Number of wiring layers 15 XZ plane area 16 Wiring layer 17 Number of substrate layers 18 Power supply / GND plane layer 19 Via sharing coordinate point 20 Wiring rule conversion 21 Design rule 22 Wiring 23 Wiring dimension 24 Wiring equalization 25 Minimum wiring interval 26 Wiring direction 27 Pin assign area 28 Heat spreader 29 Heat Conductive adhesive 30 Chip 31 Semiconductor substrate 32 (decoupling) capacitor 33 Adhesive sheet 34 Solder bump 35 Solder ball pin 36 Underfill resin 37 Substrate recess 38 Stiffener 39 Mold resin 100 Computer system 201 CPU
501 Insulation layer

Claims (5)

A computer has a semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent in the Z direction are insulated via an insulating layer, and a plurality of pads and lands. A program for executing a procedure of a design method of a semiconductor device including a semiconductor chip provided on the XY plane of
The semiconductor chip is superposed on the semiconductor substrate by aligning the central coordinate of the semiconductor chip on the XY plane with the central coordinate of the semiconductor substrate on the XY plane, and the input / output signals of the hard macroblock of the semiconductor chip are in the vicinity thereof. A superposition step for net assignment;
Vias connected to the wiring among the power supply layer / ground layer / wiring layer from the starting point of the wiring of the semiconductor chip are arranged in the Z direction, and the number of wiring layers of the power supply layer / ground layer / wiring layer of the semiconductor substrate is set. A wiring layer number setting step to be set;
In the two-dimensional coordinate system of the XY plane and the XZ plane, the grid line is drawn in the XY direction and the XZ direction from the start point and the end point of the wiring, and vias are arranged at the intersections of the grid lines. A connection step of obtaining a via matrix to be connected, and arranging a via in the XZ direction based on the via matrix and connecting to a designated power supply layer / ground layer / wiring layer;
After the connection step, when the net assigned to pins on the semiconductor substrate, take the cross on the semiconductor substrate, clockwise from the center, inside the angle of 45 degrees in the counterclockwise direction in the order, the semiconductor chip For each hard macroblock of the semiconductor chip, set the range in which the wiring direction of the hard macroblock can be set with an angle along the end face of the semiconductor chip, and set the wiring direction set for each hard macroblock Within the possible range, the wiring of each hard macroblock is drawn within the combination of the via matrix, and includes a procedure for executing each step of the semiconductor device design method including the wiring design step of determining the net assignment. Program.   In the wiring layer number setting step, vias are arranged in a V-shaped pattern on the XZ plane from the starting point of the wiring of the semiconductor chip to each wiring layer of the power supply layer / ground layer / wiring layer in the Z direction, 2. The program according to claim 1, wherein the number of wiring layers is increased if the number of wiring layers is not sufficient.   3. The program according to claim 1, wherein the connecting step uses an upper and / or lower plane layer among the plurality of power supply layers / ground layers / wiring layers as a power supply / ground plane layer. After the superposition step, each step of the semiconductor device design method further includes a constraint condition input step for inputting a constraint condition for arranging a plurality of passive elements provided on the periphery of the semiconductor chip on the semiconductor substrate. The program according to any one of claims 1 to 3, further comprising a procedure. A semiconductor substrate having a plurality of power supply layers / ground layers / wiring layers and a plurality of vias in which layers adjacent in the Z direction are insulated via an insulating layer, and an XY plane on the semiconductor substrate having a plurality of pads and lands A semiconductor device design apparatus comprising: a semiconductor chip provided on the semiconductor chip;
The semiconductor chip is superposed on the semiconductor substrate by aligning the central coordinate of the semiconductor chip on the XY plane with the central coordinate of the semiconductor substrate on the XY plane, and the input / output signals of the hard macroblock of the semiconductor chip are in the vicinity thereof. Superimposing means for net assignment;
Vias connected to the wiring layer among the power supply layer / ground layer / wiring layer from the starting point of wiring of the semiconductor chip are arranged in the Z direction, and the number of wiring layers of the power supply layer / ground layer / wiring layer of the semiconductor substrate Wiring layer number setting means for setting,
In the two-dimensional coordinate system of the XY plane and the XZ plane, the grid line is drawn in the XY direction and the XZ direction from the start point and the end point of the wiring, and vias are arranged at the intersections of the grid lines. Connecting means for obtaining a via matrix to be connected, and arranging a via in the XZ direction based on the via matrix to connect to a designated power supply layer / ground layer / wiring layer;
After connection by said connection means, when the net assigned to pins on the semiconductor substrate, take the cross on the semiconductor substrate, clockwise from the center, inside the angle of 45 degrees in the counterclockwise direction in order, the Along the end face of the semiconductor chip, for each hard macroblock of the semiconductor chip, the range in which the wiring direction of the hard macroblock can be set is set with an angle, and the wiring direction set for each hard macroblock A design apparatus for a semiconductor device, comprising: a wiring design means for drawing a wiring of each hard macroblock within a combination of via matrixes within a settable range and determining a net assignment.

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