JPH01239953A - Cmos type lsi - Google Patents

Abstract

PURPOSE:To obtain an LSI whose power consumption amount is low and which can be integrated highly by a method wherein a megamacro is constituted of a first Tr group where a dimension of a CMOS type LSI and its geometrical shape have been fixed to be one type and other logic circuits are constituted of a second Tr group whose dimension has been fixed to be different from that of the Tr group. CONSTITUTION:A first MOS Tr group 2, a memory region 3 and a second MOS Tr group 5 are formed in an integrated circuit pattern region of a CMOS type LSI chip 1; an I/O buffer and bonding pad region 4 is formed at an external peripheral part of the chip 1. A fundamental cell 7 for megamacro use is formed in this first Tr group 2; a fundamental cell 6 for chip use is formed in the second Tr group 5. A first Tr element 8 and a second Tr element 9 are arranged in the respective fundamental cells 6 and 7; a megamacro is constituted of the fundamental cell 7; other logic circuits are constituted of the fundamental cell 6; it is realized to form a CMOS type LSI whose power consumption is low and which can be integrated highly; it is possible to execute an automatic arrangement and wiring operation by using a computer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS type LSI, and particularly to a CMOS type LSI in which transistor dimensions and shapes are unified in its design method.

[Conventional technology]

Conventionally, in the design of such CMOS type LSIs, a gate array method has generally been widely adopted. In this gate array method, the channel length of the MOS transistor,
The dimensions and geometric shape such as channel width are fixed to one type, and this is an essential condition for versatility that can be applied to any circuit and automatic placement and wiring using a computer. There is. Further, in the stand-to-cell method as well, the demensicons and geometrical shapes are fixed to one type, similar to the gate array method.

FIGS. 2(a) and 2(b) are a plan view of a CMOS type SI chip and an enlarged view of its gate array, respectively, for explaining a conventional example.

As shown in FIG. 2 (a), the LSI chip 1 consists of a circuit pattern area 2' where transistors etc. are formed, an I10 buffer and a bonding pad area 4, and the circuit pattern area 2' has the same dimensions. A basic cell 6 having the same functional shape is formed.

In addition, this situation is shown enlarged in Fig. 2(b),
Transistor elements 8 of the same size and shape are formed to be complementary.

[Problem to be solved by the invention]

In the design of the conventional CMOS type LSI mentioned above, the dimension of the l transistor is set to a value with sufficient driving capacity, due to the requirements for circuit versatility and freedom in automatic placement and wiring. However, the values are not optimal for each transistor. Therefore, a CMOS type LSI manufactured according to such a design has the drawbacks of wasteful power consumption and an increase in chip area.

An object of the present invention is to provide a CMOS type LSI that consumes less power and has a smaller chip area.

[Means for Solving the Problems] A CMOS type LSI of the present invention includes a first MOS transistor group in which dimensions such as channel length and channel width of transistors and their geometrical shapes are unified into one type; The second MOS transistor group has unified transistor dimensions different from those of the first MOS transistor group, and has a unified geometric shape of one type.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to (C) are a plan view of a CMOS type LSI chip, an enlarged view of a basic cell for a chip constituting each transistor group, and a basic cell for mega-macro to explain an embodiment of the present invention, respectively. It is an enlarged view of a cell.

As shown in FIG. 1(a), a CMOS type LSI chip 1
A first MOS transistor group 2, a memory area 3, and a second MOS transistor group 5 are formed in the integrated circuit pattern area, and an I10 buffer and a bonding pad area 4 are formed in the outer periphery of the chip 1. be done. Also,
A mega/macro basic cell is formed in the first transistor group 2, and a chip basic cell 6 is formed in the second transistor group 5.

By the way, in the gate array method and standard cell method, which have been widely used in recent years, automatic placement and wiring are performed by a computer using function blocks prepared in advance. Therefore, the function plane used here usually has constant geometrical constants such as height and pitch. On the other hand, as miniaturization and higher integration progress, the functions that can be performed on a single chip are increasing, and the function blocks used within these chips are also becoming larger. These are called mega macros, and some implement all the functions of an 8-bit microcomputer or its peripheral chips.

This is because, as shown in FIG. 1(a), the internal wiring length is not so long because it is usually arranged concentratedly in a certain part of the chip (first transistor group 2). Therefore, each transistor 7 in the mega-macro does not need to have a large driving capacity, so it can sufficiently perform its function with a smaller size than the other transistors 6, which require consideration of wiring throughout the chip 1. .

In this way, the area of the chip 1 can be reduced by preparing two types of basic cells 6 and 7 with different driving capacities and using one for mega/macro and the other for chip. It also becomes possible to reduce power consumption. Further, by unifying the geometrical constants such as the height and pitch of the basic cells in each transistor group 2 and 5, it is possible to fully cope with CAD.

The size of the above-mentioned transistor is shown in Fig. 1(b).
) and (C), the second MOS transistor element 9 forming the basic self for mega/macro is formed smaller than the first MOS transistor element 8 forming the basic cell 6 for chip. [Effects of the Invention] As explained above, the CMOS type LSI of the present invention can implement mega-macro using the first transistor group whose dimension and functional shape are fixed to one type. By configuring another logic circuit with a second transistor group fixed to a dimension different from that of the first transistor group, low power consumption and high integration (low power consumption, high integration, Moreover, it has the advantage that automatic placement and wiring can be realized by a computer.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are a plan view of an 0MO8 type LSI chip, an enlarged view of a basic cell for a chip constituting each transistor group, and a mega・Enlarged view of basic cell for macro, Figure 2(a),
(b) is 0MO8 to explain a conventional example.
FIG. 2 is a plan view of a type LSI chip and an enlarged view of a gate array. 1...CM (') S-type LSI chip, 2...First transistor group (area), 3...Memory area, .'
ll10 buffer and pad region, 5... second transistor group (region), 6... basic cell for di-tube,
7... Mega/macro basic cell, 8, 9... Transistor element.

Claims (1)

[Claims] In a CMOS LSI in which a P-channel MOS transistor and an N-channel MOS transistor are formed on the same semiconductor substrate, dimensions such as channel length and channel width, and geometrical shapes of the P-channel MOS transistor and N-channel MOS transistor are determined respectively. A first MOS transistor group unified to one type, and a second MOS transistor group having transistor dimensions unified to different dimensions from the first MOS transistor group and whose geometrical shape is unified to one type. A CMOS type LSI characterized by providing two MOS transistor groups.