JPH06232267A - Method of designing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a designing method wherein it reduces the occupied area of an I/O cell for a logic LSI and it makes the multi-pin structure of an LSI package easy. CONSTITUTION:When I/O cells SL1, SL2,... constituting a buffer circuit for input/output on a semiconductor chip 1 are arranged and installed, a plurality of first basic cells 101, 102,... and second basic cells 201, 202,... are lined up and installed in prescribed regions on the chip. According to the number of transistors required to constitute desired I/O cells, one or two or more basic cells are selected from the plurality of basic cells, and I/O cell regions S1, S2,... are partitioned. By using elements inside the partitioned I/O cell regions S1, S2,..., a wiring pattern forming the I/O cells is designed. Bonding pads 2, 2,..., are formed on the chip 1 at a definite ratio with reference to the plurality of first and second basic cells, and a multi-pin structure can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology and a technology particularly effective when applied to a circuit design technology of a semiconductor integrated circuit device, for example, designing a buffer circuit for input / output of a gate array type logic LSI. Related to useful technology.

[0002]

2. Description of the Related Art In a gate array type logic LSI, an I / O cell which functions as an input buffer, an output buffer, a bidirectional buffer, etc., between a bonding pad and a logic cell forming an internal circuit. Is provided, whereby stable signal exchange between the LSI and other devices is performed. In the logic LSI, one I / O cell formation region (basic cell region) is determined corresponding to one bonding pad, and a plurality of transistors provided in this basic cell region are required in the wiring pattern. One I / O cell was formed by conducting conductive connection as much as possible. Conventional logical LS
A typical structure of an I / O cell is shown in FIG. As shown in this figure, the basic cell region (21, 22 ...) In which one I / O cell is formed is composed of an output MOS section and a pre-buffer section. , The same element pattern (basic pattern) is repeatedly arranged (in the illustrated example, the output MOS section is composed of six basic patterns 20a to 20f, and the pre-buffer section is composed of six basic patterns 20a 'to 20f'. ). The bonding pads 31, 32, ... Are provided in a ratio of one for each of the basic cell regions 21, 22 ,. In such an I / O cell layout pattern, the bonding pads 31 and 32 are provided at equal intervals, for example, in the peripheral portion of the chip regardless of the type (size) of the I / O cell, and are mounted on the lead frame side during mounting. Connection between the electrode portion and the bonding pad becomes easy.

[0003]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, the number of transistors actually used for designing an I / O cell depends on its function (for example, input buffer / output buffer / bidirectional buffer, high-speed / low-speed, etc.). /
The area required to form an O cell also differs. That is, FIG.
As shown in FIG. 3, the I / O cell (I / O cell SL ₁ formed in the region 21 is shown in the figure) is a part of the basic cell region (21), that is, the pattern 2 of the basic pattern.
Since some transistors provided in 0a to 20c and 20a 'to 20c' are formed only by conductively connecting them to each other by the wiring L20, there is an extra area in which an unused element remains in the basic cell area, The chip area is not being effectively used. This is a gate array type LSI
, The basic cell regions 21, 22 ... Are irrelevant to the size of the I / O cells actually formed,
This is because it is determined according to the I / O cell that occupies the largest area (the cell that has the largest number of transistors) (in the example of FIGS. 3 and 4, there are six basic patterns, and one I / O cell The output MOS section and the pre-buffer section are configured).

Therefore, on the semiconductor chip, both the output MOS section / pre-buffer section can be composed of two basic patterns I / O cells SL ₁ , and three can be composed I / O cells S.
As long as L ₂ and I / O cells SL ₃ that can be configured for 5 cells and I / O cells SL ₄ that can be configured for 6 cells are formed, they are shown in FIG. 3 regardless of the size of each cell. , The basic cell regions 21, 22, 2 having the basic patterns for six
Each I / O cell is formed in 3, 24 ..., and a large number of extra regions that are not involved in the configuration of the I / O cell exist.

Further, since it is necessary to make the basic cell region large in accordance with the maximum cell as described above, the number of bonding pads provided corresponding to this is limited, and the chip size is reduced. Product LSI without increasing
It was difficult to increase the number of pins. The present invention has been made in view of such circumstances, and a design of a semiconductor integrated circuit device that reduces an occupied area per I / O cell of a logic LSI and thus facilitates a multi-pin structure of an LSI package. Its main purpose is to provide a method.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, when arranging the I / O cells constituting the input / output buffer circuit on the semiconductor chip, the desired I / O is selected from a plurality of basic cells arranged in a predetermined region of the chip. One or more basic cells are selected according to the number of transistors required to form a cell, the I / O cell area is partitioned by the selected basic cells, and the I / O cell area partitioned in this way is selected. A wiring pattern for forming the I / O cell is designed by using the element.

[0007]

Since the size of the area where the I / O cell is formed can be determined according to the actual size of the cell, the extra area is reduced, and the I / O cell is provided in the peripheral portion of the chip. It can be arranged efficiently.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an enlarged view showing a peripheral portion of a semiconductor chip 1 in which a gate array type logic LSI to which the present invention is applied is formed, and FIG. 2 is a plan view showing a layout of the entire chip 1. As shown in these figures,
A large number of bonding pads 2, on the outer periphery of the chip 1.
2 ... Are provided at equal intervals. In the region inside (the lower side in FIG. 1) of the bonding pads 2, 2, ... An output MOS section (first buffer section) 3 is provided along the area.
Further inside, a pre-buffer section (second buffer section)
4 is provided at a predetermined distance d from the output MOS section 3. The output MOS section 3 and the pre-buffer section 4 are conductively connected to each other by the wirings L ₁ , L _2, ... And constitute an I / O cell having a desired function.

Specifically, the output MOS section 3 is provided with a large number of nMOS transistors forming an input protection circuit and a gate section for switching a signal transmission path. On the other hand, the prebuffer unit 4 has a large number of n-type MOSs.
A transistor or p-type MOS transistor is formed, and by changing the wiring pattern (not shown) in this part, any of an input buffer circuit, an output buffer circuit, and a bidirectional buffer circuit can be configured in the I / O cell. It is said that.

By the way, the I / O cell of this embodiment has a large number of basic cells (first basic cells) 101, 102, 103, 104 ... .. are formed by using elements such as transistors in a cell region formed by a combination of a large number of basic cells (second basic cells) 201, 202, 203, 204, ... Now, it is assumed that the first basic cell and the second basic cell are required to form six I / O cells having the largest area in the LSI chip. In the above-described conventional logic LSI design method, each basic cell area has a size capable of forming this maximum I / O cell (corresponding to six first basic cells and six second basic cells in FIG. 1). ), And one I / O cell was actually formed therein (FIGS. 3 and 4). On the other hand, the logical LS of this embodiment
In I, a basic cell is selected and an I / O cell is formed as follows according to the size of the I / O cell actually formed.

First, the I / O formed in the logic LSI
A cell area slightly larger than the average size of cells (for example, four first and fourth second basic cells) is defined as one basic cell group (indicated by a chain double-dashed line in the figure), and one cell group is provided. , One bonding pad 2, 2, ... Is arranged. Then, the I / O cell that is actually formed (S in FIG.
L ₁ , SL ₂ ...) According to the size of L ₁ , SL ₂ , ..., One or two or more adjacent basic cells are selected from the large number of basic cells 101, 102, 103 ,. ,
Regions (cell regions S ₁ , S _2, ...) Are divided for each I / O cell by the selected basic cell, and each I / O cell is formed by using elements such as transistors in the divided region. I designed the wiring pattern.

As an example, on the semiconductor chip 1, for example, an I / O cell SL ₁ which can be constituted by two first and second basic cells, and an I / O cell SL ₂ , 5 which can be constituted by three basic cells. Consider a case of sequentially forming I / O cells SL ₃ , ... At this time, the cell area S ₁ is divided by the first and second basic cells 101, 102, 201, 202, and the I / O cell S ₁ is formed by using the transistors in the cell area S ₁ . In addition, the first and second basic cells 104, 105, 10
The cell area S ₂ is divided by 6, 204, 205 and 206,
First and second basic cells 108 to 112, 208 to 212
In the cell area S ₃ to partition, constituting an I / O cell SL _2, SL ₃ using transistors in the cell region S _2, S ₃ each. Similarly, the cell region is divided according to the size of the I / O cell (for example, the number of transistors), and the elements in the cell region are connected by a desired wiring pattern to form the I / O cell. Then, the bonding pads 2, 2 ... and I /
The O cells are conductively connected in a one-to-one relationship by the wirings L11, L12, L13 .... By interposing the unused basic cell S ₀ between the I / O cells as described above, the power supply wiring can be separated between the cells.

When the I / O cell is constructed with such a layout, the element region which has not been involved in the construction of the I / O cell by the conventional method can be effectively utilized, and the input / output stages of the chip can be effectively used. High integration is achieved and the number of pins of the LSI is increased. The design efficiency is good if each of the first and second basic cells has the same pattern as the basic cells adjacent to each other, that is, the mirror-inverted pattern.

As described above, the logical LS of this embodiment is
In I, since the number of basic cells constituting an I / O cell is not fixed and can be appropriately selected according to the size of the I / O cell (for example, the number of transistors), the number of I / O cells The number of basic cells that do not contribute to the configuration is reduced. or,
The number of pads can be increased in anticipation of higher integration in the region where the I / O cells are formed, and the number of pins on the chip can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, one bonding pad is provided for each of the four basic cells, but according to the type and ratio of I / O cells installed on the LSI chip,
You may change these ratios. Further, in the present embodiment, an example in which the basic cell is divided into the output MOS section and the pre-buffer section is shown, but these may be combined to be simplified as one basic cell. Further, although the present embodiment has been described by taking a logic LSI in which the bonding pads are formed in the peripheral portion of the semiconductor chip as an example, the chip is not limited to this, and, for example, the bonding pads may be arranged with the logic cells aligned. The present invention can be applied to LSI chips scattered on the existing grid. In the above description, the case where the invention made by the present inventor is mainly applied to the design technology of the logic LSI which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be used in general design technology of semiconductor integrated circuit devices.

[0016]

The occupying area per I / O cell of the logic LSI is reduced, and the multi-pin structure of the LSI package becomes possible.

[Brief description of drawings]

FIG. 1 is a gate array type logic L to which the present invention is applied.
FIG. 6 is an enlarged view showing a peripheral portion of a semiconductor chip on which SI is formed.

FIG. 2 is a plan view showing an overall layout of a semiconductor chip.

FIG. 3 is an enlarged view showing a peripheral portion of a semiconductor chip on which a conventional gate array type logic LSI is formed.

FIG. 4 is a plan view showing a wiring pattern of an I / O cell formed in one basic cell of a conventional logic LSI.

[Explanation of symbols]

1 Semiconductor Chip 2 Bonding Pad 3 Output MOS Section 4 Pre-Buffer Section 101, 102, ... First Basic Cell 201, 202, ... Second Basic Cell S ₁ , S ₂ , S ₃ , S ₄ , ... Cell Area SL ₁ , SL ₂ , SL ₃ , SL ₄ , ... I / O cell

Claims (3)

[Claims] 1. When arranging an I / O cell constituting a buffer circuit for input / output on a semiconductor chip, a plurality of basic cells are arranged in a predetermined area of the chip, and the basic cell is arranged. From the basic cells, one or more basic cells are selected according to the number of transistors required to form the desired I / O cell, and the selected basic cells partition the I / O cell region. A method for designing a semiconductor integrated circuit device, wherein a wiring pattern for forming the I / O cell is designed by using elements in the partitioned I / O cell region. 2. The basic cell is divided into a first basic cell section composed of an nMOS transistor and a second basic cell section composed of an nMOS transistor and a pMOS transistor, and is formed. A method for designing a semiconductor integrated circuit device as described above. 3. The method for designing a semiconductor integrated circuit device according to claim 1, wherein bonding pads are provided on the chip at a constant ratio with respect to the plurality of basic cells.