JPS62179744A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To dispose input/output buffer cells on a corner not used so far by preparing the input/output buffer cells exclusively used at the corner of a semiconductor chip for the input/output buffer cells. CONSTITUTION:Input/output buffer cells 3 are disposed corresponding to external input/output pads 2 inside external input/output pads 2 provided on the peripheral side on a semiconductor chip 1 of an LSI of standard cell type. An exclusive input/output buffer cells 4 are disposed particularly at this corner. However, the characteristics are entirely the same as those of other input/output buffer cells 3. Thus, a semiconductor integrated circuit of standard cell type having exclusive input/output buffer cells which can be disposed in the dead space of the input/output buffer can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and in particular to standard
This invention relates to a cell type semiconductor integrated circuit.

[Conventional technology]

In recent years, the spread of large-scale semiconductor integrated circuits (hereinafter abbreviated as LSI) for office computers, terminal peripheral devices, control devices, etc. has been remarkable. These LSIs tend to be produced in large numbers and in small batches, and semi-customization using gate arrays has progressed in order to reduce manufacturing costs and shorten development periods. Recently, CA
Due to advances in D technology, gate arrays and other multifunctional LS
The standard cell system, which allows I to be integrated into a single chip, began to be used.

The standard cell system is a system in which a desired LSI is obtained by combining standard cells designed in advance. This is different from circuit wiring, such as a gate array, in which circuit wiring can be done using only a mask during the wiring process, and all masks are required for each chip, from cell placement to wiring, similar to a fully custom LSI. Therefore, the development cost and start-up period will be longer, but analog fist cells, memory and
It has features such as the ability to mount cells, making it possible to realize a more diverse range of systems on a single chip, and if it has the same functionality as a gate array, it can be realized on a much smaller chip, reducing manufacturing costs.

FIG. 2 is an example showing a plan view of a standard cell type semiconductor integrated circuit. FIG. 2 shows the semiconductor chip 11
The external input/output pad 12 and each input/output pad 12 are connected to each other. The input/output buffer 13 and the desired circuit are
Optimally laid out by the D system. Internal logic cells 15 are arranged. There are two types of standard cells: a polycell type and a building block type. In the former, the height direction of the cell is the same as in the gate array, but the width of the cell is different for each cell. The latter is a book in which each cell has a different height and width.

Here, the input/output buffer cell will be explained.

In a gate array, an input buffer cell and an output buffer cell are usually composed of one cell. In the standard cell, each of these cells is prepared as one cell, so the area of the buffer cell becomes small and a large number of buffers can be provided. In addition, depending on the shape of the internal cell area and the number of input/output lines, by selecting an appropriate block from among several types of blocks with different input/output buffer shapes, it is possible to reduce the excess area as much as possible. This leads to a reduction in chip size.

Figure 4 shows the layout of the standard cell type traffic buffer. Although the traffic buffer cells 22 are arranged on the four sides of the internal logic cell 21, the corners of the semiconductor chip have an unused area, that is, a dead space 23.

[Problem that the invention seeks to solve]

If the conventional standard cell input/output buffer cells mentioned above require many signal pins, the chip size is determined by the number and shape of the input/output buffer cells, regardless of the scale of internal gate usage. . Therefore, even if vertically long and horizontally long cells with the same characteristics are skillfully combined, there is a limit to the reduction in chip size, and furthermore, the corners of semiconductor chips are not used effectively.
There was dead space. Furthermore, when there are many input/output bins, the distance between the internal cells and the buffer cells often becomes long, resulting in a delay in operation speed.

The object of the present invention has been made in view of the above points, and is to provide a standard cell type semiconductor integrated circuit equipped with a dedicated input/output buffer cell that can be placed in the dead space of a human output buffer. It is in.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes an internal logic cell provided on a semiconductor chip, a plurality of input/output pads provided in a peripheral area on the semiconductor chip, and an input/output buffer cell connecting the internal logic cell and the input/output pads. A semiconductor integrated circuit comprising: a corner-dedicated input/output buffer cell disposed at a corner of a semiconductor chip;

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows an LSI using the stun gate e-cell system.
Input/output buffer cells 3 are arranged inside external input/output pads 2 provided on the periphery of semiconductor chip 1, corresponding to external output pads 2. In particular, dedicated input/output buffer cells 4 are arranged at the corners. However, the characteristics are exactly the same as other crowd buffer cells 3.

As shown in FIGS. 3(a) to 3(d), several types of input/output buffer cell groups A dedicated to corner portions are prepared.

These have the same characteristics but different shapes, and have the same function, but as shown in FIGS. 3(e) to (h), the input/output buffer cell group B has a different driving capacity from the input/output buffer cell group A. There is. Once the area of the internal cell region 50 is determined, a buffer with optimal shape characteristics can be obtained from the block cells shown in FIGS. 3(a) to 3(h). In selecting the optimal shape, other users and the number of output buffer cells to be used are taken into consideration. In other words, considering the number of output buffers required for external signals and the vertical and horizontal lengths of the internal logic cell area, input/output buffers other than the corner areas are
The cell is also selected from several types of buffer cells prepared in advance that have the same characteristics but different aspect ratios, so that the chip area can be reduced as shown in FIG. In this case, the user can design in the same way as before, and there is no need for a large degree of freedom in design.

Further, even when there are many input/output pins, there is no distance between the internal logic cell and the output buffer cell, which is advantageous in terms of operation speed.

〔Effect of the invention〕

As described above, according to the present invention, it is not necessary to prepare a human output buffer cell exclusively for the corner portion of a semiconductor chip for the human output buffer cell. In particular, when the ratio of external signal pins is high, the effect of reducing the chip area is large, which reduces manufacturing costs and improves productivity. It has the effect of increasing Moreover, it is advantageous in terms of speed.

[Brief explanation of drawings]

FIG. 1 is a plan view of a chip laid out using corner-dedicated input/output buffer cells according to an embodiment of the present invention;
Figure 2 is a plan view of a chip laid out using only conventional outflow buffer cells, and Figures 3 (al, (b), (
C) and (d) are plan views showing an example of corner-dedicated input/output buffer cells with the same characteristics but different shapes; FIG. 3(e)
, (f), (trout, and (h) are respectively shown in Fig. 3 (a) and (b).
), (C), and (d), and a plan view showing an example of a corner dedicated input/output buffer cell with the same characteristics and a different shape. FIG. 5, a layout diagram showing the relationship with the output buffer cell, shows the relationship between the internal cell area and the input/output buffer when the corner dedicated block of the present invention is used in the same internal logic cell area as in FIG. 4. It is a layout diagram. 1.11...semiconductor chip, 2,12...
・・Input/output buffer cell)', 3.13.22・・・・・・・・・・Passenger buffer cell, 4・・・Corner dedicated input/output buffer cell, 5, 15° 25・・・・・・Internal logic cell, 14.23 ... Dead space. Shiba 2

Claims (2)

[Claims] (1) An internal logic cell provided on a semiconductor chip, a plurality of input/output pads provided on the periphery of the semiconductor chip, and an input/output buffer cell connecting the internal logic cell and the input/output pad. 1. A semiconductor integrated circuit comprising: a corner-dedicated input/output buffer cell arranged at a corner of a semiconductor chip among the input/output buffer cells. (2) The semiconductor integrated circuit according to claim 1, wherein the corner-dedicated input/output buffer cell is a cell having a plurality of shapes and a plurality of characteristics.