JPH11233636A - Semiconductor integrated circuit device and its layout designing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its layout designing method that are able to reduce the restrictions in an automatic layout designing using a CAD system, and also is able to improve integrated density of an overall IC chip. SOLUTION: An IC chip 10 is constituted of pads part 11a-11j, that are connected to package pins 21a-21g that connect electrically an inner part and an outer part of the package 20 via a bonding wires, a functional region 13 that is provided an inside region of the chip 10 excluding a peripheral region of the chip where the pads part 11a-11j are provided, I/O cells 12a, 12c, 12g, 12h provided in arbitrary positions inside of the functional region 13, a macro cell 13a of RAM, ROM etc., and a functional cell region 13b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a layout design method thereof, and more particularly, to an application specific IC, that is, an ASIC (Application Specific I / O).
C) The arrangement structure and method of the input / output unit in C).

[0002]

2. Description of the Related Art With the rapid development and spread of information communication devices in recent years, there is an extremely strong demand for high integration and high functionality of LSIs mounted on those devices. In particular, AS that can design functions according to user needs
In an IC, it is necessary to set various input / output interfaces according to functions to be realized in one chip.

A conventional macro embedded cell array type L
The SI will be described with reference to FIGS. In FIG. 5, an input / output area 11 for inputting / outputting a signal to / from the outside of the IC chip 10 is provided in a peripheral area of the IC chip 10, that is, on four sides, and the entire area inside the IC chip 10 excluding the input / output area 11 is provided. Is provided with a functional region 13.
In the functional area 13, for example, a large number of uniform basic cells and macro cells 13a such as a RAM, a ROM, and a multiplier are arranged, and the basic cells are connected to each other by wiring to realize a desired function according to the needs of the user. Basic cell area 1
3b is provided.

[0004] As described above, an LSI in which a macro cell configured to have a predetermined function in advance in a functional area is arranged at an arbitrary position is generally used in a macro-embedded cell array system or an Embert array system. It is referred to as an LSI, and has a different configuration and a layout design method from an LSI of a gate array system in which a functional area includes an array of only basic cells.

The input / output area 11 provided in the peripheral area of the IC chip 10 is, as shown in FIG.
Pad portions 11a to 11f connected via bonding wires to package pins 21a to 21d provided on a package 20 on which the chip 10 is mounted, and input / output buffer cells (hereinafter, referred to as "adjacent") adjacent to these pad portions 11a to 11f. , I / O cells) are provided.

Next, the above-described LSI layout design method will be described with reference to the flowchart of FIG. First, a database for layout design is created based on information on a logical function desired by the user (S2).
1, S22). Here, the logic function information used for creating the database includes the package pins 21a to 21f.
It contains information such as the assignment and arrangement of logical functions to the.

Next, a chip size is selected from a library based on information on the number of basic cells mounted on the IC chip, the specifications of macro cells such as RAM and ROM, and the specifications of the package, and the entire layout within the chip size is selected. The region and the wiring region are determined (S23). Further, a region adjacent to the pad portion in the chip peripheral region is defined as an I / O cell placement region from the placement region and the wiring region (S2).
4) A macro cell and a basic cell area are arranged in an arrangement area other than the I / O cell arrangement area (S25).

In the I / O cell arrangement area,
The arrangement of the corresponding I / O cells is determined based on the logical function (pin information) assigned to the package pin. At this time, the type of the I / O cell is recognized based on the logic function information, and a layout pattern corresponding to the type is selected from the layout library. That is, LS
With the advancement of functions of I, the driving capability required in the functional area has been diversified, so it is necessary to provide I / O cells corresponding to each functional cell.

The processing of arranging a functional cell such as a macro cell or a basic cell in a functional area is performed by a layout library in order to realize a logical function desired by a user.
This is performed by selecting and arranging macro cells such as M and ROM, and connecting and wiring the basic cells. The above processes are automatically executed by setting logical function information and other various conditions in a layout design work on a CAD (Computer Aided Design) system.

By the way, in the above-mentioned cell array type LSI, usually, the number of pins and the logic function which can be realized by one IC chip have a certain width. For example, if the number of package pins desired by the user is wide, such as 100 to 300 pins, an IC having 300 pads is required.
If a chip is used and the number of package pins is less than 300, the pad portion is not used and is handled. Therefore, the same IC chip can be mounted on packages having different numbers of pins.

[0011]

An LSI as described above
In, an LSI having a desired logic function can be realized with a small number of IC chips, but the I / O cell arrangement area corresponds to the maximum number of package pins (for example, 300 pins) in the chip size. Since the number of package pins actually set is smaller, the unused area in the I / O cell arrangement area becomes wider, and the integration density is significantly reduced as compared with the functional area. was there.

Conventionally, in order to improve such a problem,
The following method was adopted. A method of laying out an I / O cell arrangement region in accordance with the number of package pins and reducing the occupied area. Specifically, in an IC chip having a specific chip size, the number of package pins to be set is monitored. For example, when the number of pins is less than half of the maximum number of pins, FIG.
As shown in FIG. 8B, the layout pattern (vertical direction L, horizontal direction W) 12p of the basic unit area set assuming the maximum pin number as shown in FIG. The I / O cell arrangement area 12 is reduced by adopting a pattern 12p 'having a size of 1/2 and a horizontal size of 2 times.

[0013] As described above, since the number of elements required by a predetermined I / O cell, that is, the area, is determined, it is necessary to change the aspect ratio of the shape so as to maintain a constant area. Because you can. The specifications of the I / O cells serving as the basic unit are set to those corresponding to the standard driving capability, so that the occupied area of each I / O cell is reduced and the occupied area of the entire I / O cell arrangement area is reduced. how to.

Generally, various specifications are prepared for the I / O cell according to the driving capability. Since the driving capability is correlated with the number of elements required by the I / O cell, that is, the area of the I / O cell, as shown in FIG. 6, the most frequently used power type, for example, an I / O of 2 mA A region corresponding to the cell 12a is defined as a basic unit region 12x, and the I / O cell arrangement region 12
Is defined, the entire I / O cell arrangement area is reduced.

In this case, when the IC chip is used with the maximum number of pins of the chip size, the I / O cell 12a having a driving capability of 2 mA or less can be used, and the number of pins is smaller than the maximum number of pins. In such a case, for example, a 4 mA I / O cell 12b occupying twice the area of the basic unit area 12x can be used by utilizing an adjacent unused area.

According to the above-described method, it is necessary to re-layout the I / O cell arrangement area according to the set number of package pins. Therefore, a plurality of pattern versions are prepared for one chip size. However, there is a problem that the burden is increased in both software and hardware. According to the above method, it is necessary to monitor an unused area in the I / O cell arrangement area according to the set number of package pins. However, there is a problem that the types of power types that can be used are limited.

The present invention solves the above problems, reduces the restrictions in automatic layout design using a CAD system, and improves the integration density of the entire IC chip, and a layout design method therefor. The purpose is to provide.

[0018]

According to a first aspect of the present invention, there is provided a pad provided in a peripheral area of a chip for inputting and outputting signals to and from the outside of the chip.
A functional region provided in the entire area of the chip except for the pad portion, and a macrocell configured to have at least a desired function in advance, and input / output from the outside of the chip via the pad portion An input / output buffer cell for transmitting a signal to the functional area is disposed at an arbitrary position in the functional area.

According to a second aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein:
It is characterized in that a large number of uniform basic elements are arranged, and the basic elements are connected to each other by wiring to realize an arbitrary function. According to the first or second aspect of the present invention, the entire area inside the chip peripheral area where the pad section is provided is defined as a functional area, and at any position in the functional area,
Since macro cells such as RAMs and ROMs and I / O cells are arranged, the occurrence of unused areas is reduced as compared with the case where I / O cells are arranged only in the conventional I / O cell arrangement area. Thus, the integration density of the entire chip can be improved, and the I / O cell can be arranged near the corresponding function cell, so that the desired logic function can be realized well.

According to a third aspect of the present invention, there is provided a pad provided in a peripheral region of a chip for inputting / outputting a signal to / from the outside of the chip, and provided inside the chip adjacent to the pad. An input / output section arrangement area in which an input / output buffer cell for inputting / outputting a signal from the outside of the chip via a pad section is provided. Functional areas,
In the semiconductor integrated circuit device having the above, a macro cell for realizing an arbitrary function or a large number of uniform functional elements in an unused area where the input / output buffer cell is not arranged in the input / output section arrangement area Are arranged.

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the third aspect, wherein the semiconductor integrated circuit device is a macro-embedded cell array type integrated circuit device, and A macrocell configured to have a desired function, and an element region configured to realize an arbitrary function by wiring and connecting a large number of uniform basic elements arranged in advance. I have.

According to the third or fourth aspect of the present invention, the I / O
A functional cell such as a macro cell or a basic cell can be arranged in an unused area where an I / O cell is not arranged in the O cell arrangement area and used as a functional area. And the integration density of the chip can be improved. That is, similarly to the above-described invention, the entire area inside the chip peripheral area where the pad section is provided is treated as a functional area, and the I / O cell arrangement area is conveniently located adjacent to the pad section. The I / O cell is defined and the area where the I / O cell is not disposed (unused area) is used as a functional area to improve the integration density.

According to a fifth aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit device in which a predetermined number of pad portions are provided in advance in a chip peripheral region, wherein a desired logic function required for the semiconductor integrated circuit device is provided. On the basis of,
A process of determining the number of input / output pins and defining a functional area in the whole area inside the chip excluding the peripheral area; a macro cell as a functional cell configured to have a desired function in advance; An input / output buffer cell of an arbitrary shape that transmits a signal input / output from the outside of the chip via the pad portion, corresponding to the logic function set for each, and an arbitrary position in the functional area. And arranging processing.

According to a sixth aspect of the present invention, in the layout design method of the semiconductor integrated circuit device according to the fifth aspect, the input / output buffer cell is treated as a kind of the function cell, and another input / output buffer cell is provided in the function area. It is characterized in that it is arranged mixedly with the function cell. Claim 5 or 6
According to the described invention, the entire area inside the chip peripheral area where the pad portion is provided is treated as a functional area, and macro cells such as RAM and ROM and I / O cells are arranged at arbitrary positions in the functional area. Therefore, the layout position of the I / O cells can be freely and quickly determined without being restricted by the layout of the conventional I / O cell layout area, and the degree of freedom in layout design can be increased. Can be improved.

Further, by handling the I / O cells in the same manner as other function cells, layout design on a CAD system can be easily performed.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic concept of the present invention will be described with reference to FIG. As described above, the semiconductor integrated circuit device (hereinafter, referred to as LSI) according to the present invention
As shown in FIG. 1, the entire area with a hatched area inside the pad area 11x arranged at a predetermined pitch in the peripheral area of the IC chip 10 is treated as the functional area 13, and the RAM, It is characterized in that I / O cells are arranged together with macro cells and basic cells such as ROM.

That is, the entire area excluding the pad portion inside the IC chip is treated as a functional area, and the I / O cell is treated as one of the functional cells, without providing an I / O cell arrangement area previously provided in the past. Are arranged at an arbitrary position in the function area so as to be mixed with other function cells, that is, macro cells and basic cells. According to such a configuration, the entire area excluding the pad portion inside the IC chip can be used as a functional area, and the I / O cell can be arranged at an arbitrary position in the functional area.
An unused area is not generated in the cell arrangement area, and an LSI in which the integration density of the entire chip is improved is realized.

Further, as shown in the prior art, there is no restriction in the I / O cell arrangement region provided adjacent to the pad portion. Is not affected by other I / O cells, so that restrictions on I / O cell placement processing are reduced,
A quick and flexible layout design method is realized.

[0029]

Next, a first embodiment of the LSI according to the present invention will be described with reference to FIG. In FIG. 2, an IC chip 10 mounted in a package 20 includes pad portions 11a to 11j connected via bonding wires to package pins 21a to 21g for electrically connecting the inside and the outside of the package 20; Parts 11a to 11j
A functional region 13 provided in an internal region of the IC chip 10 excluding a chip peripheral region provided with I / O cells 12a, 12c, 12g, and 1 provided in the functional region 13
2h, a macro cell 13a such as a RAM and a ROM, and a functional cell area 13b. The illustration of the wiring formed in the functional region 13 is omitted.

The I / O cells 12a, 12c, 12g, 12
h is the package pins 21a, 21b, 21e, 21f
11a, 11c, 11g, 11h connected to
And is arranged inside the functional region 13 in an arbitrary shape and at an arbitrary position. Here, the I / O cell 12
The shapes of a, 12c, 12g, and 12h are set so as to have a predetermined area according to the driving ability set based on the logic function required for the LSI. On the other hand, the arrangement position is set at an arbitrary position in the functional area 13. For example, in the case of an I / O cell for transmitting a signal to a macro cell, a good logical operation can be achieved by arranging the I / O cell in the vicinity thereof. Is realized.

Next, a layout design method for realizing the LSI of the first embodiment will be described with reference to the flowchart of FIG. First, a layout design database is created based on information on a logical function desired by a user, as in the case shown in FIG. 7 as a conventional technique (S11, S12).

Next, a chip size is selected from a library based on information on the number of basic cells mounted on the IC chip, the specifications of macro cells such as RAM and ROM, and the specifications of the package, and the entire layout within the chip size is selected. A region and a wiring region are determined (S13). Then, the I / O cell is arranged in the arrangement area together with the macro cell and the basic cell area (S25).

At this time, the type of the I / O cell is recognized based on the logical function information assigned to the package pin, and a layout pattern corresponding to the type is selected from the layout library. , With a driving capability corresponding to the function cell transmitting the signal. In particular, by treating an I / O cell as one of functional cells such as a macro cell and a basic cell provided in a functional area,
The macro cells such as RAM and ROM are selected and arranged from the layout library, and the I / O cells are arranged by the same processing as the case where the basic cells are interconnected.

Each of the above processes is automatically executed by setting logic function information and other various conditions in a layout design work on a CAD system. Next, a second embodiment of the LSI according to the present invention will be described with reference to FIG.

In FIG. 4, the IC chip 10 mounted in the package 20 has a package pin 2 for electrically connecting the inside and the outside of the package 20 as in the conventional configuration.
Pad portions 11a to 11f connected to 1a to 21d,
Functional area 1 provided in an internal area of IC chip 10 excluding a chip peripheral area provided with pad portions 11a to 11f
3 and I / O provided for convenience within the functional area 13
And a cell arrangement region 12. In addition,
The illustration of the macro cell and the basic cell arranged together with the I / O cell in the functional area 13 is omitted.

I / O cell arrangement area 1 provided for convenience
2, I / O cells 12a, 12c, 12d, and 12e connected to the pads 11a, 11c, 11d, and 11e connected to the package pins 21a to 21d. In this case, in the I / O cell arrangement area 12,
I / O cells 12a or 12c, 12e
Although unused areas 12y and 12z in which the O cells are not arranged are generated, the I / O cell arrangement area 12 of the present embodiment is provided in the functional area 13 for convenience, so that the unused area is basically the unused area. By arranging a functional cell such as a cell or a macro cell, generation of an unused area is prevented, and the number of mounted elements is increased, thereby increasing the integration density of the entire IC chip.

Since such an LSI layout design method treats the entire area inside the IC chip inside the pad section including the I / O cell arrangement area as a functional area, the flowchart shown in FIG. It has a similar procedure. Here, since the I / O cell arrangement area is defined for convenience, it is not necessary to create an I / O cell arrangement area as a procedure, and the I / O cell shown in the first embodiment is used.
It can be considered that an arbitrary position where the cell is arranged is the edge of the functional region 13.

Next, the integration density of the LSI according to the present invention and the conventional configuration will be described with reference to FIGS. In order to simplify the comparison and verification of the integration density, in FIG. 6, the area occupied by one basic cell in the unit region 12x defined in the I / O cell placement region 12 is set to 1,
It is assumed that the occupied area of the / O cell is approximately 50 times as large.

As shown in FIG. 4, the package pins 21a
Is smaller than the number of pad portions 11a to 11f provided in advance on the IC chip 10, for example,
When the four package pins 21a to 21d are connected to the four pad portions 11a, 11c, 11d, and 11e, the pad portions 11b and 11f become unused, and the number of pad portions corresponding to the four package pins is six. Individual. In the case of an LSI having 100 package pins,
The number of pad portions required for the C chip is 100/4 × 6 = 150 (1).

When the pad portion is provided in one-to-one correspondence with a unit region for arranging I / O cells,
An I / O cell arrangement area having the same number of unit areas as the pad section is required. However, since two of the six unit areas are unused areas, an area equivalent to 50 of 1/3 of the 150 I / O cell arrangement areas is unused.

When this is converted into the number of basic cells, the area occupied by one I / O cell is equivalent to 50 basic cells. Therefore, when the unused area is replaced by the basic cells, 50 × 50 = 2500 (2), and the unused area can be used as a new functional area for 2500 basic cells.

According to the present invention, since this unused area is included in the functional area, a functional cell such as a basic cell or a macro cell can be arranged at the time of layout design, and the integration density is greatly improved as compared with the conventional structure. Can be realized.
In the above-described verification, the LSI shown as the second embodiment was compared with the conventional configuration in order to simplify the comparison and verification of the integration density. Even when I / O cells are arranged at arbitrary positions in the area, there is no substantial difference in the number of basic cells that can be newly used or the area of the functional area.

As described above, according to the present invention, it is possible to arrange an I / O cell as one of the functional cells at an arbitrary position in the functional area without defining the I / O cell arrangement area. Therefore, restrictions on the layout design of the I / O cells can be reduced, the development period can be shortened and shared, and the integration density of the entire chip can be improved.

Language description in layout design,
That is, in the description at the transistor level, the I / O cell provided in the LSI to be designed can be treated as one of the function cells, so that the language description can be simplified, and the I / O by the user can be simplified. The layout design of the / O cell can be made possible. Note that the above-described LSI layout design method can be provided by being stored in a storage medium such as a floppy disk or a CD-ROM, and can be used as a unified design method in a CAD system.

[0045]

As described above, according to the semiconductor integrated circuit device of the first or second aspect, the entire area inside the chip peripheral area where the pad portion is provided is defined as the functional area, and any area within this functional area is defined. Since macro cells such as RAM and ROM and I / O cells are arranged at the positions, unused areas are compared with the case where I / O cells are arranged only in the conventional I / O cell arrangement area. Can be prevented, the integration density of the entire chip can be improved, and I / O cells can be arranged in the vicinity of the corresponding function cells, so that a desired logic function can be realized well. it can.

According to the semiconductor integrated circuit device of the third or fourth aspect, the function of a macro cell, a basic cell, or the like is provided in an unused area of the I / O cell arrangement area where no I / O cell is arranged. Since a cell can be arranged and used as a functional region, the area that can be used as a functional region can be increased, and the integration density of a chip can be improved. That is, as in the first or second aspect of the present invention, the entire area inside the chip peripheral area where the pad section is provided is treated as a functional area, and I
I / O cells are arranged by defining a / O cell arrangement area, and I / O cells are arranged.
The area where the O cell is not arranged (unused area) is used as a functional area to improve the integration density.

Further, according to the layout design method of the semiconductor integrated circuit device according to the fifth or sixth aspect, the entire area inside the chip peripheral area where the pad portion is provided is treated as a functional area, and an arbitrary position in this functional area , RAM,
Since macro cells such as ROMs and I / O cells can be arranged, the I / O cells can be arranged freely and quickly without being restricted by the layout of the conventional I / O cell arrangement area. And the degree of freedom in layout design can be improved.

Further, by treating the I / O cells in the same manner as other functional cells, layout design on a CAD system can be easily performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic concept of an LSI according to the present invention.

FIG. 2 is a diagram showing a first embodiment of an LSI according to the present invention.

FIG. 3 is a flowchart showing an LSI layout design method according to the present invention.

FIG. 4 is a diagram showing a second embodiment of the LSI according to the present invention.

FIG. 5 shows a conventional macro embedded cell array type LSI.
FIG.

FIG. 6 is a main part detailed diagram showing an I / O area in a conventional LSI.

FIG. 7 shows a conventional macro embedded cell array type LSI.
9 is a flowchart showing a layout design method of FIG.

FIG. 8 is a diagram showing a method of re-layout of an I / O cell arrangement area in a conventional LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 IC chip 11 I / O area 11a-11j Pad part 11x pad area 12 I / O cell arrangement area 12a-12h I / O cell 12p, 12p 'Layout pattern 12x Unit area 12y, 12z Unused area 13 Functional area 13a Macro cell 13b Basic cell area 20 Package 21a-21g Package pin

Claims (6)

[Claims] A pad portion provided in a peripheral region of the chip for inputting / outputting a signal to / from the outside of the chip; and a functional region provided throughout the chip except for the pad portion. A macro cell configured to have a desired function in advance, and an input / output buffer cell for transmitting a signal input / output from outside the chip to the function area via the pad portion, at an arbitrary position in the function area. A semiconductor integrated circuit device, wherein 2. The device according to claim 1, wherein a number of uniform basic elements are arranged in the functional area, and the basic elements are connected to each other by wiring to realize an arbitrary function. 13. The semiconductor integrated circuit device according to claim 1. A pad portion provided in a peripheral region of the chip for inputting / outputting a signal to / from the outside of the chip; and a pad portion provided inside the chip adjacent to the pad portion and via the pad portion. Comprising an input / output unit arrangement area in which an input / output buffer cell for inputting / outputting a signal from / to the chip and a functional area provided inside the chip excluding the pad unit and the input / output unit arrangement area In the integrated circuit device, a macro cell for realizing an arbitrary function or a number of uniform functional elements is arranged in an unused area where the input / output buffer cell is not arranged in the input / output section arrangement area. And a semiconductor integrated circuit device. 4. The semiconductor integrated circuit device is a macro-embedded cell array type integrated circuit device, wherein the functional area includes a macro cell configured in advance to have a desired function and a plurality of pre-arranged macro cells. 4. An element region configured so as to realize an arbitrary function by wiring and connecting uniform elementary elements to each other.
13. The semiconductor integrated circuit device according to claim 1. 5. A layout design method for a semiconductor integrated circuit device in which a predetermined number of pad portions are provided in a chip peripheral region in advance, wherein the number of input / output pins is determined based on a desired logic function required for the semiconductor integrated circuit device. And a process of defining a functional area in the whole area inside the chip except for the peripheral area; a macro cell as a functional cell configured to have a desired function in advance; and An input / output buffer cell of an arbitrary shape that transmits a signal input / output from outside the chip via the pad portion, in accordance with the logic function, and a process of arranging the input / output buffer cell at an arbitrary position in the functional region. And a layout design method for a semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein said input / output buffer cell is treated as a kind of said function cell, and is arranged in said function area while being mixed with another function cell. Layout design method.