TWI540724B - High voltage metal-oxide-semiconductor transistor device - Google Patents

Description

High voltage MOS transistor

The invention relates to a high voltage metal-oxide-semiconductor (hereinafter referred to as HV MOS) transistor component, in particular to a high voltage lateral double-diffused metal-oxide-semiconductor. , HV-LDMOS) transistor components.

Among power components with high-voltage processing capability, double-diffused MOS (DMOS) transistor components continue to receive attention. Common DMOS transistor components are vertical double-diffused MOS (VDMOS) and lateral double-diffused metal oxide semiconductor (LDMOS) transistor components. LDMOS transistor components are widely used in high-voltage operating environments due to their high operating bandwidth and operating efficiency, as well as planar structures that are easily integrated with other integrated circuits, such as CPU power supply (CPU power). Supply), power management system, AC/DC converter, and high-power or high-band power amplifiers. The main feature of the LDMOS transistor component is that it has a low doping concentration and a large area of lateral diffusion drift region, the purpose of which is to alleviate the high voltage between the source terminal and the drain terminal, thereby enabling a higher breakdown of the LDMOS transistor component. Voltage (breakdown Voltage).

Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a conventional HV-LDMOS transistor device. As shown in FIG. 1, a conventional HV-LDMOS transistor element 10 is disposed on a semiconductor substrate 12 having a P-well 20, a source 14 disposed in the P-well 20, and a high concentration. P-doped region 22, a gate 16 and a drain 18. The drain 18 is a high concentration N-type doped region and is disposed in an N-type well 30. The N-type well 30, that is, the aforementioned drift region, whose doping concentration and length affect the breakdown voltage and ON-resistance (R _ON ) of the HV-LDMOS transistor element 10. The gate 16 of the HV-LDMOS transistor component 10 is disposed on a gate dielectric layer 40 and extends over the field oxide layer 42.

Since the two main characteristics pursued by HV MOS transistor components are low on-resistance and high breakdown voltage, and these two requirements are conflicting with each other, it is difficult to balance. Therefore, there is still a need for a solution that can operate normally in a high voltage environment while satisfying both low on-resistance and high breakdown voltage.

Accordingly, it is an object of the present invention to provide an HV MOS transistor element having low on-resistance and high breakdown voltage.

According to the patent application scope provided by the present invention, an HV MOS is provided The HV MOS transistor device includes a substrate, a gate disposed on the substrate, a drain region and a source region respectively disposed on the substrate on opposite sides of the gate, and a setting a first isolation structure below the gate. It is worth noting that the gate is completely overlapped with the first insulating structure.

According to the patent application scope provided by the present invention, there is further provided an HV MOS transistor device, the transistor device comprising a substrate, a gate disposed on the substrate, a plurality of drift regions formed in the substrate, and a plurality of a first insulating structure formed in the substrate. The gate extends in a first direction, the drift regions are aligned along the first direction, and the first insulating structures are also aligned along the first direction. Each of the first insulating structures extends in a second direction, and the second direction is perpendicular to the first direction. In addition, the gate portion covers each of the drift regions and portions of the first insulating structures, and the drift regions under the gates and the first insulating structures are staggered with each other along the first direction.

According to the HV MOS transistor of the present invention, a first insulating structure completely overlapped with the gate is provided under the gate, and the breakdown voltage is increased without increasing the on-resistance.

Please refer to FIG. 2 to FIG. 4 , wherein FIG. 2 is a partial layout diagram of the first preferred embodiment of the HV MOS transistor component provided by the present invention, and FIG. 3 to FIG. 4 are respectively FIG. A schematic cross-sectional view of the middle edge A ₁ -A ₁ ' and B ₁ -B ₁ 'tangent. As shown in FIG. 2 to FIG. 4, the HV MOS transistor element 100 provided in the preferred embodiment is disposed on a substrate 102, such as a substrate. The substrate 102 has a first conductivity type, which in the preferred embodiment is p-type. The HV MOS transistor device 100 provided in the preferred embodiment includes a gate 120 disposed on the substrate 102 and including a drift region 106 in the substrate 100. The drift region 106 includes a second conductivity type, and the second conductivity pattern is complementary to the first conductivity pattern. Therefore, in the preferred embodiment, the second conductivity type is n-type, and the drift region 106 It is an n-type drift region. In the drift region 106, a base region 108 is formed, and the substrate region 108 includes a first conductivity type, and thus is a p-type substrate region. In the substrate 102 on both sides of the gate 120, a source region 110 and a drain region 112 are respectively disposed, and the source region 110 and the drain region 112 both include a second conductivity type, so the n-type source region is With n-type bungee area. Further, as shown in FIGS. 3 and 4, the source region 110 is disposed in the p-type body region 108, and the drain region 112 is disposed in the n-type drift region 106. In addition, in the p-type body region 108, a p-type doping region 114 complementary to the n-type source region 110 is further disposed, and the p-type doping region 114 is electrically connected to the n-type source region 110. It is also worth noting that in FIG. 2, the spatial relative relationship of certain constituent elements is emphasized, and the n-type source region 110, the n-type drain region 112, the p-type base region 108, and the like are not illustrated. The p-type doping region 114 and the like constitute elements, but those skilled in the art should be able to easily know the formation positions of the above-described constituent elements according to the disclosures of FIGS. 3 and 4, so the spatial relationship of the constituent elements is no longer Narration.

Please also refer to Figures 2 to 4. The gate 120 of the HV MOS transistor device 100 provided in the preferred embodiment includes a gate conductive layer 122, a gate dielectric layer 124, and a sidewall spacer 126 formed on the sidewall of the gate conductive layer 122. And as shown in FIG. 2, is provided on the gate electrode 120 on the substrate 102 a line extending in a first direction D _1. In addition, a plurality of shallow trench isolation (STI) 104 for providing electrical isolation between the HV MOS transistor component 100 and other semiconductor components is further disposed in the substrate 102. It should be noted that the HV MOS transistor component 100 provided by the preferred embodiment further includes a plurality of insulating structures 130, such as a plurality of STIs. As shown in FIG. 4, one of the insulating structures 130 may have a depth equal to the depth of the STI 104, but is not limited thereto. The insulating structures 130 are parallel to each other and extend in a second direction D ₂ , and the second direction D ₂ is interlaced with the first direction D ₁ as shown in FIG. 2, preferably perpendicular to each other. More importantly, the insulating structure 130 is interposed in the n-type drift region 106. Therefore, where the gate 120 passes, a pattern in which the n-type drift region 106 and the plurality of insulating structures 130 are alternately arranged is formed, and the n-type drift region 106 and insulating structure 130 along the first direction D ₁ lines staggered. In other words, a gate line 120 cover the n-type drift region portion 106 and the insulating portion of each structure 130, 120 and the drift region beneath the gate 106 and the first insulating structure of 130 lines along the first direction D ₁ are arranged interleaved with one another. As shown in FIG. 2, in the preferred embodiment, the insulating structure 130 under the gate 120 has the same width as the n-type drift region 106, but is not limited thereto. The insulating structure 130 and the STI 104 can be simultaneously fabricated, but are not limited thereto.

As can be seen from FIGS. 2 to 4, an n-type drift region 106 (and a portion of the p-type base region 108 formed therein) and the insulating structure 130 are alternately formed under the gate 120. As shown in FIG. 4, when the underlying gate 120 is formed as an insulating structure 130, the gate conductive layer 122 and the gate dielectric layer 124 of the entire gate structure are completely overlapped with the insulating structure 130 as shown in FIG. . In other words, the gate 120 is completely disposed within the area of the insulating structure 130, so that portions of the channel region that would otherwise be formed are now fully occupied by the insulating structure 130. However, when the underlying formation of the gate 120 is the n-type drift region 106 and the partial p-type base region 108 as shown in FIG. 3, the channel region 128 can still be retained, and current can be ensured via the n-type drift region 106. The channel region 128 reaches the source region 110 from the drain region 112 and achieves a voltage drop in this path. More importantly, since the insulating structures 130 are disposed on both sides of the n-type drift regions 106 as shown in FIG. ₂ in the parallel second direction D ₂ , the electric field of the n-type drift region 106 can be alleviated. Increase the purpose of the breakdown voltage. In addition, since the corner of the p-type base region 108 (as indicated by the circle C in FIG. 3) is the most fragile pn junction, the depth of the insulating structure 130 is preferably larger than the p-type base region. The depth of 108 is such that the corner C of the p-type base region 108 is sandwiched from both sides to reduce the electric field thereof, and the HV MOS transistor element 100 is prevented from collapsing at the corner C of the p-type base region 108.

Therefore, the HV MOS transistor element 100 according to the first preferred embodiment reduces the electric field of the n-type drift region 106 by the n-type drift region 106 and the insulating structure 130 staggered under the gate 120. Successfully increase the breakdown voltage without increasing the on-resistance.

Please refer to FIG. 5 to FIG. 7 , wherein FIG. 5 is a partial layout diagram of a second preferred embodiment of the HV MOS transistor component provided by the present invention, and FIG. 6 to FIG. 7 are respectively 5th. A schematic cross-sectional view taken along the line A ₂ -A ₂ ' and B ₂ -B ₂ ' in the figure. As shown in FIG. 5 to FIG. 7, the HV MOS transistor element 200 provided in the preferred embodiment is disposed on a substrate 202. The substrate 202 has a first conductivity type, which in the preferred embodiment is also p-type. The HV MOS transistor device 200 provided in the preferred embodiment includes a gate 220 disposed on the substrate 202 and including a drift region 206 in the substrate 200. The drift region 206 includes a second conductivity type, and the second conductivity pattern is complementary to the first conductivity type. Therefore, in the preferred embodiment, the second conductivity type is also n-type. In the n-type drift region 206, a matrix region 208 is formed, and the substrate region 208 includes a first conductivity type, and thus is a p-type substrate region. In the substrate 202 on both sides of the gate 220, a source region 210 and a drain region 212 are respectively disposed, and the source region 210 and the drain region 212 both include a second conductivity type. Further, as shown in FIGS. 6 and 7, the source region 210 is disposed in the p-type body region 208, and the drain region 212 is disposed in the n-type drift region 206. In addition, in the p-type body region 208, a p-type doping region 214 complementary to the n-type source region 210 is further disposed, and the p-type doping region 214 is electrically connected to the n-type source region 210. It is also worth noting that in FIG. 5, the spatial relative relationship of certain constituent elements is emphasized, and the n-type source region 210, the n-type drain region 212, the p-type substrate region 206, and the like are not illustrated. The p-type doping region 214 and the like constitute an element, but those skilled in the art should be able to easily know the formation position of the above-mentioned constituent elements according to the disclosures of FIGS. 6 and 7, so that the spatial relationship of the constituent elements is no longer Narration.

Please also refer to Figures 5 to 7. The gate 220 of the HVMOS transistor device 200 provided in the preferred embodiment includes a gate conductive layer 222, a gate dielectric layer 224, and a sidewall spacer 226 formed on the sidewall of the gate conductive layer 222. And as shown in FIG. 5, is provided on the substrate 202 on the gate electrode lines 220 a extend along a first direction D _1. In addition, a plurality of STIs 204 for electrically isolating the HV MOS transistor component 200 from other semiconductor components are disposed in the substrate 202. It should be noted that the HV MOS transistor component 200 provided by the preferred embodiment further includes a plurality of insulating structures 230, such as a plurality of STIs. It should be noted that the insulating structure 230 provided by the preferred embodiment is composed of a first insulating structure 230a and a second insulating structure 230b, respectively. As shown in FIG. 5, each of the insulating structure 230a of the first insulating structure 230 along a second line extending direction D _2, D ₂ and the second direction line as shown in FIG. 5, the first direction D ₁ are staggered, Preferably they are perpendicular to each other. More importantly, the first insulating structure 230a is inserted into the n-type drift region 206, so that where the gate 220 passes, a pattern in which the n-type drift region 206 and the plurality of first insulating structures 230a are alternately arranged is formed. And the n-type drift region 206 and the first insulating structure 230a are staggered in the first direction D ₁ . In other words, the gate 220 covers a portion of each of the n-type drift regions 206 and a portion of the respective insulating structures 230, and the drift regions 206 under the gates 220 and the first insulating structures 230 are staggered with each other along the first direction D ₁ . As shown in FIG. 5, in the preferred embodiment, the first insulating structure 230a and the n-type drift region 106 have the same width, but are not limited thereto. The second insulating structure 230b of the insulating structure 230 extends along the first direction D ₁ and is disposed below the gate 220 near one side of the drain region 212. In addition, as shown in FIG. 5, the second insulating structure 230b is disposed on one side of the first insulating structure 230a, and overlaps with a portion of each of the first insulating structures 230a and is physically connected. More importantly, each of the second insulating structures 230b is physically connected to each other to form a continuous structure. Therefore, the second insulating structure 230a and the first insulating structure 230a form a comb-like insulating structure, and the second insulating structure 230b serves as a comb handle of the comb-like insulating structure; the first insulating structure 230a serves as a comb-like insulating structure. Comb teeth.

Please refer to Figure 5 and Figure 7. In the preferred embodiment, the STI 204 and the insulating structure 230 can be formed by different fabrication methods. For example, a shallow trench (not shown) may be formed on the substrate 202 to predetermine the location where the second insulating structure 230b is formed. A pattern is then formed on the substrate 202 A mask (not shown) is used to define the formation positions of the first insulating structure 230a and the STI 204. Next, an etching process is performed to etch the substrate 202 through the patterned mask to form a deep trench (not shown) in the substrate 202. Then, the insulating material is filled in the shallow trench and the deep trenches, and the excess insulating material is removed by a planarization process, and the first insulating structure 230a and the second insulating structure 230b are simultaneously formed to electrically isolate the HV. STI 204 of MOS component 200 and other components. As shown in FIG. 7, since a part of the first insulating structure 230a overlaps with the second insulating structure 230b, when the etching process of the deep trench is performed, the overlapping portions obtain a large depth, so the final formed The first insulating structure 230a can also include a first portion 232 and a second portion 234. As shown in FIG. 6, in the preferred embodiment, the depth of the first portion 232 is the same as the depth of the STI 204, and the depth of the second portion 234 is greater than the depth of the STI 204. In addition, the depth of the second insulating structure 230b is smaller than the first insulating structure 230a and the STI 204, and preferably smaller than the depth of the drain region 212, as shown in FIG. However, those skilled in the art should be aware that the manner in which the STI 204, the first insulating structure 230a, and the second insulating structure 230b are formed is not limited to the above steps, and may be separately fabricated. Therefore, in other embodiments, the first insulating structure 230a may be a structure that does not have a depth difference by itself, that is, the first insulating structure 230a has an exact same depth, and the depth is equal to the depth of the STI 204.

Please refer back to Figure 7. In the preferred embodiment, the gate conductive layer 222 overlaps a portion of the p-type body region 208 to form a channel region 228 having a length L ₁ . In addition, the gate 220 also overlaps and is in direct contact with the portion of the n-type drift region 206, and the portion of the gate conductive layer 222 that overlaps with the n-type drift region 206 and directly contacts has a length L ₂ . In addition, the gate conductive layer 222 further overlaps a portion of the second insulating structure 230b, and the overlapped portion has a length L ₃ . As shown in FIG. 6, the channel region 228 and the second insulating structure 230b are separated from each other by the n-type drift region 206. More importantly, in the preferred embodiment, either length L ₁ , length L _{2 ,} and length L ₃ may not be zero. Since the depth of the second insulating structure 230b is smaller than the depth of the STI 204, the phenomenon of electric field crowding can be alleviated, so that the breakdown voltage can be increased without increasing the on-resistance.

Please refer back to Figures 5 to 7. Below the gate 220, an n-type drift region 206 (and a portion of the p-type body region 208 formed therein) and an insulating structure 230 are interleaved. As shown in FIG. 6, when the first insulating structure 230a of the insulating structure 230 is formed under the gate 2120, the gate conductive layer 222 and the gate dielectric layer 224 of the entire gate structure are as shown in FIG. It overlaps with the first insulating structure 230a. In other words, the portion of the channel region that would otherwise be formed is now fully occupied by the first insulating structure 230. However, when the underlying formation of the gate 220 is the second insulating structure 230b of the insulating structure 230, the n-type drift region 206, and the partial p-type base region 208 as shown in FIG. 7, the channel region 228 can still be retained, and Ensuring that current can reach the source region 210 from the drain region 212 via the n-type drift region 206 and the channel region 228, and achieve a voltage drop in this path. More importantly, since the first insulating structure 230a is disposed on both sides of the n-type drift region 206 as shown in FIGS. 5 and 6 in the parallel second direction D ₂ , the n-type drift region can be alleviated. The electric field in part 206 reaches the purpose of increasing the breakdown voltage. In addition, since the corner of the p-type base region 208 (as indicated by the circle C in FIG. 7) is the most fragile pn junction, the depth of the first insulating structure 230a is preferably greater than the depth of the p-type base region 208. Therefore, the corner C of the p-type base region 208 can be sandwiched from both sides to enhance the electric field thereof, thereby preventing the HV MOS transistor element 200 from collapsing at the corner C of the p-type base region 208.

Therefore, the HV MOS transistor element 200 according to the preferred embodiment reduces the phenomenon of electric field concentration by the second insulating structure 230b disposed under the gate 220, and is further arranged by the n-type staggered under the gate 220. The drift region 206 and the first insulating structure 230a mitigate the electric field of the n-type drift region 206, so that the breakdown voltage can be further increased without increasing the on-resistance.

Please refer to FIG. 8. FIG. 8 is a partial layout diagram of a third preferred embodiment of the HV MOS transistor component provided by the present invention. It should be noted that in order to highlight the relative relationship of some constituent elements of the HV MOS transistor component provided by the preferred embodiment, the doped regions such as the source region, the drain region and the substrate region are not shown in FIG. 8 . in. However, those skilled in the art should readily appreciate the formation positions of the constituent elements in accordance with the first and second preferred embodiments described above.

Please refer to Figure 8. The HV MOS transistor element 300 of the preferred embodiment includes an n-type drift region 306 disposed in a substrate (not shown) and a gate 320 disposed on the n-type drift region 306, and The gate 320 has a layout shape of a playground track type. As shown in Fig. 8, the gate 320 is composed of a pair of mutually parallel straight portions 320a and a pair of curved end portions 320b respectively provided at both ends of the gate straight portion 320a. In addition, the gate 320 provided in the preferred embodiment may also be any pattern for the HV MOS transistor component. For example, the gate 320 may be a rectangular frame pattern or extend along an edge of a comb pattern. Comb box shape. It should be noted that the HV MOS transistor component 300 provided by the preferred embodiment may adopt a design of a common source or a common source. When the HV MOS transistor element 300 is of a common source design, the source region is formed in the n-type drift region 306 at the center of the raceway-shaped gate 320, that is, the common source is surrounded by the gate 320. Similarly, when the HV MOS transistor element 300 is of a common drain design, the drain region is formed in the n-type drift region 306 at the center of the raceway-shaped gate 320, so that the common drain is surrounded by the gate 320.

The HV MOS transistor component 300 provided by the preferred embodiment further includes an STI 304 for providing electrical isolation. In addition, it is noted that the HV MOS transistor component 300 provided by the preferred embodiment further includes a plurality of insulating structures 330, such as a plurality of STIs. One of the insulating structures 330 may have a depth There are many types. For example, the depth of the insulating structure 330 can be the same as that of the STI 304 as described in the first preferred embodiment and in FIG. However, the insulating structure 330 can also have a first insulating structure and a second insulating structure as described in the second preferred embodiment, wherein the depth of the first insulating structure is greater than or equal to the depth of the STI 304, and the depth of the second insulating structure. The system can be smaller than the first insulating structure and the STI 304 as shown in FIG. In addition, the first insulating structure may also include the first portion and the second portion having different depths as described in the second preferred embodiment and the sixth embodiment. For the above-mentioned differences in depth differences, reference may be made to the first and second preferred embodiments described above, and thus no further details are provided herein. In addition, when the insulating structure 330 includes the first insulating structure and the second insulating structure having different depths, the second insulating structure having a depth smaller than the first insulating structure and other STIs is disposed under the gate 320 near one side of the shared drain .

Please continue to see Figure 8. It should be noted that in the preferred embodiment, the insulating structures 330 are arranged in the same direction as the gate 320 extends. More importantly, the insulating structure 330 is inserted into the n-type drift region 306. Therefore, where the gate 320 passes, a pattern in which a plurality of n-type drift regions 306 and a plurality of insulating structures 330 are alternately disposed is formed. In the preferred embodiment, the insulating structure 330 under the gate straight portion 320a has the same width as the n-type drift region 306, but is not limited thereto. However, the insulating structure 330 and the n-type drift region 306 under the gate curve portion 320b may have different widths. More importantly, the respective insulating structures 330 under the gate curve portion 320b may themselves have different widths. As shown in FIG. 8, the insulating structure 330 under the gate curve portion 320b has a first end 332 and a second end 334. The first end 332 has a width W ₁ and the second end 334 has a width W ₂ . And the width W _{1 is} smaller than the width W ₂ . This is because the electric field concentration is often caused in the gate curve portion 320b to reduce the breakdown voltage and the like. Therefore, the preferred embodiment provides the insulating structure 330 having a larger width in the gate curve portion 320b to alleviate the effect of the electric field concentration in the portion. .

As can be seen from FIG. 8, the n-type drift region 306 and the insulating structure 330 are alternately formed under the gate 320. When the insulator 320 is formed below the gate 320, the entire gate 320 overlaps the insulating structure 330. In other words, the portion of the channel region that would otherwise be formed is now fully occupied by the insulating structure 330. However, when the underlying formation of the gate 320 is the n-type drift region 306 as shown in FIG. 8, the channel region can still be preserved, and electrons can be ensured from the source region via the channel region and the n-type drift region 306. The polar region and the purpose of achieving pressure drop in this path.

Therefore, the HV MOS transistor element 300 according to the third preferred embodiment reduces the electric field of the n-type drift region 306 by the n-type drift region 306 and the insulating structure 330 staggered under the gate 320. In addition, when the insulating structure 330 includes an insulating structure having a depth smaller than that of the general STI 304, the phenomenon of electric field concentration can be alleviated. Therefore, the HV MOS transistor element 300 provided in the preferred embodiment can increase the breakdown voltage without increasing the on-resistance.

In the above, the HV MOS transistor component provided by the present invention provides an insulating structure disposed under the gate and interleaved with the drift region, and the drift region and the insulating structure are used to reduce the drift region. Electric field strength. In addition, when the insulating structure itself has a difference in depth, the present invention can alleviate the effect of electric field concentration by a shallow insulating structure having a depth smaller than that of an STI generally providing electrical isolation. Therefore, the present invention can overcome low on-resistance and high breakdown voltage, and these two requirements are often difficult to balance with each other, and effectively increase the breakdown voltage without increasing the on-resistance, and further increase the HV MOS transistor component. ability. In addition, the HV MOS transistor element provided by the present invention can be effectively applied to a common source or a common drain design, and provides an insulating structure having a different width in a portion where electric field concentration is likely to occur, and the present invention provides The HV MOS transistor component is more effective in mitigating the problem of a breakdown voltage caused by a common source or common electric field concentration of a common drain design.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧High voltage lateral double diffused MOS transistor components

12‧‧‧Semiconductor substrate

14‧‧‧ source

16‧‧‧ gate

18‧‧‧汲polar

20‧‧‧P type well

22‧‧‧P-doped area

30‧‧‧N type well

40‧‧‧ gate dielectric layer

42‧‧‧Field oxide layer

100, 200, 300‧‧‧ high voltage MOS transistor components

102, 202‧‧‧ base

104, 204, 304‧‧‧ shallow trench isolation

106, 206, 306‧‧‧n drift zone

108, 208‧‧‧p type base area

110, 210‧‧‧ source area

112, 212‧‧ ‧ bungee area

114, 214‧‧‧p-type doped region

120, 220, 320‧‧‧ gate

320a‧‧‧ Straight line

320b‧‧‧ Curve section

122, 222‧‧‧ gate conductive layer

124, 224‧‧ ‧ gate dielectric layer

126, 226‧‧‧ side wall

128, 228‧‧‧ passage area

130, 230, 330‧‧‧ insulation structure

230a‧‧‧First insulation structure

230b‧‧‧Second insulation structure

232‧‧‧ first

234‧‧‧Part II

332‧‧‧ first end

334‧‧‧ second end

_{A 1 -A 1 ', A 2} -A 2', B 1 -B 1 ', B 2 -B 2' ‧‧‧ tangent

C‧‧‧ Corner of the base area

D ₁ ‧‧‧First direction

D ₂ ‧‧‧second direction

L ₁ , L ₂ , L ₃ ‧‧‧ length

W ₁ , W ₂ ‧ ‧ width

Figure 1 is a schematic cross-sectional view of a conventional HV-LDMOS transistor device.

2 is a partial layout diagram of a first preferred embodiment of the HV MOS transistor component provided by the present invention.

Fig. 3 to Fig. 4 are schematic cross-sectional views taken along line A _{1 -} A ₁ ' and B ₁ - B ₁ ' in Fig. 2, respectively.

FIG. 5 is a partial layout diagram of a second preferred embodiment of the HV MOS transistor component provided by the present invention.

Fig. 6 to Fig. 7 are schematic cross-sectional views taken along line A _{2 -} A ₂ ' and B ₂ - B ₂ ' in Fig. 5, respectively.

FIG. 8 is a partial layout diagram of a third preferred embodiment of the HV MOS transistor component provided by the present invention.

100‧‧‧High voltage MOS transistor components

104‧‧‧Shallow trench isolation

106‧‧‧n type drift zone

120‧‧‧ gate

130‧‧‧Insulation structure

A ₁ -A ₁ '‧‧‧ Tangent

B ₁ -B ₁ '‧‧‧ Tangent

D ₁ ‧‧‧First direction

D ₂ ‧‧‧second direction

Claims (16)

A high voltage metal-oxide-semiconductor (HV MOS) transistor component includes: a substrate; a gate disposed on the substrate; a drain region and a source region, respectively In the substrate on both sides of the gate; a body region and a drift region, wherein the source region is disposed in the substrate region, and the substrate region and the drain region are disposed In the drift region; and a first isolation structure disposed under the gate, and the gate is completely overlapped with the first insulation structure. The HV MOS transistor device of claim 1, further comprising a plurality of second insulating structures disposed in the substrate, the second insulating structures electrically insulating the HV MOS transistor. The HV MOS transistor component of claim 2, wherein one of the first insulating structures has a depth equal to one of the second insulating structures. The HV MOS transistor component of claim 2, wherein the first insulating structure further comprises a first portion and a second portion, the first portion A first depth is included and the second portion includes a second depth. The HV MOS transistor component of claim 4, wherein the first depth is equal to a depth of the second insulating structure, and the second depth is greater than the depth of one of the second insulating structures. The HV MOS transistor component of claim 2, further comprising a third insulating structure disposed under the gate. The HV MOS transistor component of claim 6, wherein a depth of one of the third insulating structures is less than a depth of one of the first insulating structures and a depth of the second insulating structures. The HV MOS transistor component of claim 6, wherein the gate portion covers a portion of the third insulating structure. The HV MOS transistor component of claim 6, wherein the first insulating structure contacts the third insulating structure. A high voltage semiconductor transistor component (HV MOS) transistor component includes: a substrate; a gate disposed on the substrate, and the gate is extended along a first direction Extending; a plurality of drift regions are formed in the substrate, and the drift regions are arranged along the first direction; a plurality of first insulating structures are formed in the substrate, and each of the first insulating structures is along a second The direction is extended, and the second direction is perpendicular to the first direction, the first insulating structures are arranged along the first direction; and a second insulating structure is disposed in the substrate and extends along the first direction, And the gate partially overlaps the second insulating structure, wherein the gate covers the drift region and a portion of each of the first insulating structures, and the drift regions under the gate and the first insulating structures The lines are staggered with each other along the first direction. The HV MOS transistor component of claim 10, wherein the drift regions are electrically connected to each other. The HV MOS transistor component of claim 11, further comprising a source region and a drain region disposed in the drift region on both sides of the gate. The HV MOS transistor component of claim 10, wherein the second insulating structure partially overlaps each of the first insulating structures. For example, the HV MOS transistor component described in claim 10, Wherein the depth of one of the second insulating structures is less than a depth of the first insulating structures. The HV MOS transistor component of claim 10, wherein each of the first insulating structures comprises a first end and a second end. The HV MOS transistor component of claim 15, wherein the width of the first end is different from the width of the second end.