TWI542003B - High voltage metal-oxide-semiconductor transistor device and layout pattern thereof - Google Patents

Description

High voltage MOS transistor and its layout pattern

The invention relates to a high voltage metal-oxide-semiconductor (hereinafter referred to as HV MOS) transistor component and a layout pattern thereof, in particular to a high voltage lateral double-diffused metal (high voltage lateral double-diffused metal). -oxide-semiconductor, HV-LDMOS) transistor components and their layout patterns.

Among power components with high-voltage processing capability, double-diffused MOS (DMOS) transistor components continue to receive attention. Common DMOS transistor components are vertical double-diffused MOS (VDMOS) and lateral double-diffused metal oxide semiconductor (LDMOS) transistor components. LDMOS transistor components are widely used in high-voltage operating environments due to their high operating bandwidth and operating efficiency, as well as planar structures that are easily integrated with other integrated circuits, such as CPU power supply (CPU power). Supply), power management system, AC/DC converter, and high-power or high-band power amplifiers. The main feature of the LDMOS transistor component is the low doping concentration and large-area lateral diffusion drift region set by the source terminal. The purpose is to alleviate the high voltage between the source terminal and the drain terminal, so that the LDMOS transistor component can be obtained. High breakdown voltage (breakdown voltage).

Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a conventional HV-LDMOS transistor device. As shown in FIG. 1, a conventional HV-LDMOS transistor element 10 is disposed on a semiconductor substrate 12 having a P-well 20, a source 14 disposed in the P-well 20, and a high concentration. P-doped region 22, a gate 16 and a drain 18. The drain 18 is a high concentration N-type doped region and is disposed in an N-type well 30. The N-type well 30, that is, the aforementioned drift region, whose doping concentration and length affect the breakdown voltage and ON-resistance (R _ON ) of the HV-LDMOS transistor element 10. The gate 16 of the HV-LDMOS transistor component 10 is disposed on a gate dielectric layer 40 and extends over the field oxide layer 42.

Since the two main characteristics pursued by HV MOS transistor components are low on-resistance and high breakdown voltage, and these two requirements are often conflicting with each other, it is difficult to balance. Therefore, there is still a need for a solution that can operate normally in a high voltage environment while satisfying both low on-resistance and high breakdown voltage.

Accordingly, it is an object of the present invention to provide an HV MOS transistor element that provides low on-resistance and high breakdown voltage and a layout pattern thereof.

According to the scope of the invention provided by the present invention, a layout pattern of a HV MOS transistor is provided. The layout pattern includes a first doped region, a second doped region, and a non-continuous doped region disposed between the first doped region and the second doped region. The first doped region and the second doped region have a first conductivity type. The discontinuous doped region further includes a plurality of third doped regions, a plurality of gaps interlaced with the third doped regions, and a plurality of fourth dopings disposed within the equally spaced regions Area. The third doped regions comprise a second conductivity type, and the second conductivity pattern is complementary to the first conductivity pattern; and the fourth doped regions comprise the first conductivity type.

According to the scope of the invention provided by the present invention, an HV MOS transistor element is additionally provided. The HV MOS transistor component includes a substrate, a gate disposed on the substrate, a drain region disposed in the substrate, a source region disposed in the substrate, and a source region disposed on the source region A discontinuous doped region between the drain region and the drain region. An insulating layer is formed on the substrate, and the gate covers a portion of the insulating layer. The drain region and the source region have a first conductivity type. In addition, the discontinuous doped region further includes a plurality of third doped regions, a plurality of intervals alternately disposed with the third doped regions, and a plurality of fourth doped regions disposed within the equally spaced regions . The third doped regions comprise a second conductivity type, and the second conductivity pattern is complementary to the first conductivity pattern. And the fourth doped regions comprise the first conductivity type.

The HV MOS transistor element and its layout pattern according to the present invention utilize the discontinuous doped region to boost the breakdown voltage of the HV MOS transistor. In addition, the HV MOS transistor component and its layout pattern provided by the present invention are disposed in the discontinuous doping region to reduce the total area of the doped portion in the discontinuous doped region. In the present invention, the fourth doped regions disposed within the equal intervals are used as a shortcut for electron flow, so that the on-resistance can be more effectively reduced. Briefly, the HV MOS transistor component and its layout pattern provided by the present invention can simultaneously achieve the high breakdown voltage and low on-resistance.

Please refer to FIG. 2 to FIG. 7 , wherein FIG. 2 and FIG. 6 to FIG. 7 are schematic diagrams showing the layout pattern of the HV MOS transistor component provided by the present invention, and FIG. 3 to FIG. 5 are respectively FIG. 2 . A schematic cross-sectional view taken along the line A-A', B-B' and C-C' tangent. As shown in FIG. 2 to FIG. 5, the HV MOS transistor element 100 provided in the preferred embodiment is disposed on a substrate 102, such as a substrate. The substrate 102 has a first conductivity type, which in the preferred embodiment is p-type. The HV MOS transistor element 100 further includes an insulating layer 104, but it is noted that in order to clearly show the relative relationship of certain specific doping regions in the HV MOS transistor element 100, the insulating layer 104 is omitted in FIG. Those skilled in the art should be able to readily understand the location of the insulating layer 104 in accordance with the drawings in Figures 3 through 5.

Please continue to see Figures 2 through 5. The HV MOS transistor component 100 provided by the preferred embodiment further includes a deep well region 106, the deep well region 106 includes a second conductivity type, and the second conductivity type is complementary to the first conductivity type. Therefore, in the preferred embodiment, the second conductivity type is n-type. In the deep well region 160, a drift region 108 (shown in Figures 3 through 5) and a high pressure well region 110 (also shown in Figures 3 through 5) are formed. The drift region 108 includes a second conductivity type; and the high voltage well region 110 includes a first conductivity type. In other words, the HV MOS transistor element 100 includes an n-type drift region 108 and a p-type high voltage well region 110. In the n-type drift region 108, a first doping region 112 is formed; and in the high voltage well region 110, a second doping region 114 and a third doping region 116 are formed. The first doping region 112 and the second doping region 114 have a second conductivity type and serve as the n-type drain region 112 and the n-type source region 114 of the HV MOS transistor element 100, respectively. The third doped region 116 includes a first conductivity type for use as a p-type body region 116 of the HV MOS transistor device 100. As shown in FIGS. 2 to 5, the base region 116 is electrically connected to the source region 114.

The HV MOS transistor device 100 also includes a gate 130, but it is noted that in order to clearly show the relative relationship of certain specific doped regions in the HV MOS transistor device 100, the gate 130 is also omitted in FIG. Those skilled in the art can also easily understand the position of the gate 130 according to the drawings in Figures 3 to 5. As shown in Figures 3 to 5, the gate 130 is set On the substrate 102, a portion of the insulating layer 104 is covered.

Please still refer to Figures 2 through 5. The HV MOS transistor element 100 provided by the preferred embodiment further includes a non-continuous doped region 120. As shown in FIGS. 2 to 5, the discontinuous doped region 120 is disposed between the drain region 112 and the source region 114, and the drain region 112, the source region 114, and the discontinuous shape are doped. The miscellaneous regions 120 are spaced apart from one another and electrically isolated the drain region 112, the source region 114, and the discontinuous doped region 120 using the deep well region 106. As shown in FIG. 2 to FIG. 5 , the discontinuous doped region 120 further includes a plurality of fourth doped regions 122 , a plurality of spaces 124 , and a plurality of fifth doped regions 126 . The fourth doped region 122 includes the first conductive type, and thus is a p-type doped region 122; the fifth doped region 126 includes the second conductive type, and thus is an n-type doped region 126. It should be noted that the fifth doping region 126 is doped with a doping concentration, and the doping concentration is less than 1 ^* 10 ¹² (1E12), but is not limited thereto.

As shown in FIG. 2, the spacers 124 are interleaved with the p-type doping regions 122, so that each of the p-type doping regions 122 is adjacent to the spacer 124, and the n-type doping region 126 is disposed in the interval 124. . Therefore, the p-type doping region 122 and the n-type doping region 126 are isolated from each other by the interval 124. In addition, as shown in FIGS. 3 to 5, the insulating layer 104 completely covers the discontinuous doped region 120. In other words, the insulating layer 104 completely covers the p-doped region 122 (as shown in FIG. 3). , an interval 124 (as shown in FIG. 4), and an n-type doping region 126 (eg, Figure 5). It is noted that the total area of the spaces 124 is less than or equal to 20% of the area of the discontinuous doped region 120. It should be noted that although in the preferred embodiment, an n-type doping region 126 is disposed in each of the spaces 124, in the variation of the present invention, depending on the product requirements, at certain intervals 124 The n-type doped region 126 is disposed internally, while the arrangement of the n-type doped region 126 is omitted in some of the spaces 124.

Please refer back to Figure 2. According to the HV MOS transistor device 100 and the layout pattern thereof provided by the preferred embodiment, the p-type doping region 122 and the n-type doping region 126 are each a rectangular doped region, and the length of the n-doped region 126 is long. The edge is parallel to the short side of the p-doped region 122. More importantly, the length L of the n-type doped region 126 is equal to the width W _{1 of the} p-type doped region 122 as shown in FIG. Further, the spacer 124 has a width W _2, and the line width W ₂ of 9 microns or less (micrometer, μm). Therefore, an n-type doped region 124 in the spaces 126 of one line width W ₃ is less than 7 m, and the width of the n-type doped region 126 must be less than the width W ₃ W ₂ 124 of the spacer.

The HV MOS transistor element 100 according to the preferred embodiment is disposed under the insulating layer 104, and the conductive pattern is complementary to the discontinuous doped region 120 of the n-type source region 114 and the n-type drain region 112. The resistance value of the HV MOS transistor element 100 can be raised by the p-type doping region 122. When the high voltage signal flows through the path, the voltage drop capability of the embodiment is effectively increased due to the increase of the resistance value, and then the output signal becomes a low voltage signal. In other words, by the arrangement of the p-type doping region 122, the breakdown voltage of the HV MOS transistor element 100 can be effectively improved. However, the improvement in the on-resistance of the HV MOS transistor component 100 is not desirable to the industry, and thus the preferred embodiment provides a plurality of spacers 124 in the discontinuous doped region 120. Since the spacer 124 can be provided to reduce discontinuity in the area of the shaped portion doping region 120 having a p-type dopant, it is effective to reduce the R _ON.

More importantly, the preferred embodiment further provides an n-type doped region 126 in the spacer 124, and the n-type doped region 126 provides a relatively simple path for electrons, thereby reducing R _ON . As described above, since the high breakdown voltage and the low on-resistance are two conflicting requirements, in the preferred embodiment, the total area of the spacers 124 accounts for less than or equal to 20% of the area of the discontinuous doped region 120. %, and the width W _{2 of the} interval 124 is less than or equal to 9 μm, while the doping concentration of the n-type doping region 126 is less than 1E10 and the width W ₃ is less than 7 μm to satisfy the requirement of high breakdown voltage while reducing the on-resistance.

See also Figure 6. It is noted that in order to clearly show the relationship between the p-doped region 122 and the spacer 124 in the discontinuous doped region 120, only the p-doped region 122 of the discontinuous doped region 120 is depicted in FIG. The spacer 124 is omitted, but the n-type doped region 126 is omitted, however, those skilled in the art should be able to compare the spatial relationship of the n-doped region 126 with other constituent elements in accordance with the aforementioned FIGS. 2 through 5. As shown in FIG. 6, in the preferred embodiment, the discontinuous doped region 120 may be further defined to include an inner portion 140 and an outer portion 142. In detail, the discontinuous doped regions 120 are arranged along the edge of the deep well region 106 to form a racetrack shape or a comb shape; the p-type doped regions 122 and spaces 124 are also arranged along the edge of the deep well region 106 and are in the shape of a racetrack or Comb shape. The comb base, the outermost two comb teeth, and the front end of each comb are defined as a peripheral portion 142, and the inner comb and the comb bottom are defined as a central portion 140. It should be noted that the interval 124 disposed at the central portion 140 has a first pattern density D ₁ , and the interval 124 disposed at the peripheral portion 142 has a second pattern density D ₂ , and the first pattern density D _{1 is} less than the second Pattern density D ₂ . For example, spacer portion 140 disposed at the center 124 of the total area of the discontinuous shape representing the area doped region 120 R ₁ Percentage 15% or less; and provided on the peripheral portion 142 of the spacer 124 of the total area accounting for discontinuous shape The percentage R ₂ of the area of the doped region 120 is less than or equal to 25%, and the total area of the interval 124 of the central portion 140 occupies the total area of the area R _{1 of the} discontinuous doped region 120 and the interval 124 of the peripheral portion 142. The difference in the percentage R ₂ of the area of the discontinuous doped region 120 may be 7%, but is not limited thereto. Additionally, as previously discussed, in variations of the present invention, the n-type doped regions 126 may be disposed in certain spaces 124 as desired by the product, while the n-type doped regions 126 are omitted in certain spaces 124. Settings. In detail, the n-type doping region 126 may be disposed in each of the spaces 124 of the peripheral portion 142, however, the spacer 124 disposed at the central portion 140 may selectively omit the plurality of n-type doping regions 126. This is because in the HV MOS transistor element 100, the n-type deep well region 106 corresponding to the peripheral portion 142 has a lower doping concentration due to the doping process relationship, resulting in the HV MOS transistor 100 corresponding to the peripheral portion 142. There is a high on-resistance. Therefore, the second pattern density D ₂ provided in the interval 124 of the peripheral portion 142 provided by the preferred embodiment is higher, or has more n-type doping regions 126. In other words, since the total area of the spaces 124 of the peripheral portions 142 is large or has a large number of n-type doping regions 126, the HV MOS transistor element 100 can be lowered corresponding to the peripheral portion 142 without affecting the breakdown voltage. On-resistance.

See also Figure 7. As previously described, to clearly illustrate the relationship of the p-doped region 122 to the spacer 124 in the discontinuous doped region 120, only the p-doped region 122 of the discontinuous doped region 120 is depicted in FIG. The spacer 124 is omitted, but the n-type doped region 126 is omitted, however, those skilled in the art should be able to compare the spatial relationship of the n-doped region 126 with other constituent elements in accordance with the aforementioned FIGS. 2 through 5. As shown in FIG. 7, in the preferred embodiment, the discontinuous doped region 120 can be further defined to include a plurality of corner regions 150 and a plurality of straight-line regions 152. As described above, the discontinuous doped regions 120 are arranged in the shape of a comb along the edge of the deep well region 106, and as shown in Fig. 7, the discontinuous doped regions 120 having the circular arc shape are all Defined as a corner portion 150, the discontinuous doped region 120 arranged in a line is defined as a straight portion 152. It should be noted that the interval 124 disposed at the corner portion 150 has a third pattern density D ₃ , and the interval 124 disposed at the straight portion 152 has a fourth pattern density D ₄ , and the third pattern density D _{3 is} greater than the fourth Pattern density D ₄ . Additionally, as previously discussed, in variations of the present invention, the n-type doped regions 126 may be disposed in certain spaces 124 as desired by the product, while the n-type doped regions 126 are omitted in certain spaces 124. Settings. In detail, the n-type doping region 126 may be disposed in each of the spaces 124 of the corner portion 150, however, the interval 124 disposed in the linear portion 152 may selectively omit the plurality of n-type doping regions 126. This is because in the HV MOS transistor element 100, the portion corresponding to the corner portion 150 has a large electric field, resulting in the HV MOS transistor 100 having a higher on-resistance at the corresponding corner portion 150. Therefore, the third pattern density D ₃ provided in the interval 124 of the corner portion 150 provided by the preferred embodiment is higher, or has more n-type doping regions 126. In other words, since the total area of the spaces 124 of the corner portions 150 is larger or has more n-type doping regions 12, the HV MOS transistor element 100 can be lowered corresponding to the corner portion 150 without affecting the breakdown voltage. On-resistance.

In summary, the HV MOS transistor component and its layout pattern provided by the present invention utilize the discontinuous doped region to increase the breakdown voltage of the HV MOS transistor. In addition, the HV MOS transistor element and its layout pattern provided by the present invention are disposed in the discontinuous doping region to reduce the total area of the doped portion in the discontinuous doped region. In the present invention, the doping region having the same conductivity type as the source/drain region disposed in the equal intervals is used as a shortcut for electron flow, so that the on-resistance can be more effectively reduced. Briefly, the HV MOS transistor component and its layout pattern provided by the present invention can simultaneously achieve the high breakdown voltage and low on-resistance.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧High voltage lateral double diffused MOS transistor components

12‧‧‧Semiconductor substrate

14‧‧‧ source

16‧‧‧ gate

18‧‧‧汲polar

20‧‧‧P type well

22‧‧‧P-doped area

30‧‧‧N type well

40‧‧‧ gate dielectric layer

42‧‧‧Field oxide layer

100‧‧‧High voltage MOS transistor components

102‧‧‧Base

104‧‧‧Insulation

106‧‧‧Shenjing District

108‧‧‧Drift area

110‧‧‧High-pressure well area

112‧‧‧First doped area

114‧‧‧Second doped area

116‧‧‧ Third doped area

120‧‧‧discontinuous doped area

122‧‧‧fourth doping zone

124‧‧‧ interval

126‧‧‧ fifth doping area

130‧‧‧ gate

140‧‧‧ central part

142‧‧‧ peripheral part

150‧‧‧ corner section

152‧‧‧ Straight line

Figure 1 is a schematic cross-sectional view of a conventional HV-LDMOS transistor device.

Fig. 2 is a schematic view showing the layout pattern of the HV MOS transistor element provided by the present invention.

Fig. 3 to Fig. 5 are schematic cross-sectional views taken along line A-A', B-B' and C-C' in Fig. 2, respectively.

6 and 7 are schematic views respectively showing the layout pattern of the HV MOS transistor component provided by the present invention.

100‧‧‧High voltage MOS transistor components

102‧‧‧Base

112‧‧‧First doped area

114‧‧‧Second doped area

116‧‧‧ Third doped area

120‧‧‧discontinuous doped area

122‧‧‧fourth doping zone

124‧‧‧ interval

126‧‧‧ fifth doping area

Claims (20)

A layout pattern of a high voltage MOS transistor, comprising: a first doped region having a first conductivity type; a second doped region having the first conductivity type; and a discontinuous shape ( a non-continuously doped region disposed between the first doped region and the second doped region, the discontinuous doped region further comprising: a plurality of third doped regions, the third doped regions The region includes a second conductivity type, and the second conductivity pattern is complementary to the first conductivity pattern; a plurality of gaps, and the intervals are interleaved with the third doped regions And a plurality of fourth doped regions disposed within the equal intervals, the fourth doped regions including the first conductive type, and the fourth doped regions and the third doped regions Complete separation by these intervals. The layout pattern of claim 1, wherein the first doped region, the second doped region, and the discontinuous doped region are spaced apart from each other. The layout pattern of claim 1, wherein the total area of the spaces accounts for less than or equal to 20% of the area of the discontinuous doped region. Such as the layout pattern described in claim 1 of the patent scope, wherein the fourth The length of the doped regions is equal to the width of the third doped regions. The layout pattern of claim 1, wherein the width of the spaces is less than or equal to 9 micrometers (μm). The layout pattern of claim 5, wherein the fourth doped region has a width of less than 7 micrometers. The layout pattern of claim 1, wherein the discontinuous doped region further defines an inner portion and an outer portion. The layout pattern according to claim 7, wherein the pattern density of the spaces disposed at the central portion is smaller than the pattern density of the spaces disposed at the peripheral portion. The layout pattern of claim 8, wherein a total area of the spaces disposed in the central portion occupies 15% or less of an area of the discontinuous doped region, and is disposed at the peripheral portion. The total area of the spacers is less than or equal to 25% of the area of the discontinuous doped region. The layout pattern of claim 1, wherein the discontinuous doped region further defines a plurality of corner regions and a straight-line area, and is disposed in the corner portion The interval The pattern density is greater than the pattern density of the spacing disposed at the line portion. The layout pattern of claim 1, wherein the third doped regions and the fourth doped regions are separated by the equal intervals. The layout pattern according to claim 1, wherein each of the four doped regions is formed in each of the intervals. A high voltage metal-oxide-semiconductor (HV MOS) transistor component, comprising: a substrate having an insulating layer formed thereon; a gate disposed on the substrate and covering a portion of the insulating layer a drain region disposed in the substrate, the drain region having a first conductivity type; a source region disposed in the substrate, and the source region including the first conductivity type; a discontinuous doped region disposed between the source region and the drain region, the discontinuous doped region further comprising: a plurality of third doped regions, wherein the third doped regions comprise a first a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; a plurality of intervals, and the intervals are alternately arranged with the third doped regions; and a plurality of fourth doped regions, Set within the interval, the first The four doped regions comprise the first conductivity type, and the fourth doped regions and the third doped regions are completely separated by the equal intervals. The HV MOS transistor component of claim 13 further comprising a deep well region, and the deep well region comprises the first conductivity type. The HV MOS transistor component of claim 14, wherein the source region, the drain region, and the discontinuous doped region are disposed in the deep well region, and the deep well region is electrically connected to each other Sexual isolation. The HV MOS transistor device of claim 13, wherein the discontinuous doped region is disposed under the insulating layer. The HV MOS transistor device of claim 13, wherein the length of the fourth doped region is equal to the width of the third doped region. The HV MOS transistor component of claim 13, wherein the width of the spaces is less than 9 microns. The HV MOS transistor device of claim 18, wherein the fourth doped region has a width of less than 7 microns. For example, the HV MOS transistor component described in claim 13 is The third doped regions and the fourth doped regions are separated by the equal intervals.