JP2010087421A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lateral semiconductor device that has a high withstand voltage and can reduce on-resistance more than that of a device of a prior art without changing a chip size and the withstand voltage in a lateral MOSFET. <P>SOLUTION: A lateral MOSFET 30 is divided into a first lateral MOSFET 31 and a second lateral MOSFET 32 that are connected in series. Thus a withstand voltage held between a first n<SP>+</SP>source region 5 and a second n<SP>+</SP>drain region 13 is held between a first n<SP>+</SP>source region 5 and a first n<SP>+</SP>drain region 9 of the first lateral MOSFET 31 and a second n<SP>+</SP>source region 10 and a second n<SP>+</SP>drain region 7 of the second horizontal MOSFET 32. Therefore, an electric field is held as two divided electric fields and an impurity concentration Cn of an n<SP>-</SP>drift region 3 can be increased from that before voltage division, thereby reducing on-resistance Ron without changing a device size. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lateral semiconductor device having a high breakdown voltage such as a lateral power MOSFET.

FIG. 6 is a cross-sectional view of a main part of a conventional high breakdown voltage lateral MOSFET using an SOI (Silicon On Insulator) substrate. Here, the lateral MOSFET 70 is a lateral N-channel MOSFET. The SOI substrate 80 has a structure in which an oxide film 52 and an n ⁻ drift region 53 are stacked in this order on a support substrate 51.
As shown in FIG. 6, the p base region 54 is selectively provided in the surface layer of the n ⁻ drift region 53, and the n ⁺ source region 55 is selectively provided in the surface layer of the p base region 54. An n ⁺ drain region 57 is selectively provided in the surface layer of the n ⁻ drift region 53 apart from the p base region 54. The n ⁺ source electrode 62 is in electrical contact with the n ⁺ source region 55 and the p base region 54. The drain electrode 63 is in electrical contact with the n ⁺ drain region 57.

A gate electrode 56 is provided on the p base region 54 sandwiched between the n ⁺ source region 55 and the n ⁻ drift region 53 via a gate insulating film 65.
Further, in Patent Document 1, an LDMOS, a LIGBT including a drift region having a first surface and a first conductivity type, and first and second conductive regions extending from the first surface into the drift region. In a lateral semiconductor device such as a lateral diode, a lateral GTO, a lateral JFET, or a lateral BJT, a second conductivity extending from the first surface into the drift region between the first semiconductor region and the second semiconductor region. It is described that it comprises one or more additional regions having a rate type.

The additional region forms a junction that divides the electric field between the first semiconductor region and the second semiconductor region when a current path is established between the first semiconductor region and the second semiconductor region. Yes. Therefore, it is disclosed that the doping concentration of the drift region can be increased, thereby reducing the on-resistance of the device.
Special table 2004-508697 gazette

FIG. 7 is a schematic diagram for explaining the relationship between each item of the lateral MOSFET 70 of FIG. 6 and the on-resistance and breakdown voltage (breakdown voltage). The specifications are as follows. In the lateral MOSFET 70, the length X of the n ⁻ drift region (the length between the p base region 54 and the n ⁺ drain region 57), the width Y (depth length) of the n ⁻ drift region, n ^- the depth of the drift region Z (depth to oxide film 52) and the n ^- impurity concentration Cn of the drift region.

When the on-resistance of the lateral MOSFET 70 is Ron, Ron∝X / (Y · Z). Further, when the impurity concentration of the n ⁻ drift region 53 is Cn, Ron∝1 / Cn. Therefore, Ron∝ (1 / Cn) · (X / (Y · Z)). Further, when the breakdown voltage is V _B , there is a relationship of Ron∝V _B ^2.5 .
To design the breakdown voltage V _B of the lateral MOSFET in high withstand voltage, when a high voltage is applied n ^- so that does not fit depletion layer extends in the drift region, n ^- it is necessary to increase the length X of the drift region. In order to increase the breakdown voltage V _B is, n ^- it is necessary to reduce the impurity concentration Cn of the drift region. When X is increased and Cn is decreased, Ron increases. Further, as X increases, the chip size increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral semiconductor device having a high withstand voltage that can reduce the on-resistance of a lateral MOSFET without changing the chip size and withstand voltage without changing the conventional element. .

  To achieve the above object, a first conductive type first semiconductor region (drift region) and a second conductive type second semiconductor region (first type) selectively provided on a surface layer of the first semiconductor region. 1 base region), a third semiconductor region (second base region) of a second conductivity type selectively provided on the surface layer of the first semiconductor region apart from the second semiconductor region, and the second semiconductor A first conductivity type fourth semiconductor region (first source region) selectively provided in a surface layer of the region, and the second semiconductor region separated from the second semiconductor region by the surface layer of the first semiconductor region; A fifth semiconductor region (first drain region) of a first conductivity type that is oppositely provided and selectively provided between the second semiconductor region and the third semiconductor region, and a surface layer of the third semiconductor region includes the first semiconductor layer. 5th semiconductor region of the 1st conductivity type selectively provided apart from 5 semiconductor regions A second source region), a seventh semiconductor region (second drain region) of the first conductivity type selectively provided on the surface layer of the first semiconductor region apart from the third semiconductor region, and the fourth A first gate electrode provided via a gate insulating film on the second semiconductor region sandwiched between the semiconductor region and the first semiconductor region; and the sixth semiconductor region sandwiched between the first semiconductor region and the first semiconductor region. A second gate electrode provided on the third semiconductor region via a gate insulating film; a first main electrode (source electrode) provided in electrical connection with the second semiconductor region; and the seventh semiconductor. A second main electrode (drain electrode) provided in electrical connection with the region, and a connection electrode provided in electrical connection with the fifth semiconductor region and the sixth semiconductor region, respectively To do.

When the fifth semiconductor region is selectively provided on the surface layer of the third semiconductor region across the pn junction of the first semiconductor region and the second semiconductor region, away from or in contact with the sixth semiconductor region. Good.
The first semiconductor region, the second semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the first gate electrode constitute a first lateral MOSFET portion, and the first semiconductor region, the third semiconductor region, The semiconductor region, the sixth semiconductor region, the seventh semiconductor region, and the second gate electrode constitute a second lateral MOSFET portion, and the connection electrode connects the first lateral MOSFET portion and the second lateral MOSFET portion in series. Good.

  The connection electrode may also serve as the drain electrode of the first lateral MOSFET part and the source electrode of the second lateral MOSFET part.

According to the present invention, the conventional lateral MOSFET is divided into a first lateral MOSFET portion and a second lateral MOSFET portion, and each is connected in series, so that the n ⁺ source region and the n ⁺ drain region of the conventional lateral MOSFET are connected. The withstand voltage held by the first lateral MOSFET portion of the present invention is between the first n ⁺ source region and the first n ⁺ drain region, and between the second n ⁺ source region and the second n ⁺ drain region of the second lateral MOSFET portion. The pressure is divided and held.

As a result, the electric field is divided and kept in two, and the impurity concentration in the n ⁻ drift region can be made higher than before voltage division, so that the on-resistance can be reduced without changing the device size. Can do.
According to the semiconductor device of the present invention, it is possible to have a larger current capability than the conventional one while having the same breakdown voltage as that of the conventional lateral MOSFET.

  Embodiments will be described in the following examples. In the following description, the first conductivity type is p-type and the second conductivity type is n-type, but they may be reversed.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the lateral MOSFET 30 of the present invention is manufactured on an SOI substrate 40. The SOI substrate 40 has a structure in which an oxide film 2 and an n ⁻ drift region 3 are stacked in this order on a support substrate 1.
A first p base region 4 and a second p base region 8 are selectively provided separately from the surface layer of the n ⁻ drift region 3. A first n ⁺ source region 5 is selectively provided on the surface layer of the first p base region 4. The first n ⁺ drain region 5 is selectively provided in the surface layer of the n ^- drain region 3 adjacent to the surface layer of the second p base region 8 and facing the first n ⁺ source region 5. A second n ⁺ source region 10 is selectively provided on the surface layer of the second p base region 8 apart from the first n ⁺ drain region 5. A second n ⁺ drain region 7 is selectively provided in the surface layer of the n ⁻ drain region 3 apart from the second p base region 8.

On the first p base region 4 sandwiched between the first n ⁺ source region 5 and the n ⁻ drift region 3, a first gate electrode 6 is provided via a gate insulating film 15. A second gate electrode 11 is provided on the second p base region 8 sandwiched between the second n ⁺ source region 10 and the n ⁻ drift region 3 via a gate insulating film 16.
A first source electrode 12 is provided in electrical contact with the first n ⁺ source region 5 and the first p base region 4. A connection electrode 14 serving as both the first drain electrode and the second source electrode is provided in electrical contact with the first n ⁺ drain region 5, the second p base region 8 and the second n ⁺ source region 10. A second drain electrode 13 is provided in electrical contact with the second n ⁺ drain region 7. The first source electrode 12 becomes the source electrode of the lateral MOSFET 30, and the second drain electrode 13 becomes the drain electrode of the lateral MOSFET 30.

  The lateral MOSFET 30 includes a first lateral MOSFET portion 31 and a second lateral MOSFET portion 32. The electrodes of the first lateral MOSFET portion 31 are a first source electrode 12, a first drain electrode (connection electrode 14), and a first gate. Each electrode of the second lateral MOSFET section 32 is the second source electrode (connection electrode 14), the second drain electrode 13, and the second gate electrode 11.

The connection electrode 14 serving as the first drain electrode and the second source electrode serves to connect the first lateral MOSFET portion 31 and the second lateral MOSFET portion 32 in series.
FIG. 2 is an explanatory diagram for explaining the operation of the lateral MOSFET of the present invention.
First, the off state of the lateral MOSFET 30 of the present invention will be described. As shown in FIG. 2, as shown in FIG. 1, the lateral MOSFET 30 is formed on the same semiconductor substrate (n ⁻ drift region 3) by connecting a first lateral MOSFET portion 31 and a second lateral MOSFET portion 32 in series. It has the structure made.

A voltage Vo is applied between the source electrode (first source electrode 12) and the drain electrode (second drain electrode 13) of the lateral MOSFET 30. The extension of the depletion layer 17 extending to the n ⁻ drift region 3 of the first lateral MOSFET portion 31 reaches the first n ⁺ drain region 9 of the first lateral MOSFET portion 31 at a voltage of (½) Vo, and at the voltage of Vo. The extension of the depletion layer 17 extending to the n ⁻ drift region 3 of the second lateral MOSFET portion 32 reaches the second drain region 13 of the second lateral MOSFET portion 32, that is, the drain region of the lateral MOSFET 30 with a voltage of Vo.

Therefore, the voltage handled by the first lateral MOSFET unit 31 and the voltage handled by the second lateral MOSFET unit 32 are each (1/2) Vo.
Therefore, the breakdown voltage of the first lateral MOSFET 31 and the second lateral MOSFET portion 32 will be better half of the breakdown voltage _{V B} of the lateral MOSFET 30. Since the breakdown voltage is half that of the lateral MOSFET 30, the impurity concentration Cn of the n ⁻ drift region 3 constituting the first and second lateral MOSFET portions 31 and 32 can be increased. Further, by making the impurity concentration Cn high and by setting the breakdown voltage to half that of the lateral MOSFET 30, the lateral length X1 + X2 of the n ⁻ drift region 3 including the first and second lateral MOSFET portions 31 and 32 of the present invention is combined. Can be made the same as the lateral length X of the drift region of the conventional lateral MOSFET.

As described above, in the lateral MOSFET 30 of the present invention, the impurity concentration Cn can be made higher than that of the conventional lateral MOSFET 70. Therefore, when the breakdown voltage and the chip size are the same, the on-resistance Ron of the lateral MOSFET 30 of the present invention can be reduced.
Next, the case where the lateral MOSFET 30 of the present invention is turned on will be described. A voltage is applied between the source electrode (first source electrode 12) and the drain electrode (second drain electrode 13), and the first and second lateral MOSFET sections are applied to the first gate electrode 6 and the second gate electrode 11, respectively. By applying a gate voltage equal to or higher than the gate threshold voltages 31 and 32, the first and second lateral MOSFET sections 31 and 32 can be turned on simultaneously. However, in order to turn on the second lateral MOSFET section 32, the potential of the second gate electrode 11 needs to be equal to or higher than the gate threshold voltage with respect to the potential of the second source electrode (connection electrode 14).

Further, in the lateral MOSFET 30 of the present invention, since the on-resistance Ron can be reduced, a large drain current can flow.
In FIG. 1, the first n ⁺ drain region 9 is arranged from the second p base region 4 to the n ⁻ drift region 3. However, as shown in FIG. 3, the first n ⁺ drain region 9 is arranged in the second p base region 8. Instead, it may be disposed on the surface layer in the n ⁻ drift region 3. In this case, it is preferable in terms of breakdown voltage to cover the pn junction exposed portions of the second p base region 8 and the n − drift region 3 with the insulating film 19 so that the connection electrode 14 does not contact the pn junction.

In FIG. 1, the first n ⁺ drain region 9 and the second n ⁺ source region 10 are separated. However, as shown in FIG. 4, an n ⁺ region 19 that connects them may be disposed. In this case, a p ⁺ region 20 that penetrates the n + region 19 may be provided to electrically connect the connection electrode 14 and the second p base region 8.

FIG. 5 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from FIG. 1 is that n buffer regions 21 and 22 are provided around the first n ⁺ drain region 9 and the second n ⁺ drain region 7. In this way, the lengths X3 and X4 of the n ⁻ drift region of the first lateral MOSFET portion 31 and the second lateral MOSFET portion 32 can be shortened, and the chip size and the on-resistance can be reduced compared to FIG. Reduction can be achieved simultaneously.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. Explanatory diagram for explaining the operation of the lateral MOSFET of the present invention Cross-sectional view of the main part of a lateral MOSFET having a configuration different from that of FIG. Cross-sectional view of the main part of a lateral MOSFET having a configuration different from that of FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Cross-sectional view of the main part of a conventional high breakdown voltage lateral MOSFET using an SOI substrate Schematic diagram for explaining the relationship between each specification of the lateral MOSFET 70 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Oxide film 3 n ^- drift region 4 1p base region 5 1n ⁺ source region 6 1st gate electrode 7 2n ⁺ drain region 8 2p base region 9 1n ⁺ drain region 10 2n ⁺ source region DESCRIPTION OF SYMBOLS 11 2nd gate electrode 12 Source electrode 13 Drain electrode 14 Connection electrode 15, 16 Gate insulating film 17 Depletion layer 18 Insulating film 19 n ⁺ area | region 20 p ⁺ area | region 30 Horizontal MOSFET
31 1st lateral MOSFET part 32 2nd lateral MOSFET part 40 SOI substrate

Claims (4)

A first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type selectively provided in a surface layer of the first semiconductor region; and the second semiconductor in a surface layer of the first semiconductor region. A second conductive type third semiconductor region selectively provided apart from the region, a first conductive type fourth semiconductor region selectively provided on a surface layer of the second semiconductor region, and the first A fifth semiconductor region of a first conductivity type that is selectively provided between the second semiconductor region and the third semiconductor region so as to be separated from the second semiconductor region at a surface layer of the semiconductor region and to face the second semiconductor region. A sixth semiconductor region of a first conductivity type selectively provided in a surface layer of the third semiconductor region apart from the fifth semiconductor region; and the third semiconductor region in a surface layer of the first semiconductor region A seventh semiconductor region of the first conductivity type selectively provided apart from the first semiconductor region, and the fourth semiconductor A first gate electrode provided via a gate insulating film on the second semiconductor region sandwiched between the region and the first semiconductor region, and the sixth semiconductor region sandwiched between the sixth semiconductor region and the first semiconductor region. A second gate electrode provided on a third semiconductor region via a gate insulating film; a first main electrode provided in electrical contact with the second semiconductor region and the fourth semiconductor region; and the seventh semiconductor. A second main electrode provided in electrical contact with the region; and a connection electrode provided in electrical contact with the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region, respectively. A featured semiconductor device. The fifth semiconductor region is selectively provided on the surface layer of the third semiconductor region across the pn junction between the first semiconductor region and the second semiconductor region, or separated from the sixth semiconductor region. The semiconductor device according to claim 1, wherein the semiconductor device is selectively provided in contact with the region. The first semiconductor region, the second semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the first main electrode, the connection electrode, and the first gate electrode constitute a first lateral MOSFET portion, The first semiconductor region, the third semiconductor region, the sixth semiconductor region, the seventh semiconductor region, the connection electrode, the second main electrode, and the second gate electrode constitute a second lateral MOSFET portion, and the connection 3. The semiconductor device according to claim 1, wherein an electrode connects the first lateral MOSFET portion and the second lateral MOSFET portion in series. 4. The semiconductor device according to claim 3, wherein the connection electrode serves also as a drain electrode of the first lateral MOSFET part and a source electrode of the second lateral MOSFET part.

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