TWI469342B - Semiconductor device and operating method for the same - Google Patents

Description

Semiconductor structure and method of operation thereof

The present invention relates to semiconductor structures and methods of operation thereof, and more particularly to insulated gate bipolar transistors (IGBTs) and methods of operation thereof.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits.

Reducing the device area often severely compromises the electrical performance of the semiconductor structure. In order to maintain the electrical performance of the semiconductor structure, it is necessary to avoid the high voltage and leakage current of the high voltage device region from affecting the low voltage device and reducing the operational efficiency of the device.

A semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region, and a first gate structure. The first doped region has a first conductivity type. The second doped region encloses the first doped region and has a second conductivity type opposite to the first conductivity type. The third doped region has a first conductivity type. The fourth doped region has a second conductivity type. The first gate structure is located on the second doped region. The third doped region and the fourth doped region are respectively located in the second doped region and the first doped region on opposite sides of the first gate structure.

A method of operating a semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region, and a first gate structure. The first doped region has a first conductivity type. The second doped region encloses the first doped region and has a second conductivity type opposite to the first conductivity type. Third doping The impurity region has a first conductivity type. The fourth doped region has a second conductivity type. The first gate structure is located on the second doped region. The third doped region and the fourth doped region are respectively located in the second doped region and the first doped region on opposite sides of the first gate structure. The method of operation of the semiconductor structure includes the following steps. A first bias voltage is applied to the first gate structure. The fourth doped region is coupled to the first electrode. The first electrode is one of an anode and a cathode. The second doped region and the third doped region are coupled to the second electrode. The second electrode is the other of the anode and the cathode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. The first doped region 102 can include adjacent doping wells 104 and doping wells 106. In one embodiment, the doping well 104 and the doping well 106 have a first conductivity type, such as an N conductivity type. For example, the doping well 104 is a high pressure N-type well (HVNW).

The second doped region 108 can include adjacent doped wells 110, buried doped layers 112, doped wells 114, first doped layers 116, and doped contact regions 118. In one embodiment, the doping well 110, the buried doped layer 112, the doping well 114, the first doped layer 116, and the doped contact region 118 have a second conductivity type opposite to the first conductivity type, such as a P conductivity type. . For example, doping well 110 and doping well 114 are high voltage P-type doped regions (HVPD). The doped contact region 118 is heavily doped (P+).

In an embodiment, the doping well 110 , the buried doping layer 112 , the doping well 114 , the first doping layer 116 , and the doping contact region 118 of the second doping region 108 are surrounding the first doping region 102 . Doping well 104 and doping well 106.

The third doping region 120 is located at the doping well 114 of the second doping region 108, The first doped layer 116 is between the doped contact region 118. In an embodiment, the third doping region 120 has a first conductivity type such as an N conductivity type. For example, the third doped region 120 is a heavily doped (N+) contact region.

The fourth doped region 122 is disposed in the doping well 106 of the first doped region 102. In an embodiment, the fourth doping region 122 has a second conductivity type such as a P conductivity type. For example, the fourth doped region 122 is a heavily doped (P+) contact region.

The first gate structure 124 is on the doping well 114 between the doping well 104 and the third doping region 120.

The fifth doped region 126 can include adjacent doped contact regions 128, doped wells 130, doped wells 132, buried doped layers 134, and doped wells 136. In one embodiment, the doped contact region 128, the doping well 130, the doping well 132, the buried doped layer 134, and the doping well 136 have a first conductivity type, such as an N conductivity type. For example, the doped contact region 128 is heavily doped (N+). The doping well 136 is a high pressure N-type well (HVNW). In one embodiment, the doped contact region 128, the doping well 130, the doping well 132, the buried doping layer 134, and the doping well 136 of the fifth doping region 126 surround the second doping region 108, such as Figure 1 shows.

The sixth doped region 140 can include an adjacent base substrate 142, a buried doped region 144, a doping well 146, a second doped layer 148, and a doped contact region 150. In one embodiment, the base substrate 142, the buried doped region 144, the doping well 146, the second doped layer 148, and the doped contact region 150 have a second conductivity type, such as a P conductivity type. For example, the doping well 146 is a high pressure doped well (HVPD). The doped contact region 150 is heavily doped (P+).

The doped contact region 138 is disposed between the doping well 114 of the second doped region 108, the first doped layer 116, and the doped contact region 118. In an embodiment The doped contact region 138 has a first conductivity type such as an N conductivity type. For example, the doped contact region 138 is heavily doped (N+).

The doped contact region 152 is disposed between the doping well 146 of the sixth doped region 140, the second doped layer 148, and the doped contact region 150. In one embodiment, the doped contact region 152 has a first conductivity type, such as an N conductivity type. For example, the doped contact region 152 is heavily doped (N+).

The second gate structure 154 is disposed on the doping well 114, the doping well 136, and the doping well 146 between the doped contact region 138 and the doped contact region 152.

The top doped layer 156 can be disposed between the isolation layer 158 and the doping well 104 of the first doped region 102. In one embodiment, the top doped layer 156 has a second conductivity type, such as a P conductivity type. Conductive layer 162 can be disposed on isolation layer 158. Conductive layer 162 can include polysilicon. The isolation layer 160 can be disposed on the doping well 110 of the second doped region 108. The isolation layer 158 and the isolation layer 160 are not limited to the field oxide (FOX) shown in FIG. 1, and other suitable insulation structures such as shallow trench isolation may be used.

In an embodiment, the doped contact region 118 of the third doped region 120, the doped contact region 138, and the second doped region 108 may be coupled to an electrode 168, such as a cathode, and the voltage may be 0V, such as ground. The doped contact region 128 of the fourth doped region 122, the conductive layer 162 and the fifth doped region 126 may be coupled to the electrode 164 such as an anode, and the voltage may be between 0V and 700V. The first gate structure 124 can be coupled to an electrode 166 that provides a bias voltage of, for example, 0V~15V. The second gate structure 154 can be coupled to an electrode 170 that provides a bias voltage of 0V~15V. The doped contact region 150 of the doped contact region 152 and the sixth doped region 140 may be coupled to an electrode 172, such as a cathode, and the voltage may be 0V, such as ground.

In an embodiment, the semiconductor structure is used as an insulating gate bipolar transistor (IGBT) device. For example, the first gate structure 124 is a gate used as an IGBT, the fourth doping region 122 is an anode coupled to the IGBT, such as the electrode 164, and the third doping region 120 is a cathode coupled to the IGBT, such as the electrode 168. . The doping well 114 is coupled to the buried doped layer 112 below the doping well 104 and the doping well 110 positioned between the doping well 130 and the doping well 106. During high voltage operation of the IGBT device, the electrode 164 (anode) is lifted to form an inversion layer, and the hole current caused by the inversion layer is limited to the second conductivity type, for example, the P conductivity type buried doping layer 112 and the doping well 110. The hole flow is prevented from passing through the substrate 142 to affect other nearby devices such as low voltage (LV) devices.

The second gate structure 154 can be used as a gate of a double diffused gold oxide half field effect transistor (DMOS) for controlling the formation of a channel in the doping well 146 adjacent to the doped contact region 152, adjacent to the doped contact region. 138 is doped in well 114. In an embodiment, the IGBT device can be doped by the second gate structure 154 to form a via doped contact region 152, doped contact region 138, doping well 136, buried doped layer 134, doped well 132, doped Well 130, doped contact region 128 to provide additional current paths, that is, the IGBT device has multiple multi-channels to boost the anode (electrode 164) current of the IGBT device. In addition, the first conductivity type, such as the N conductivity type doping well 136, the buried doped layer 134, the doping well 132, the doping well 130, the doped contact region 128, and the second conductivity type, such as the P conductivity type doping well 114, the PN interface between the buried doping layer 112 and the doping well 110 can further limit the hole flow energy caused by the inversion layer in the buried doped layer 112 and the doping well 110 during the high voltage operation of the IGBT device. Avoiding hole flow through substrate 142 affects other nearby devices such as low voltage (LV) devices. In an embodiment, the IGBT device has a low turn on voltage and has a low turn-on Turn on resistance (Rdson-sp).

a first doped layer 116 between the doped contact region 118, the third doped region 120, the doped contact region 138 and the doping well 114, and the doped contact region 150, the doped contact region 152 and The second doped layer 148 between the doped wells 146 can avoid punch through during operation of the device.

The difference between the semiconductor structure of FIG. 2 and the semiconductor structure of FIG. 1 is that the isolation layer 174 in FIG. 1 is replaced by a deep trench isolation 276 surrounding the active region. For example, deep trench isolation 276 may be on the sides of doped contact region 128, doping well 130, doping well 132, and buried doped layer 134, and may extend to substrate 142 under buried doped layer 134. in. Additionally, deep trench isolation 276 may be on the sides of doped well 146 and buried doped region 144 and may extend into substrate 142 below buried doped region 144. Deep trench isolation 276 can suppress the substrate current between the HV IGBT device and other, for example, CMOS devices. Deep trench isolation 276 may be formed from a dielectric material.

The difference between the semiconductor structure of FIG. 3 and the semiconductor structure of FIG. 2 is that the buried insulating layer 378 is disposed under the buried doped layer 134 of the fifth doped region 126. The deep trench isolation 376 on the side of the doped contact region 128, the doping well 130, the doping well 132 and the buried doped layer 134, and the deep trench isolation on the side of the buried doped region 144 and the doping well 146 Adjacent to the buried insulating layer 378. In some embodiments, deep trench isolation 376 can extend into buried insulating layer 378. Deep trench isolation 376 and buried insulating layer 378 may be formed of a dielectric material. Deep trench isolation 376 and buried insulating layer 378 can inhibit substrate current between the IGBT device and other, for example, CMOS devices.

The difference between the semiconductor structure of Fig. 4 and the semiconductor structure of Fig. 1 is The fifth doped region 426A includes adjacent doped wells 136 and buried doped layers 434A. The fifth doped region 426B includes adjacent doped contact regions 128, doping wells 130, doping wells 132, and buried doped layers 434B. The doping well 136, the buried doped layer 434A, the doped contact region 128, the doping well 130, the doping well 132, and the buried doped layer 434B have a first conductivity type such as an N conductivity type. The buried doped layer 434A and the buried doped layer 434B are separated from each other by the buried doped layer 112 of the adjacent second doped region 108 and the base 142 of the sixth doped region 140. In one embodiment, the substrate 142 can be grounded, and the hole flow caused by the inversion layer during operation of the IGBT device can be collected through the buried doping layer 112 between the buried doped layer 434A and the buried doped layer 434B. To the substrate 142.

The semiconductor structure of FIG. 5 differs from the semiconductor structure of FIG. 4 in that the isolation layer 174 in FIG. 4 is replaced by a deep trench isolation 576 surrounding the active region. For example, deep trench isolation 576 can be on the sides of doped contact region 128, doping well 130, doping well 132, and buried doped layer 434B, and can extend to substrate 142 under buried doped layer 434B. in. Additionally, deep trench isolation 576 can be on the sides of doped well 146 and buried doped region 144 and can extend into substrate 142 below buried doped region 144. Deep trench isolation 576 can suppress the substrate current between the HV IGBT device and other, for example, CMOS devices.

The semiconductor structure of FIG. 6 differs from the semiconductor structure of FIG. 5 in that the buried insulating layer 678 is disposed under the buried doped layer 434B of the fifth doped region 426B. The deep trench isolation 676 on the side of the doped contact region 128, the doping well 130, the doping well 132 and the buried doped layer 434B, and the deep trench isolation on the side of the buried doped region 144 and the doping well 146 are 676 Adjacent to the buried insulating layer 678. In some embodiments, deep trench isolation 676 can be extended to bury In the edge layer 678. Deep trench isolation 676 and buried insulating layer 678 can inhibit substrate current between the IGBT device and other, for example, CMOS devices.

The semiconductor structure of FIG. 7 differs from the semiconductor structure of FIG. 1 in that the second gate structure 154, the doped contact region 138, the doped contact region 152, and the second doped layer 148 in FIG. 1 are omitted. The fifth doped region 726 can include adjacent doped contact regions 128, doped wells 130, doped wells 132, buried doped layers 134 and doped wells 136 and doped contact regions 780. In one embodiment, the doped contact region 128, the doping well 130, the doping well 132, the buried doped layer 134, and the doping well 136 and the doped contact region 780 have a first conductivity type, such as an N conductivity type. For example, the doped contact region 780 is heavily doped (N+). In one embodiment, the doped contact region 128 of the fifth doped region 726, the doping well 130, the doping well 132, the buried doped layer 134, and the doping well 136 and the doped contact region 780 are surrounded by the second Doped region 108 is as shown in FIG.

Referring to FIG. 7, in an embodiment, the doped contact region 150 on the doping well 146 is coupled to an electrode 172, such as a cathode, and the voltage can be 0V, such as ground. The doped contact region 780 is coupled to the electrode 782, such as a cathode, and the voltage can be between 0V and 15V. The doped contact region 118 and the third doped region 120 on the first doped layer 116 are coupled to an electrode 168, such as a cathode, and the voltage can be 0V, such as ground. The first gate structure 124 can be coupled to an electrode 166 that provides a bias voltage of, for example, 0V~15V. The doped contact region 128 of the fourth doped region 122, the conductive layer 162 and the fifth doped region 726 can be coupled to the electrode 164 such as an anode, and the voltage can be between 0V and 700V.

In an embodiment, the semiconductor structure is used as an insulated gate bipolar transistor (IGBT) device. For example, the first gate structure 124 is a gate used as an IGBT, and the fourth doping region 122 is an anode, such as an electrode, coupled to the IGBT. 164, the third doping region 120 is coupled to a cathode of the IGBT, such as the electrode 168. The doping well 114 is coupled to the buried doped layer 112 below the doping well 104 and the doping well 110 positioned between the doping well 130 and the doping well 106. During high voltage operation of the IGBT device, the electrode 164 (anode) is lifted to form an inversion layer, and the hole current caused by the inversion layer is limited to the second conductivity type, for example, the P conductivity type buried doping layer 112 and the doping well 110. The hole flow is prevented from passing through the substrate 142 to affect other nearby devices such as low voltage (LV) devices.

In an embodiment, the IGBT device can provide an additional current path by the opposite ends respectively coupled to the anode, such as the electrode 164 and the cathode, such as the fifth doped region 726 of the electrode 782, that is, the IGBT device has multiple current channels (multi -channel) to boost the anode (electrode 164) current of the IGBT device. In addition, the PN interface between the fifth conductivity region 726 of the first conductivity type, such as the N conductivity type, and the second dopant region 108 of the second conductivity type, such as the P conductivity type, can further reverse the process of operating the IGBT device at a high voltage. The hole flow caused by the layer can be confined in the buried doped layer 112 and the doping well 110 to prevent the hole flow from passing through the substrate 142 to affect other nearby devices such as low voltage (LV) devices. In an embodiment, the IGBT device has a low turn-on voltage and a low turn-on resistance (Rdson-sp).

The difference between the semiconductor structure of FIG. 8 and the semiconductor structure of FIG. 7 is that the isolation layer 174 of FIG. 7 is replaced by a deep trench isolation 876 surrounding the active region. For example, deep trench isolation 876 can be on the sides of doped contact region 128, doping well 130, doping well 132, and buried doped layer 134, and can extend to substrate 142 under buried doped layer 134. in. In addition, deep trench isolation 876 can be located on the sides of doped well 146 and buried doped region 144. Above, and may extend into the substrate 142 below the buried doped region 144. Deep trench isolation 876 can suppress the substrate current between the HV IGBT device and other, for example, CMOS devices.

The semiconductor structure of FIG. 9 differs from the semiconductor structure of FIG. 8 in that the buried insulating layer 978 is disposed under the buried doped layer 134 of the fifth doped region 726. The deep trench isolation 876 on the side of the doped contact region 128, the doping well 130, the doping well 132 and the buried doped layer 134, and the deep trench isolation 876 on the side of the buried doped region 144 and the doping well 146 Adjacent to 978. In some embodiments, deep trench isolation 876 can extend into buried insulating layer 978. Deep trench isolation 876 and buried insulating layer 978 can inhibit substrate current between the IGBT device and other, for example, CMOS devices.

The semiconductor structure of FIG. 10 differs from the semiconductor structure of FIG. 8 in that the fifth doped region 1026A includes adjacent doped wells 136 and buried doped layers 1034A. The fifth doped region 1026B includes adjacent doped contact regions 128, doping wells 130, doping wells 132, and buried doped layers 1034B. The doping well 136, the buried doped layer 1034A, the doped contact region 128, the doping well 130, the doping well 132, and the buried doped layer 1034B have a first conductivity type such as an N conductivity type. The buried doped layer 1034A and the buried doped layer 1034B are separated from each other by the buried doped layer 112 adjacent to the 108 and the substrate 142 of the sixth doped region 140. In one embodiment, the substrate 142 can be grounded, and the hole flow caused by the inversion layer during operation of the IGBT device can be collected through the buried doped layer 112 between the buried doped layer 1034A and the buried doped layer 1034B. To the substrate 142.

The semiconductor structure of FIG. 11 differs from the semiconductor structure of FIG. 10 in that the buried insulating layer 1178 is disposed under the buried doped layer 1034B of the fifth doped region 1026B. Doped contact region 128, doping well 130, doping well 132 The deep trench isolation 1176 on the side of the buried doped layer 1034B and the deep trench isolation 1176 on the side of the doped well 146 are adjacent to the buried trench 1178. In some embodiments, deep trench isolation 1176 can extend into buried insulating layer 1178. Deep trench isolation 1176 and buried insulating layer 1178 can inhibit substrate currents between the IGBT device and other, for example, CMOS devices.

In an embodiment, the semiconductor structure can operate as an IBGT, and the electrical properties can be as shown in FIG. 12 with a breakdown voltage of about 900 volts. The results of Fig. 13 show that the general IGBT (Comparative Example) has a large substrate leakage current under low voltage conditions, which affects adjacent devices such as low voltage devices. The semiconductor structure of the single channel of the embodiment (i.e., the second gate structure that does not use the gate used as the DMOS) has a low substrate leakage current at low anode currents. The semiconductor structure of the multi-channel (i.e., the second gate structure having the gate used as the DMOS) in the embodiment can have a higher anode current without increasing the substrate leakage current. The results of Fig. 14 show that the semiconductor structure of the multi-channel (i.e., the second gate structure having the gate used as the DMOS) in the embodiment can have a higher anode current without increasing the substrate leakage current. The IGBT semiconductor structure of an embodiment can be used to provide a high output current that can be applied to a motor driver as shown in FIG.

The embodiments are disclosed above, but are not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope of the patent application is subject to change.

102‧‧‧First doped area

104‧‧‧Doped well

106‧‧‧Doped well

108‧‧‧Second doped area

110‧‧‧Doped well

112‧‧‧ buried doped layer

114‧‧‧Doped well

116‧‧‧First doped layer

118‧‧‧Doped contact area

120‧‧‧ Third doped area

122‧‧‧fourth doping zone

124‧‧‧First gate structure

126, 426A, 426B, 726, 1026A, 1026B‧‧‧ fifth doped area

128‧‧‧Doped contact area

130‧‧‧Doped well

132‧‧‧Doped well

134, 434A, 434B, 1034A, 1034B‧‧‧ buried layer

136‧‧‧Doped well

138‧‧‧Doped contact area

140‧‧‧ sixth doping area

142‧‧‧Base

144‧‧‧ Buried doped area

146 ‧‧‧Doped well

148‧‧‧Second doped layer

150‧‧‧Doped contact area

152‧‧‧Doped contact area

154‧‧‧Second gate structure

156‧‧‧ top doped layer

158‧‧‧Isolation

160‧‧‧Isolation

162‧‧‧ Conductive layer

164‧‧‧electrode

166‧‧‧electrode

168‧‧‧electrode

170‧‧‧ electrodes

172‧‧‧electrode

174‧‧‧Isolation

276, 376, 576, 676, 876, 1176‧‧ ‧ deep trench isolation

378, 678‧‧‧ buried insulation

780‧‧‧Doped contact area

782‧‧‧electrode

978‧‧‧ buried insulation

1 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

2 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

3 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

4 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

FIG. 5 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 6 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

FIG. 7 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

8 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 9 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 10 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

11 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 12 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 13 shows the electrical properties of the semiconductor structure.

Figure 14 shows the electrical properties of the semiconductor structure of the embodiment.

Fig. 15 is a circuit diagram showing a semiconductor structure of an application embodiment.

102‧‧‧First doped area

104‧‧‧Doped well

106‧‧‧Doped well

108‧‧‧Second doped area

110‧‧‧Doped well

112‧‧‧ buried doped layer

114‧‧‧Doped well

116‧‧‧First doped layer

118‧‧‧Doped contact area

120‧‧‧ Third doped area

122‧‧‧fourth doping zone

124‧‧‧First gate structure

126‧‧‧ fifth doping area

128‧‧‧Doped contact area

130‧‧‧Doped well

132‧‧‧Doped well

134‧‧‧ buried doped layer

136‧‧‧Doped well

138‧‧‧Doped contact area

140‧‧‧ sixth doping area

142‧‧‧Base

144‧‧‧ Buried doped area

146‧‧‧Doped well

148‧‧‧Second doped layer

150‧‧‧Doped contact area

152‧‧‧Doped contact area

154‧‧‧Second gate structure

156‧‧‧ top doped layer

158‧‧‧Isolation

160‧‧‧Isolation

162‧‧‧ Conductive layer

164‧‧‧electrode

166‧‧‧electrode

168‧‧‧electrode

170‧‧‧ electrodes

172‧‧‧electrode

174‧‧‧Isolation

Claims (10)

A semiconductor structure comprising: a first doped region having a first conductivity type; a second doped region surrounding the first doped region and having a second conductivity type opposite to the first conductivity type a third doped region having the first conductivity type; a fourth doped region having the second conductivity type; a first gate structure on the second doped region, wherein the third doping region The impurity region and the fourth doping region are respectively located in the second doping region and the first doping region on opposite sides of the first gate structure. a fifth doped region having the first conductivity type; a sixth doped region having the second conductivity type; and a contact doping region having the first conductivity type and located in the sixth doping region . The semiconductor structure of claim 1, wherein the fifth doped region surrounds the second doped region. The semiconductor structure of claim 1, wherein the portion of the fifth doped region on the opposite side of the second doped region is coupled to an anode and a cathode, respectively. The semiconductor structure of claim 1, further comprising: a doped contact region having the first conductivity type, wherein the second doped region is between the fifth doped region and the doped contact region And a second gate structure located adjacent to the fifth doping region and the fifth doping The region is sandwiched by the portion of the doped contact region of the second doped region. The semiconductor structure of claim 1, further comprising a plurality of fifth doped regions having the first conductivity type, wherein the fifth dopings on opposite sides of the second doped region The zones are coupled to an anode and a cathode, respectively. A method of operating a semiconductor structure, wherein the semiconductor structure comprises: a first doped region having a first conductivity type; a second doped region surrounding the first doped region and having a opposite opposite to the first conductive region a second conductivity type; a third doped region having the first conductivity type; a fourth doped region having the second conductivity type; and a first gate structure located in the second doped region The third doped region and the fourth doped region are respectively located in the second doped region and the first doped region on the opposite side of the first gate structure ; a fifth doped region Having the first conductivity type; a sixth doped region having the second conductivity type; and a contact doping region having the first conductivity type and located in the sixth doping region; operation of the semiconductor structure The method includes: applying a first bias to the first gate structure; coupling the fourth doped region to a first electrode, the first electrode being one of an anode and a cathode; and the first The second doped region and the third doped region are coupled to a second electrode, the second electrode being the anode and the cathode Of another. The method of operating a semiconductor structure according to claim 6, wherein the fifth doped region surrounds the second doped region, wherein the method of operating the semiconductor structure further comprises: Portions on opposite sides of the two doped regions are coupled to the first electrode and the second electrode, respectively. The method of operating a semiconductor structure according to claim 6, wherein the semiconductor structure further comprises: a doped contact region having the first conductivity type, wherein the second doping region is between the fifth doping a region between the region and the doped contact region; and a second gate structure on a portion of the fifth doped region adjacent to the doped contact region of the fifth doped region with the second doped region The operating method of the semiconductor structure further includes: applying a second bias voltage to the second gate structure; coupling the fifth doping region to the first electrode; and coupling the doped contact region to the first Two electrodes. The method of operating a semiconductor structure according to claim 6, wherein the semiconductor structure further comprises: a second gate structure, the sixth doping between the fifth doped region and the doped contact region The operating region of the semiconductor structure further includes: applying a second bias voltage to the second gate structure; coupling the fifth doping region to the first electrode; and the doping contact region The sixth doping region is coupled to the second electrode. The method of operating a semiconductor structure according to claim 6, wherein the semiconductor structure further comprises a plurality of fifth doped regions having the first conductivity type and respectively located in the second doped region On the opposite side, the method of operating the semiconductor structure further includes coupling the fifth doped regions to the first electrode and the second electrode, respectively.