TWI509792B - Semiconductor device and operating method for the same - Google Patents

Description

Semiconductor device and method of operating same

The present invention relates to a semiconductor device and method of operating the same, and more particularly to an insulated gate bipolar transistor (IGBT) device and method of operation thereof.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor devices while improving the unit cost of speed, performance, density, and integrated circuits.

Reducing the device area often severely compromises the electrical performance of the semiconductor device. In order to maintain the electrical performance of the semiconductor device, in operation, it is necessary to avoid the high voltage and leakage current of the high voltage device region from affecting the low voltage device, and reduce the operational efficiency of the device.

A semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact, and a The first gate structure. The first doped region has a first conductivity type. The second doped region is adjacent to the first doped region and has a second conductivity type opposite to the first conductivity type. The first doped contact and the second doped contact are on the first doped region. There is a first PN junction between the first doped contact and the second doped contact. First A doped layer is located below the first doped contact or the second doped contact. The first doped layer has a second PN junction between the first doped contact or the second doped contact, adjacent to the first PN junction. The third doped contact has a first conductivity type and is disposed in the second doped region. The first gate structure is disposed on the second doping region between the first doping region and the third doping contact.

A method of operating a semiconductor device is provided. The semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact, and a first gate structure . The first doped region has a first conductivity type. The second doped region is adjacent to the first doped region and has a second conductivity type opposite to the first conductivity type. The first doped contact and the second doped contact are on the first doped region. There is a first PN junction between the first doped contact and the second doped contact. The first doped layer is located below the first doped contact or the second doped contact. The first doped layer has a second PN junction between the first doped contact or the second doped contact, adjacent to the first PN junction. The third doped contact has a first conductivity type and is disposed in the second doped region. The first gate structure is disposed on the second doping region between the first doping region and the third doping contact. The method of operation includes the following steps. A first bias is applied to the first gate structure. The first doped contact and the second doped contact are coupled to a first electrode. The first electrode is one of an anode and a cathode. The third doped contact is coupled to a second electrode. The second electrode is the other of the anode and the cathode.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧First doped area

104‧‧‧Second doped area

106, 106A, 106B‧‧‧ first doped layer

108‧‧‧First doped layer

110‧‧‧Second doping contact

112‧‧‧ Third doping contact

114‧‧‧First gate structure

116, 118, 120, 124, 140, 142, 146, 154, 580‧‧‧ doping wells

122, 144, 152‧‧‧ buried doped layer

126‧‧‧Second doped layer

128, 138, 158, 160, 162‧‧‧ contact areas

130‧‧‧First PN junction

132‧‧‧Second PN junction

134‧‧‧Isolation

136‧‧‧ Third doped area

148‧‧‧fourth doping zone

150‧‧‧Base

156‧‧‧ third doped layer

164‧‧‧Second gate structure

166‧‧‧ Conductive layer

168, 170, 172, 174, 176, 378‧‧ ‧ electrodes

682‧‧‧Reducing the surface electric field layer

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

2 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

3 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

4 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

5 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

6 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

Figures 7 and 8 show the electrical properties of the IBGT semiconductor device.

Fig. 9 is a circuit diagram showing a semiconductor device to which an embodiment is applied.

Please refer to FIG. 1 , which illustrates a cross-sectional view of a semiconductor device in accordance with an embodiment. The semiconductor device includes a first doped region 102 , a second doped region 104 , a first doped layer 106 , a first doped contact 108 , a second doped contact 110 , a third doped contact 112 , and a first gate structure 114 . .

The first doped region 102 can include adjacent doping wells 116 and doping wells 118. In one embodiment, the doping well 116 and the doping well 118 have a first conductivity type, such as an N conductivity type. For example, the doping well 116 is a high pressure N-type well (HVNW).

The second doping region 104 can include adjacent doping wells 120, buried doping layer 122, doping wells 124, second doping layer 126, and contact regions 128, all having a second conductivity type opposite to the first conductivity type. For example, the P conductivity type. For example, doping well 120 and doping well 124 are high voltage P-type doped regions (HVPD). Contact region 128 is heavily doped (P+). In one embodiment, the doping well 120, the buried doping layer 122, the doping well 124, the second doping layer 126, and the contact region 128 of the second doping region 104 are doped to surround the first doping region 102. The well 116 is doped with the doping well 118.

The first doped contact 108 and the second doped contact 110 are located on the doping well 118 of the first doped region 102. The first doped contact 108 and the second doped contact 110 have different conductivity types with a first PN junction 130 therebetween. In one embodiment, the first doped contact 108 and the second doped contact 110 form a shorted anode.

The first doped layer 106 is located below the first doped contact 108 and is located on the doping well 116 and the doping well 118 of the first doped region 102. A first PN junction 132 is formed between the first doped layer 106 and the first doped contact 108 adjacent to the first PN junction 130. The first PN junction 130 and the second PN junction 132 adjacent to each other form an L shape. In an embodiment, the first doped layer 106 has a second conductivity type such as a P conductivity type.

In this embodiment, the first doped contact 108 has a first conductivity type, such as an N conductivity type, and the second doped contact 110 has a second conductivity type, such as a P conductivity type. In one embodiment, the first doped contact 108 and the second doped contact 110 are heavily doped (P+) contact regions.

The third doped contact 112 is between the doping well 124 of the second doped region 104, the second doped layer 126, and the contact region 128. In one embodiment, the third doped contact 112 has a first conductivity type, such as an N conductivity type. For example, the third doped contact 112 is a heavily doped (N+) contact region.

The first gate structure 114 is on the doping well 124 between the doping well 116 and the third doping contact 112. The isolation layer 134 can be disposed on the first doped layer 106 and the doping well 116 of the first doped region 102. The spacer layer 134 is not limited to the field oxide (FOX) shown in FIG. 1, and other suitable insulating structures such as shallow trench isolation or the like may be used.

The semiconductor device can include a third doped region 136 that can include contiguous contact regions 138, doping wells 140, doping wells 142, buried doped layers 144, and doping wells 146, all having a first conductivity type such as N Conductive type. For example, contact region 138 is heavily doped (N+). The doping well 146 is a high pressure N-type well (HVNW). In one embodiment, the contact region 138 of the third doping region 136, the doping well 140, the doping well 142, the buried doping layer 144, and the doping well 146 surround the second doping region 104, such as the first The figure shows.

The semiconductor device can include a fourth doped region 148 that can include an adjacent substrate 150, a buried doped layer 152, a doping well 154, a third doped layer 156, and a contact region 158, each having a second conductivity type, such as P Conductive type. For example, the doping well 154 is a high pressure doped well (HVPD). Contact region 158 is heavily doped (P+).

Contact region 160 is disposed between doping well 124 of second doped region 104, second doped layer 126, and contact region 128. In one embodiment, the contact region 160 has a first conductivity type, such as an N conductivity type. For example, contact region 160 is heavily doped (N+).

The contact region 162 is disposed between the doping well 154 of the fourth doping region 148, the third doping layer 156, and the contact region 158. In one embodiment, the contact region 162 has a first conductivity type, such as an N conductivity type. For example, contact region 162 is heavily doped (N+).

The second gate structure 164 is disposed on the doping well 124, the doping well 146, and the doping well 154 between the contact region 160 and the contact region 162. Conductive layer 166 can be disposed on isolation layer 134. Conductive layer 166 can include polysilicon or other suitable material.

In an embodiment, the first doping contact 108, the second doping contact 110. The contact region 138 of the conductive layer 166 and the third doped region 136 can be coupled to the electrode 168. The third doping contact 112 , the contact region 160 and the contact region 128 of the second doping region 104 may be coupled to the electrode 170 . The first gate structure 114 can be coupled to the electrode 172. The second gate structure 164 can be coupled to the electrode 174. Contact region 158 of contact region 162 and fourth doped region 148 may be coupled to electrode 176.

In an embodiment, the semiconductor device is used as an insulated gate bipolar transistor (IGBT) device. The first gate structure 114 is a gate used as an IGBT. For example, during operation, electrode 168 is an anode and the voltage can range from 0V to 700V. Electrode 170 is a cathode and the voltage can be 0V, such as ground. The electrode 172 can provide a bias voltage of 0V~15V. Electrode 174 can provide a bias voltage of 0V~15V. Electrode 172 and electrode 174 can be a common electrode. Electrode 176 is the base electrode and the voltage can be 0V, such as ground.

During high voltage operation of the IGBT device, the electrode 168 (anode) is lifted to form an inversion layer, and the inversion layer causes a hole flow to be injected from the electrode 168 to amplify the electron flow. The first doped contact 108, the second doped contact 110, the first doped layer 106 and the doped well 118 of the first doped region 102 form an NPN bipolar structure (eg, a first doped contact 108, a second The doped well 118 doped with the contact 110 and the first doped region 102 forms an NPN bipolar structure, or the first doped contact 108, the first doped layer 106, and the doping well 118 of the first doped region 102 The constructed NPN bipolar structure can increase the hole flow and further increase the amplification rate of the device electron flow. This NPN bipolar structure can avoid unwanted voltage snapback or negative differential resistance (NDR) effects of IGBT devices. The (P-conducting) first doped layer 106 extending under the isolation layer 134 and adjacent to the first gate structure 114 can provide a flow path for the hole flow near the electrode 170 (cathode) to prevent the hole flow from passing through the substrate 150. Other devices in the vicinity, such as low voltage (LV) devices.

The second gate structure 164 can be used as a gate of a double diffused gold oxide half field effect transistor (DMOS) for controlling the formation of a channel in the doping well 154 adjacent to the contact region 162 and doping adjacent to the contact region 160. Well 124. In an embodiment, the IGBT device can be formed by the second gate structure 164 to form a via, the contact region 162, the contact region 160, the doping well 146, the buried doped layer 144, the doping well 142, the doping well 140, the contact Region 138 provides an additional current path, i.e., the IGBT device has multiple multi-channels to boost the anode current of the IGBT device.

The (P-conducting) buried doping layer 122 and the doping well 120 near the electrode 168 (anode) can also help to confine the hole flow, avoiding the hole flow through the substrate 150 and affecting other devices in the vicinity. In addition, a first conductivity type such as an N conductivity type doping well 146, a buried doped layer 144, a doping well 142, a doping well 140, a contact region 138, and a second conductivity type, such as a P conductivity type doping well 124, The PN junction between the buried doping layer 122 and the doping well 120 can further limit the hole flow energy caused by the inversion layer in the buried doped layer 122 and the doping well 120 during high voltage operation of the IGBT device, thereby avoiding The hole flow passes through the substrate 150 to affect other devices in the vicinity.

In an embodiment, the IGBT device has a low turn-on voltage and a low turn-on resistance (Rdson-sp).

a second doped layer 126 between the contact region 128, the third doped contact 112, the contact region 160 and the doping well 124, and a portion between the contact region 158, the contact region 162, and the doping well 154 The three doped layer 156 can avoid punch through during operation of the device.

2 is a cross-sectional view of a semiconductor device in accordance with an embodiment, The difference from the semiconductor device shown in Fig. 1 is explained below. Referring to FIG. 2, the first doped layer 106A is adjacent to the first doped contact 108 and the second doped contact 110. In one embodiment, the second doped contact 110 has a first conductivity type, such as an N conductivity type, and the first doped contact 108 and the first doped layer 106A have a second conductivity type, such as a P conductivity type. In another embodiment, the first doped contact 108 has a first conductivity type, such as an N conductivity type, and the second doped contact 110 and the first doped layer 106A have a second conductivity type, such as a P conductivity type. During operation of the IGBT device, the first doped contact 108, the second doped contact 110, the first doped layer 106A, and the doped well 118 of the first doped region 102 form an NPN bipolar structure (eg, first The doped well 108 doped with the contact 108, the first doped layer 106A and the first doped region 102, or an NPN bipolar structure, or the second doped contact 110, the first doped layer 106A, and the first doping The NPN bipolar structure formed by the doping well 118 of the region 102 can increase the hole flow injected from the electrode 168 and increase the amplification of the device electron current. This NPN bipolar structure can avoid undesired voltage snaps or negative differential resistance effects of IGBT devices. The (P-conductivity) first doped layer 106A extending under the isolation layer 134 and adjacent to the first gate structure 114 can provide a flow path for the hole flow near the electrode 170 (cathode), preventing the hole flow from passing through the substrate 150 and affecting the vicinity Other devices.

Fig. 3 is a cross-sectional view showing a semiconductor device according to an embodiment, and the difference from the semiconductor device shown in Fig. 1 is explained as follows. The semiconductor device of FIG. 3 omits the second gate structure 164, the contact region 160, the contact region 162, and the third doping layer 156 in FIG. The doping well 146 of the third doped region 136 is coupled to the electrode 378.

4 is a cross-sectional view showing a semiconductor device according to an embodiment, and the difference from the semiconductor device shown in FIG. 3 is explained as follows. Please refer to Figure 4, The first doped layer 106A is adjacent to the first doped contact 108 and the second doped contact 110. In one embodiment, the second doped contact 110 has a first conductivity type, such as an N conductivity type, and the first doped contact 108 and the first doped layer 106A have a second conductivity type, such as a P conductivity type. In another embodiment, the first doped contact 108 has a first conductivity type, such as an N conductivity type, and the second doped contact 110 and the first doped layer 106A have a second conductivity type, such as a P conductivity type. During operation of the IGBT device, the first doped contact 108, the second doped contact 110, the first doped layer 106A, and the doped well 118 of the first doped region 102 form an NPN bipolar structure (eg, first The doped well 108 doped with the contact 108, the first doped layer 106A and the first doped region 102, or an NPN bipolar structure, or the second doped contact 110, the first doped layer 106A, and the first doping The NPN bipolar structure formed by the doping well 118 of the region 102 can increase the hole flow injected from the electrode 168 and increase the amplification of the device electron current. This NPN bipolar structure can avoid undesired voltage snaps or negative differential resistance effects of IGBT devices. The (P-conductivity) first doped layer 106A extending under the isolation layer 134 and adjacent to the first gate structure 114 can provide a flow path for the hole flow near the electrode 170 (cathode), preventing the hole flow from passing through the substrate 150 and affecting the vicinity Other devices.

Fig. 5 is a cross-sectional view showing a semiconductor device according to an embodiment, and the difference from the semiconductor device shown in Fig. 3 is explained as follows. The semiconductor device shown in Fig. 5 is a buried doped layer 144 of the first conductivity type, for example, N conductivity type, which is omitted in Fig. 3. Furthermore, the buried doped layer 122 in FIG. 3 is replaced by a doping well 580 of a second conductivity type such as a P conductivity type.

Fig. 6 is a cross-sectional view showing a semiconductor device according to an embodiment, and the difference from the semiconductor device shown in Fig. 1 is explained as follows. The first doped layer 106B is located below the first doped contact 108 and is located in the doping well of the first doped region 102 118 on. The first doped layer 106B does not extend below the isolation layer 134. In one embodiment, the first doped contact 108 has a first conductivity type, such as an N conductivity type, and the second doped contact 110 and the first doped layer 106B have a second conductivity type, such as a P conductivity type. The first doping contact 108, the second doping contact 110, the first doping layer 106B and the doping well 118 of the first doping region 102 constitute an NPN structure (eg, the first doping contact 108, the first doping layer) 106B and the NPN bipolar structure formed by the doping well 118 of the first doping region 102, or the NPN formed by the doping well 118 of the first doping contact 108, the second doping contact 110 and the first doping region 102 A bipolar structure) that increases the flow of holes injected from the electrode 168 to increase the amplification of the electron flow of the device and avoid undesirable voltage snaps or negative differential resistance effects of the IGBT device. The first doped layer 106B is a reduced surface electric field (RESURF) layer 682 that is separated from the isolation layer 134, wherein the RESURF layer 682 has a second conductivity type, such as a P conductivity type.

Figures 7 and 8 show the electrical properties of the IBGT semiconductor device. Wherein the IBGT semiconductor device of Embodiment 1 uses a first doped layer extending below the isolation layer, and the IBGT semiconductor device of Embodiment 2 uses a first doped layer that does not extend below the isolation layer, and the IBGT semiconductor device of Comparative Example 3 does not have A first doped layer is used. From the curves shown in Figs. 7 and 8, it is found that the IBGT semiconductor device of the embodiment has the advantages of saving power and increasing the output current, and can avoid the voltage snapback effect of the comparative example. The IGBT semiconductor device of the embodiment can be applied to (for example, a half bridge, full bridge) motor driver as shown in FIG.

In an embodiment, for example, the gate electrode of the gate structure of the semiconductor device may include a suitable material such as polysilicon, metal, metal halide, or the like. The substrate may include an insulating layer overlying germanium (SOI). The semiconductor device can utilize a local oxidation of silicon (SOI) process and shallow trench isolation (shallow trench isolation) Isolation; SOI) process, deep trench isolation (DTI) process, overlying insulating process, epitaxial process, non-epilation process, or other suitable process. The semiconductor device can be designed as a hexagonal, octagonal, circular, runway, or other suitable shaped structure.

The embodiments are disclosed above, but are not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope of the patent application is subject to change.

102‧‧‧First doped area

104‧‧‧Second doped area

106‧‧‧First doped layer

108‧‧‧First doped layer

110‧‧‧Second doping contact

112‧‧‧ Third doping contact

114‧‧‧First gate structure

116, 118, 120, 124, 140, 142, 146, 154‧‧‧ doping wells

122, 144, 152‧‧‧ buried doped layer

126‧‧‧Second doped layer

128, 138, 158, 160, 162‧‧‧ contact areas

130‧‧‧First PN junction

132‧‧‧Second PN junction

134‧‧‧Isolation

136‧‧‧ Third doped area

148‧‧‧fourth doping zone

150‧‧‧Base

156‧‧‧ third doped layer

164‧‧‧Second gate structure

166‧‧‧ Conductive layer

168, 170, 172, 174, 176‧‧ ‧ electrodes

Claims (10)

A semiconductor device comprising: a first doped region having a first conductivity type; a second doped region adjacent to the first doped region and having a second conductivity type opposite to the first conductivity type; a first doping contact; a second doping contact adjacent to the first doping contact, wherein the first doping contact and the second doping contact are located on the first doping region, the first doping Having a first PN junction between the contact and the second doped contact; a first doped layer under the first doped contact or the second doped contact, wherein the first doped layer is Having a second PN junction between the first doped contact or the second doped contact, adjacent to the first PN junction, and the first doped layer extends over the first doped region and the Between the first junctions, the first doped layer and the first doped region have opposite conductivity types; a third doped contact having the first conductivity type and disposed in the second doped region And a first gate structure disposed on the second doped region between the first doped region and the third doped contact. The semiconductor device of claim 1, wherein the first PN junction and the second PN junction adjacent to each other form an L shape. The semiconductor device of claim 1, further comprising an isolation layer disposed between the first doping contact and the third doping contact, wherein the first A doped layer is between the isolation layer and the first doped region. The semiconductor device according to claim 1, which is used as an insulated gate bipolar transistor (IGBT) device. The semiconductor device of claim 1, wherein the first doping contact is closer to the first gate structure than the second doping contact, and the second doping contact has the first conductivity type, the first A doped contact and the first doped layer have the second conductivity type, the first doped layer being adjacent to the first doped contact and the second doped contact. The semiconductor device of claim 1, wherein the first doping contact is closer to the first gate structure than the second doping contact, the first doping contact having the first conductivity type, the first The doped contact and the first doped layer have the second conductivity type, the first doped layer being adjacent to the underside of the first doped contact. The semiconductor device of claim 1, wherein the first doped layer and the second doped region are separated from each other by the first doped region. The semiconductor device of claim 1, wherein the first doping contact and the second doping contact are electrically connected to one of an anode and a cathode, and the third doping contact is electrically Connected to the anode and the other of the cathodes. The semiconductor device of claim 1, wherein the first doping contact, the first doped layer and the first doped region constitute an NPN structure, the second doping contact, the first doping The layer and the first doped region constitute an NPN structure, or the first doped contact, the second doped contact, and the first doped region constitute an NPN structure. A method of operating a semiconductor device, wherein the semiconductor device comprises: a first doped region having a first conductivity type; a second doped region adjacent to the first doped region and having a second conductivity type opposite to the first conductivity type; a first doped contact a second doping contact adjacent to the first doping contact, wherein the first doping contact and the second doping contact are located on the first doping region, the first doping contact and the second doping Having a first PN junction between the impurity contacts; a first doped layer under the first doped contact or the second doped contact, wherein the first doped layer is in contact with the first doping Or a second PN junction between the second doping contacts adjacent to the first PN junction, and the first doped layer extends between the first doped region and the first junction The first doped layer and the first doped region have opposite conductivity types; a third doped contact having the first conductivity type and disposed in the second doped region; and a first gate a structure disposed on the second doped region between the first doped region and the third doped contact, the method comprising: applying a first bias to a first gate structure; the first doping contact and the second doping contact are coupled to a first electrode, the first electrode is one of an anode and a cathode; and the third doping contact is coupled To a second electrode, the second electrode is the other of the anode and the cathode.