TWI570916B - Semiconductor structure - Google Patents

Description

Semiconductor structure 【0001】

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including an insulated gate bipolar transistor (IGBT).

【0002】

High voltage power ICs are used in switching power supplies (SMPS), lighting, motor control, and plasma drive. Higher efficiency, better reliability, better strain and lower system-level cost are all sought after. Lateral IGBTs are widely used in power integrated circuit technology. The lateral IGBT combines the advantages of both double diffused metal oxide semiconductor (DMOS) and bipolar transistors, such as high input impedance and good gate control (advantages of DMOS), and low on-state voltage drop. Has a high current level (the advantage of a bipolar transistor). In addition, lateral IGBTs have lower on-state resistance (Ron) than DMOS, thus reducing on-state losses. Multi-channel lateral IGBTs have reduced forward voltage drop due to their more channels. Vertical IGBTs have lower conduction state losses than lateral IGBTs.

[0003]

In the present specification, a semiconductor structure including an improved IGBT is provided.

[0004]

According to an embodiment, a semiconductor structure includes a substrate, a first doped region, a first well, a second doped region, a plurality of first heavily doped regions, a plurality of electrical conductors, and a plurality of dielectrics, a first a double doped region, a third heavily doped region, a fourth heavily doped region, and a first gate electrode and a first gate dielectric. The first doped region is formed in the substrate. The first doped region has a first doping type. The first well is formed in the substrate. The first well has a first doping type. A second doped region is formed in the substrate and surrounds the first doped region. The second doped region separates the first well from the first doped region. The second doped region has a second doping type. The first heavily doped region is formed in the first doped region. The first heavily doped region has a second doping type. The electrical conductor and the dielectric are formed on the substrate and interposed between the first heavily doped regions. A conductive system is formed on the dielectric. The second heavily doped region is formed in the first well. The second heavily doped region has a first doping type. The third heavily doped region is formed in the second doped region. The third heavily doped region has a second doping type. The fourth heavily doped region is formed in the second doped region and adjacent to the third heavily doped region. The fourth heavily doped region has a first doping type. The first gate electrode and the first gate dielectric are formed on the substrate and interposed between the first heavily doped region and the fourth heavily doped region. The first gate electrode is formed on the first gate dielectric.

[0005]

In accordance with another embodiment, a semiconductor structure includes a substrate and an IGBT. The IGBT includes a first doped region, a first well, a second doped region, a plurality of first heavily doped regions, a plurality of electrical conductors and a plurality of dielectrics, a second heavily doped region, and a first a triple doped region, a fourth heavily doped region, and a first gate electrode and a first gate dielectric. The first doped region is formed in the substrate. The first doped region has a first doping type. The first well is formed in the substrate. The first well has a first doping type. A second doped region is formed in the substrate and surrounds the first doped region. The second doped region separates the first well from the first doped region. The second doped region has a second doping type. The first heavily doped region is formed in the first doped region. The first heavily doped region is formed in the first doped region. The first heavily doped region has a second doping type. The electrical conductor and the dielectric are formed on the substrate and interposed between the first heavily doped regions. A conductive system is formed on the dielectric. The second heavily doped region is formed in the first well. The second heavily doped region has a first doping type. The third heavily doped region is formed in the second doped region. The third heavily doped region has a second doping type. The fourth heavily doped region is formed in the second doped region and adjacent to the third heavily doped region. The fourth heavily doped region has a first doping type. The first gate electrode and the first gate dielectric are formed on the substrate and interposed between the first heavily doped region and the fourth heavily doped region. The first gate electrode is formed on the first gate dielectric. The first heavily doped region and the second heavily doped region are electrically connected and serve as an anode of the IGBT, and the third heavily doped region and the fourth heavily doped region are electrically connected and serve as a cathode of the IGBT.

[0006]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0028]

100‧‧‧Semiconductor structure
102‧‧‧Substrate
104‧‧‧First doped area
106‧‧‧First Well
108‧‧‧Second doped area
110‧‧‧Second well
112‧‧‧ third well
114‧‧‧fourth well
116‧‧‧First buried layer
118‧‧‧ fifth well
120‧‧‧First heavily doped area
122‧‧‧Electric conductor
124‧‧‧Dielectric
126‧‧‧Second heavily doped area
128‧‧‧ Third heavily doped area
130‧‧‧4th heavily doped area
132‧‧‧First gate electrode
134‧‧‧First gate dielectric
136‧‧‧ sixth well
138‧‧‧Second buried layer
140‧‧‧The seventh well
142‧‧‧eighth well
144‧‧‧ fifth heavily doped area
146‧‧‧Doped layer
148‧‧‧ sixth heavily doped area
150‧‧‧ seventh heavily doped area
152‧‧‧second gate electrode
154‧‧‧Second gate dielectric
156‧‧ ‧ field oxide layer
158‧‧‧First field oxide
160‧‧‧Second field oxide
162‧‧‧The third field oxide
200‧‧‧Semiconductor structure
300‧‧‧Semiconductor structure
364‧‧‧ buried oxide
366‧‧‧ field board
400‧‧‧Semiconductor structure
402‧‧‧Anode
404‧‧‧ cathode
406‧‧‧ gate

【0007】

1 and 2 are schematic views of a semiconductor structure in accordance with an embodiment.
Figure 3 is a schematic illustration of a semiconductor structure in accordance with an embodiment.
Figure 4 is a schematic illustration of a semiconductor structure in accordance with an embodiment.
Figure 5 is a schematic illustration of a semiconductor structure in accordance with an embodiment.
6 to 8 are characteristic diagrams of an example according to the present invention and a comparative example thereof.
Figure 9 is an application diagram of a semiconductor structure in accordance with an embodiment.

[0008]

Please refer to FIG. 1 , which illustrates a semiconductor structure 100 in accordance with an embodiment. The semiconductor structure 100 includes a substrate 102, a first doped region 104, a first well 106, a second doped region 108, a plurality of first heavily doped regions 120, a plurality of electrical conductors 122, and a plurality of dielectric materials 124, A second heavily doped region 126, a third heavily doped region 128, a fourth heavily doped region 130, and a first gate electrode 132 and a first gate dielectric 134.

【0009】

The first doping region 104 is formed in the substrate 102. The first doped region 104 can include a second well 110 and a third well 112. The third well 112 is adjacent to the second well 110 and extends below the second well 110. The doping concentration of the second well 110 is higher than the doping concentration of the third well 112. The first well 106 is formed in the substrate 102. The second doped region 108 is formed in the substrate 102 and surrounds the first doped region 104. The second doped region 108 separates the first well 106 from the first doped region 104. The second doping region 108 can include a fourth well 114, a first buried layer 116, and a fifth well 118. The fourth well 114 separates the first well 106 from the first doped region 104. The fifth well 118 is separated from the fourth well 114. The first buried layer 116 connects the fourth well 114 and the fifth well 118.

[0010]

The first heavily doped region 120 is formed in the first doped region 104. More specifically, the first heavily doped region 120 is formed in the second well 110. A second heavily doped region 126 is formed in the first well 106. A third heavily doped region 128 is formed in the second doped region 108. The fourth heavily doped region 130 is adjacent to the third heavily doped region 128 and adjacent to the third heavily doped region 128. More specifically, the third heavily doped region 128 and the fourth heavily doped region 130 are formed in the fifth well 118.

[0011]

The first doping region 104, the first well 106, the second heavily doped region 126, and the fourth heavily doped region 130 have a first doping type. The second doped region 108, the first heavily doped region 120, and the third heavily doped region 128 have a second doping type. The substrate 102 can have a second doping type. The first doping type may be an n-type and the second doping type may be a p-type. According to an embodiment, the first well 106 and the third well 112 may be high pressure n-type wells, the second well 110 may be an n-type well, and the fourth well 114 and the fifth well 118 may be high pressure deep p-type wells, first The buried layer 116 can be a p-type buried layer.

[0012]

In one embodiment, the first well 106 has a doping concentration of 10 ¹² cm ^-2 to 10 ¹³ cm ^-2 , and the second well 110 has a doping concentration of 10 ¹³ cm ^-2 to 10 ¹⁵ cm ^-2 , and a third The doping concentration of the well 112 is 10 ¹² cm ^-2 ~ 10 ¹³ cm ^-2 , the doping concentration of the fourth well 114 is 10 ¹² cm ^-2 ~ 10 ¹³ cm ^-2 , and the doping concentration of the fifth well 118 is 10 ¹² cm ^-2 ~ 10 ¹³ cm ^-2 , the doping concentration of the first buried layer 116 is 10 ¹² cm ^-2 ~ 10 ¹⁴ cm ^-2 , and the doping concentration of the first heavily doped region 120 is

10 ¹⁴ cm ^-2 ~ 10 ¹⁵ cm ^-2 , the doping concentration of the second heavily doped region 126 is 10 ¹⁴ cm ^-2 ~ 10 ¹⁵ cm ^-2 , and the doping concentration of the third heavily doped region 128 is 10 ¹⁴ cm ^-2 ~ 10 ¹⁵ cm ^-2, a fourth doping concentration of the heavily doped region 130 is ^{10 14 cm -2 ~ 10 15 cm} -2.

[0013]

The electrical conductor 122 and the dielectric 124 are formed on the substrate 102 and interposed between the first heavily doped regions 120. Conductor 122 is formed on dielectric 124. The electrical conductor 122 may be formed of polycrystalline silicon, a metal or a poly-silicide or the like.

[0014]

The first gate electrode 132 and the first gate dielectric 134 are formed on the substrate 102 and interposed between the first heavily doped region 120 and the fourth heavily doped region 130. The first gate electrode 132 is formed on the first gate dielectric 134. The first gate electrode 132 may be formed of polycrystalline germanium, a metal or a polycrystalline germanide or the like.

[0015]

The first doped region 104, the first well 106, the second doped region 108, the first heavily doped region 120, the electrical conductor 122 and the dielectric 124, the second heavily doped region 126, and the third heavily doped region 128. The fourth heavily doped region 130 and the first gate electrode 132 and the first gate dielectric 134 may constitute an IGBT, and more specifically, a junction-isolated lateral IGBT (Junction-isolated lateral IGBT, JI -LIGBT). At this time, the first heavily doped region 120 and the second heavily doped region 126 are electrically connected and serve as an anode of the IGBT, and the third heavily doped region 128 and the fourth heavily doped region 130 are electrically connected and serve as an IGBT. Cathode.

[0016]

The first heavily doped region 120 and the second well 110 may constitute a complex parasitic PNP bipolar junction transistor (BJT), as shown in FIG. As a result, the current contributed by the hole increases, and thus the total current increases and Ron decreases. In addition, the electrical conductors 122 contribute to current distribution. With such a structure, the characteristic on-state resistance (Ron, sp) and BVdss characteristics can be improved. Also, the substrate current is suppressed.

[0017]

The semiconductor structure 100 can also include a sixth well 136. A sixth well 136 is formed in the substrate 102 and adjacent to the fifth well 118. The sixth well 136 has a first doping type. The sixth well 136 can be a high pressure n-type well. The semiconductor structure 100 can also include a second buried layer 138. The second buried layer 138 connects the first well 106 and the sixth well 136. The second buried layer 138 has a first doping type. The second buried layer 138 may be an n-type buried layer. In one embodiment, the doping concentration of the sixth well 136 is 10 ¹² cm ^-2 to 10 ¹³ cm ^-2 , and the doping concentration of the second buried layer 138 is 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . The second buried layer 138 connects the fourth well 114 and the sixth well 136 to form a current path and suppress substrate current.

[0018]

The semiconductor structure 100 can also include a seventh well 140, an eighth well 142, and a fifth heavily doped region 144. The seventh well 140 is formed on the substrate 102. The seventh well 140 has a first doping type. The seventh well 140 can be a high pressure n-type well. An eighth well 142 is formed in the substrate 102 and between the sixth well 136 and the seventh well 140. The eighth well 142 has a second doping type. The eighth well 142 can be a high pressure deep p-type well. A fifth heavily doped region 144 is formed in the eighth well 142. The fifth heavily doped region 144 has a second doping type. In one embodiment, the doping concentration of the seventh well 140 is 10 ¹² cm ^-2 ~ 10 ¹³ cm ^-2 , and the doping concentration of the eighth well 142 is 10 ¹² cm ^-2 ~ 10 ¹³ cm ^-2 , fifth The heavily doped region 144 has a doping concentration of 10 ¹⁴ cm ^-2 to 10 ¹⁵ cm ^-2 . The semiconductor structure 100 can also include a doped layer 146. A doped layer 146 is formed in the third well 112. The doped layer 146 can be a p-top layer.

[0019]

The semiconductor structure 100 can further include a sixth heavily doped region 148, a seventh heavily doped region 150, and a second gate electrode 152 and a second gate dielectric 154. A sixth heavily doped region 148 is formed in the fifth well 118 and adjacent to the third heavily doped region 128. The sixth heavily doped region 148 has a first doping type. A seventh heavily doped region 150 is formed in the eighth well 142 and adjacent to the fifth heavily doped region 144. The seventh heavily doped region 150 has a first doping type. The second gate electrode 152 and the second gate dielectric 154 are formed on the substrate 102 and interposed between the sixth heavily doped region 148 and the seventh heavily doped region 150. The second gate electrode 152 is formed on the second gate dielectric 154. The second gate electrode 152 may be formed of polycrystalline germanium, a metal or a polycrystalline germanide or the like. In one embodiment, the doping concentration of the sixth heavily doped region 148 is 10 ¹⁴ cm ^-2 to 10 ¹⁵ cm ^-2 , and the doping concentration of the seventh heavily doped region 150 is

To ^{10 14 cm -2 ~ 10 15 cm} -2. The sixth heavily doped region 148, the seventh heavily doped region 150, and the second gate electrode 152 and the second gate dielectric 154 may constitute a DMOS. This DMOS is connected to the sixth well 136 and further connected to the first well 106 which is part of the anode. As a result, the anode current can be further increased, and the substrate current can be further suppressed.

[0020]

Semiconductor structure 100 can also include a field oxide layer 156. A field oxide layer 156 is formed on the substrate 102. Field oxide layer 156 includes a first field oxide 158, a second field oxide 160, and a third field oxide 162. A first field oxide 158 is formed on the fourth well 114. A second field oxide 160 is formed on the third well 112. A portion of the first gate electrode 132 is formed on the second field oxide 160. A third field oxide 162 is formed on the seventh well 140. Although the field oxide layer 156 is illustrated in the drawings, other isolation methods such as shallow trench isolation (STI) or deep trench isolation (DTI) may be employed.

[0021]

Please refer to FIG. 3, which illustrates a semiconductor structure 200 in accordance with an embodiment. The difference between the semiconductor structure 200 and the semiconductor structure 100 is that there is no DMOS structure in the semiconductor structure 200. That is, the sixth heavily doped region 148, the seventh heavily doped region 150, and the second gate electrode 152 and the second gate dielectric 154 are not present in the semiconductor structure 200.

[0022]

Please refer to FIG. 4, which illustrates a semiconductor structure 300 in accordance with an embodiment. There is no second buried layer 138 in the semiconductor structure 300. The semiconductor structure 300 can be fabricated by a silicon-on-insulator (SOI) process and includes a buried oxide 364. Buried oxide 364 is formed under first well 106, first doped region 104, second doped region 108, and sixth well 136. Additionally, semiconductor structure 300 includes a plurality of field plates 366. Field plate 366 is formed on second field oxide 160 in the drift region of semiconductor structure 300 to provide a reduced surface field (RESURF) structure in semiconductor structure 300. Field plate 366 can be formed from polysilicon.

[0023]

The fabrication of the semiconductor structure according to the present invention may employ a widely used process such as a local oxidation of silicon (LOCOS) process, an SOI process, an epitaxial process, a non-epitaxial process, an STI process, or a DTI process, etc. . Thus, the fabrication of semiconductor structures in accordance with the present invention can be compatible with the fabrication of other devices, such as 700 V power CMOS.

[0024]

Although a rectangular configuration type is described in the foregoing embodiments, the semiconductor structure according to the present invention may have other configurations such as a hexagon, an octagon, a circle, or a racetrack. FIG. 5 illustrates a circular example of a semiconductor structure 400 including an anode 402, a cathode 404, and a gate 406.

[0025]

Referring now to Figures 6-8, the characteristics of the examples according to the present invention and their comparative examples are shown. As shown in Fig. 6, the example according to the present invention can be applied to a case where a breakdown voltage higher than 700 V is required. As shown in Fig. 7, the anode current system according to the example of the present invention is further increased. As shown in Figure 8, the substrate current is less than about 10 ^-6 A/um until the anode voltage is 15 V.

[0026]

In the semiconductor structure according to the present invention, Ron, sp can be lowered due to the arrangement of the parasitic BJT structure, and thus the conduction state loss can be remarkably reduced. In addition, a low on-voltage can be obtained. For example, in the case of Vgs > Vth, Vds can be 0 V. Such a semiconductor structure can be applied to a motor driver (whether in a half bridge circuit or a full bridge circuit) as shown in FIG. Alternatively, such a semiconductor structure can also be applied to a light emitting diode driver or a current driver or the like.

[0027]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧Semiconductor structure

102‧‧‧Substrate

104‧‧‧First doped area

106‧‧‧First Well

108‧‧‧Second doped area

110‧‧‧Second well

112‧‧‧ third well

114‧‧‧fourth well

116‧‧‧First buried layer

118‧‧‧ fifth well

120‧‧‧First heavily doped area

122‧‧‧Electric conductor

124‧‧‧Dielectric

126‧‧‧Second heavily doped area

128‧‧‧ Third heavily doped area

130‧‧‧4th heavily doped area

132‧‧‧First gate electrode

134‧‧‧First gate dielectric

136‧‧‧ sixth well

138‧‧‧Second buried layer

140‧‧‧The seventh well

142‧‧‧eighth well

144‧‧‧ fifth heavily doped area

146‧‧‧Doped layer

156‧‧ ‧ field oxide layer

158‧‧‧First field oxide

160‧‧‧Second field oxide

162‧‧‧The third field oxide

Claims (10)

[Item 1] A semiconductor structure comprising:
a substrate;
a first doped region is formed in the substrate, the first doped region has a first doping type;
a first well formed in the substrate, the first well having the first doping type;
a second doped region is formed in the substrate and surrounds the first doped region, the second doped region separates the first well from the first doped region, and the second doped region has a first doped region Two doping type;
a plurality of first heavily doped regions formed in the first doped region, the first heavily doped regions having the second doping type;
a plurality of electrical conductors and a plurality of dielectrics are formed on the substrate and interposed between the first heavily doped regions, wherein the conductive systems are formed on the dielectric materials;
a second heavily doped region formed in the first well, the second heavily doped region having the first doping type;
a third heavily doped region formed in the second doped region, the third heavily doped region having the second doping type;
a fourth heavily doped region formed in the second doped region adjacent to the third heavily doped region, the fourth heavily doped region having the first doping type; and a first gate electrode And a first gate dielectric formed on the substrate between the first heavily doped region and the fourth heavily doped region, wherein the first gate electrode is formed in the first gate Electrical quality. [Item 2] The semiconductor structure of claim 1, wherein the first doped region comprises:
a second well, wherein the first heavily doped region is formed in the second well; and a third well adjacent to the second well and extending below the second well; and wherein the second doping The area includes:
a fourth well separating the first well from the first doped region;
a fifth well separated from the fourth well, wherein the third heavily doped region and the fourth heavily doped region are formed in the fifth well; and a first buried layer connected to the fourth well The fifth well. [Item 3] The semiconductor structure of claim 2 further includes:
A sixth well formed in the substrate adjacent to the fifth well, the sixth well having the first doping type. [Item 4] The semiconductor structure of claim 3 further includes:
a second buried layer connecting the first well and the sixth well, the second buried layer having the first doping type. [Item 5] The semiconductor structure of claim 3 further includes:
a seventh well formed in the substrate, the seventh well having the first doping type;
An eighth well formed in the substrate and interposed between the sixth well and the seventh well, the eighth well having the second doping type; and a fifth heavily doped region formed in the first In the eight wells, the fifth heavily doped region has the second doping type. [Item 6] The semiconductor structure of claim 5 further includes:
a sixth heavily doped region formed in the fifth well adjacent to the third heavily doped region, the sixth heavily doped region having the first doping type;
a seventh heavily doped region formed in the eighth well adjacent to the fifth heavily doped region, the seventh heavily doped region having the first doping type; and a second gate electrode and a first A gate dielectric is formed on the substrate and interposed between the sixth heavily doped region and the seventh heavily doped region, wherein the second gate electrode is formed on the second gate dielectric. [Item 7] The semiconductor structure of claim 3 further includes:
A buried oxide is formed in the first well, the first doped region, the second doped region, and the sixth well. [Item 8] The semiconductor structure of claim 2 further includes:
A doped layer is formed in the third well. [Item 9] The semiconductor structure of claim 2 further includes:
An oxide layer is formed on the substrate, the field oxide layer comprising:
a first field oxide formed on the fourth well;
a second field oxide is formed on the third well, wherein a portion of the first gate electrode is formed on the second field oxide; and a plurality of field plates are formed on the second field oxide. [Item 10] A semiconductor structure comprising:
a substrate; and an insulated gate bipolar transistor (IGBT) comprising:
a first doped region is formed in the substrate, the first doped region has a first doping type;
a first well formed in the substrate, the first well having the first doping type;
a second doped region is formed in the substrate and surrounds the first doped region, the second doped region separates the first well from the first doped region, and the second doped region has a first doped region Two doping type;
a plurality of first heavily doped regions formed in the first doped region, the first heavily doped regions having the second doping type;
a plurality of electrical conductors and a plurality of dielectrics are formed on the substrate and interposed between the first heavily doped regions, wherein the conductive systems are formed on the dielectric materials;
a second heavily doped region formed in the first well, the second heavily doped region having the first doping type;
a third heavily doped region formed in the second doped region, the third heavily doped region having the second doping type;
a fourth heavily doped region formed in the second doped region adjacent to the third heavily doped region, the fourth heavily doped region having the first doping type; and a first gate electrode And a first gate dielectric formed on the substrate between the first heavily doped region and the fourth heavily doped region, wherein the first gate electrode is formed in the first gate Electrically
The first heavily doped region and the second heavily doped region are electrically connected and serve as an anode of the IGBT, and the third heavily doped region and the fourth heavily doped region are electrically connected and serve as the anode The cathode of the IGBT.