TWI222743B - Structures and fabrication methods trench insulated gate bipolar transistors - Google Patents

Abstract

The purpose of the present invention is to provide structures and fabrication methods to protect trench insulated gate bipolar transistors against heavy-ion-induced destructive failures. The present invention uses the horizontal and vertical extension of the P+ plug to reduce the lateral resistance of the P-base region and harden the trench insulated gate bipolar transistors against radiation without sacrificing the normal performance of the trench insulated gate bipolar transistors.

Description

22743 V. Description of the invention (1) [Technical Field of the Invention]-The present invention is to provide a structure and a manufacturing method for fI radiation breakdown of a bipolar transistor with a grooved gate insulation gate. A1 The lateral resistance value characteristics of a Trench insuiated Gate Bipolar Hanstor (TIGBT) in order to improve the anti-transmission ability of the element. In particular, the present invention can improve the anti-radiation capability of the component without affecting the normal operation of the component without changing the structure and method of the bipolar transistor of the gate-shaped gate insulator and without complicated manufacturing steps. [Previous technology] In recent years, the efficiency of the insulated gate bipolar transistor has been rapidly improved, and it has become a switching element with a high operating voltage, which makes the application range of the insulated gate bipolar transistor widely expanded, and can be used with metal oxide semiconductors. (Metal Oxide Semiconductor; MOS) and bipolar structure are used together 'especially in high-power applications. Such as: mobile phone communications and satellite communications. Insulation ~ metamorphic polar transistors are divided into planar gate insulated gate transistors and slot-shaped interpole insulation bipolar transistors according to their structure. Insulated bipolar transistors have superior characteristics in terms of power loss than traditional planar gate insulated gate bipolar transistors. ^ "A and dare research found that insulated closed bipolar transistors still have their shortcomings. Take NIGBT-type inter-insulator bipolar transistors (TIGBTs) as an example, because of the internal parasitic gate fluid (thyristor The relationship between) and heavy ion Ding ** should be a kind of stone skin π · π · ι 1222743 V. Description of the invention (2) %% foot phenomenon (hearvy-ion-induced destructive failures), called a single event flash event (single event latch-up (SEL), which forms a parasitic pnpn structure inside igBT, which will rapidly increase the component current. This is because the JFET region does not exist in the design of the trough gate insulated gate bipolar transistor, so it will have a relatively large A low on-resistance is present. If there is a flash-lock (SEL) factor that induces a single event in the Earth, such as the existence of a large number of Xingchang shooting environments, the internal components will be triggered to produce a latch-up phenomenon. Currently in the development of space applications Is encountering the above problems: the parasitic gate fluid inside the insulated gate bipolar transistor is often triggered due to the radiation effect in space, and then a positive feedback mechanism is generated. This positive feedback mechanism will quickly The component current is added, and the component is finally burned. As shown in Figure 2, Figure 2 is a structure diagram of a general N-channel insulated gate bipolar transistor. The grooved gate insulated gate bipolar transistor mainly includes an N + emitter 26 ( N + emitter), an emitter metal 29, an N-drift region 22, an N + buffer layer 21, a P + substrate 20, a p base 24 (p base) and a slot-shaped gate 25. Its related positions are shown in Figure 2. It should be noted that this structure is such that when there is a heavy ion effect induction, its N-pool region 22, P base 23 and N + The emitter 26 forms a parasitic junction of npn. ^ = It is easy to bow when the environment is induced, such as heavy ion effect or radiation. ^ SEL ' The method has not been proposed yet. The present invention proposes a method for improving the anti-radiation capability of the gate-shaped bipolar transistor with a gate-shaped gate electrode. ,,,edge

V. Description of the invention (3) [Summary of the invention] The main purpose of the present invention is to provide the structure and manufacturing method of a unipolar transistor, the lateral resistance value of a double-slot gate insulated gate bipolar gate bipolar transistor, and the utilization thereof. Reduce the working characteristics of the slot-shaped gate insulation and improve the radiation resistance of the component j to achieve the normal component. Another object of the present invention is to provide a transistor structure, which is formed in the absolute-shaped free-pole insulation of the N-channel. p + Plug lateral and vertical two-bar edge: the area of the f-polarity transistor through the P + plug of the bipolar transistor, ^ the possibility of large gate-shaped gate insulation, so there can be less parasitic gate fluid than g% Touch the re-purpose ability of the present invention. The structure of the transistor, in the P-channel, the insulated θ gate, the insulated gate bipolar is formed by the lateral and vertical extension of the N + plug: In the crystal, the area of the bipolar electrical plug is applied: Force 2 = the pole Possibility of insulation triggering, so you can have higher progress: First, ^ First, take a semiconductor substrate doped = formed in the P + substrate by diffusion, and a P-well is formed by the interposer layout method, where The p_weU element, 'its: the step of forming a P + plug is the important factor of the present invention. The existence of the second region can reduce the possibility of parasitic closed fluid being triggered. Next, the layers and polycrystalline silicon poles are formed. After forming the -N + emitter, the upper layer is oxidized to form the upper layer of the polycrystalline silicon gate. 1222743 V. Description of the invention (4) Layer ‘finally perform the emitter metallization step’ to complete the transistor production. [Embodiment] The present invention utilizes the characteristics of reducing the lateral resistance of a slot-shaped gate insulated bipolar transistor. In this way, the presence of high-radiation in the environment will not induce the flash-lock phenomenon. It can achieve compliance with the normal working characteristics of the component and improve the anti-radiation ability of the component. Wherein, the lateral resistance value (not shown in the structure A of Fig. 1) refers to the hole current of the bipolar transistor of the gate-insulated gate.

(hole current) flows under the N + emitter through the P base region, and finally flows out of the resistance region formed by the era it ter electrode. In order to explain the transistor structure of the present invention in detail, the present invention will provide an insulated gate bipolar transistor made of an N-type channel as an example and illustrated with reference to the figure.

First, referring to FIG. 1, the slotted gate insulated gate bipolar transistor described in the embodiment of the present invention mainly includes an N + emitter 6 (N + emitter), an emitter metal 19, and a p + The substrate 10 (p + substrate), a P + plug 13 (P + plug), a p base 14 (p + base), and a slot gate 15 (gate). The process steps are as follows: A doping step is performed in a silicon substrate to make the substrate a P + substrate 10, and then N + buffer layer ^ (N + buffer layer) and N-drift are formed in the substrate using diffusion or ion distribution. Area 12 (N-drift area). This N-drift area 12 is used to withstand high voltage. Next, P + plugl3 is formed by diffusion or ion implantaon. The formation area of the P + Piugi3 is the focus of the present invention.

Page 81222743 V. Description of the invention (5) --------- P + Plugl3 under N + emitter 16 is doped with low resistance by diffusion method, so that it can be originally under n + emitter 16 A large resistance with a low concentration formed by p basel4m. In this structure, the doping concentration of P + p 丨 ug 丨 3 is higher than that of P basel4. With this doping of p + Piugi3, the lateral resistance can be reduced, and the area of p + plugi3 can be increased by extending laterally and vertically, as shown in Structure A. This structure will have a small lateral resistance value, which makes it difficult to drive the parasitic gate fluid. The N + buffer layer 11 and the N-drift region 12 described above can also be formed (epi) using an epitaxial method. The horizontal axis distance on the right side of P + Pi ugl3 mentioned in Ma Yueyueyi can be extended to the right side without affecting the original operating characteristics of the children and achieving the most effective principle of reducing lateral resistance, so that Radiation resistance is further improved. The depth of P + P 1 ug can be extended vertically downwards without affecting the original operating characteristics of the element and the most effective principle of reducing lateral resistance, so that the radiation resistance is further improved.乂 The purpose of the present invention to form the P + Plugl3 is to change the low-resistance and high-resistance area originally opened by p baseU into a thick and small resistance area formed by p + P 1 ug 1 3, which can greatly reduce the side.向 Resistance. That is to say: after the ion impact, the transient current source generated will decrease with the resistance of the element's internal port = to make the parasitic NPN transistor inside the element more = 1 driven, because the hole current of this transient current source Through the emitter discharge, 4 'the range it flows through is P + plugl 3 with small resistance. This side ί = effectively reduces the large resistance area originally formed by p base 1 4. Once the resistance decreases, this N + The small pressure formed by the emitter 16 and! ^ Plugl3 1222743

:: will greatly reduce the forward-bias voltage of this diode, due to the possibility of a parasitic interstitial fluid being triggered by heavy ions. As long as it is driven: a positive feedback mechanism should be generated. This structure can be referenced to reduce parasitic idle current II.

Continuing, as shown in FIG. 1, p-well is formed by using the ionic distribution method jimplantati0n: that is, "region 14". 3. The gate oxide layer was formed in the substrate by dry oxidation. The oxide was deposited on the substrate using low-pressure chemical vapor deposition (L0w pressUR cknncal vapor depositi0n; Lpcv)) to deposit grooved gate electrodes. 15 (poly gate), forming the emitter metal ig by a step of subtracting, metallization). The transistor manufactured in this way can reduce the lateral resistance of the parasitic gate fluid emitter and the base as described above, so that it will be stable in the heavy ion environment such as satellite power supply system or high altitude aircraft. According to the gist of the present invention, the slotted gate insulated bipolar transistor may be an N-channel slotted gate insulated bipolar transistor or a P-shaped channel slotted gate insulated bipolar transistor. The embodiment of the present invention only describes the manufacturing method of the N-channel channel-shaped gate insulated gate bipolar transistor. (sputter) or physical vapor deposition (phys ^ al \ aper deposition; PVD) deposition of metal aluminum silicon copper to form N + emitter 16 (emitter) and dry oxidation to form an oxide layer 17 (gate layer). Finally, using emitter metallization (emitter

1222743

The slot-shaped gate insulated gate bipolar transistor described in the embodiment of the present invention is closed and its size is limited. Its size may be sub-micron, deep-sub-micron, or Nano-meter. In the embodiment of the present invention, a series of experiments are compared with the slot-shaped gate insulated gate bipolar transistor (shown in FIG. 2) or a similar structure transistor (shown in FIG. 3) made in the conventional manner. The working voltage (as shown in Figure 4), the sensitivity of the SEL phenomenon after the impact of heavy ions (as shown in Figure 5) and the sensitivity of the SEL phenomenon after the impact at the same position of the transistor (as shown in Figure 6) ) And other conditions. . First, the transistor structure involved in the experiment will be described. I. Structure A: As shown in FIG. 1, it is an embodiment of the present invention. Π · Structure B: As shown in Fig. 2, it is a vertical structure diagram of the basic grooved gate insulated gate bipolar transistor structure B. Melon. Structure C: As shown in FIG. 3, it is in a groove-shaped gate insulated bipolar transistor element in a similar manner to DMOS, but additionally forms a layer of P + diffusion region 33 (represented by structure c), However, the depth of this p + diffusion region is shallower than the structure A of FIG. 1. This structure includes an N + emitter 36 (N + emitter), an emitter metal 39 (EmiUer metal), a p + substrate 30 (P + substrate), a P + plug 33 (p + plug), and a base 34 (P + base), a grooved gate 35 (gate), a gated layer 38, an upper oxide layer 37, an N + buffer layer 31 (N + buffer layer), and an N-drift area 32. The formation of this structure is mainly due to the fact that after heavy ions strike the element, the hole current will not flow vertically or laterally, so this structure can reach

1222743 V. Description of the invention (8) = contact (_1.Contact) and the purpose of reducing the lateral voltage drop inside the polar transistor element. The results of this article are as follows: First, please refer to Figure 4, the three unstructured collector currents vs. gate voltage curves (fixed collector voltage is 20V) for structures A to c. B and c have similar normal working curves, so the structure (structure A) used in the radiation resistance of this case has the same operating characteristics, and will not affect its original operating characteristics. Figure 5 shows the use of different structures (structures B and C) and the same position (x = 14 / zm) in the fixed bracket f. Observe the sensitivity and degree of structures B and c to the SEL phenomenon. From this figure, it can be seen that no SEL phenomenon occurs in the structure c, because the $ collector current decreases with time, and it will eventually return to the leakage current value of the original equilibrium =, that is, under this structure, the heavy The ions did not cause permanent damage to the inside of the bipolar transistor of the grooved gate,

Everything will return to its original state. Conversely, from this picture, it can be seen that a large current is generated inside the structure B. This large current is the SEL current, which will burn 70 pieces. From this, it can be seen that the P + diffusion region provided by the present invention has the existence of tritium. -p continuation, please refer to Figure 6, impacting the same position of structure A and structure C (χ = 14 with heavy ions (LET = 0.4 pC // zm)), using the same collector bias (VC = 2 0 0V) 'Then it can be seen that the structure c has caused the seL phenomenon', but the structure A has not caused the SEL phenomenon. This is because the cross-sectional area of the p + well region of the structure a becomes larger, so the lateral resistance value can be reduced, which in this case means It can allow more current to flow to the p + well region of structure A,

1222743

It does not drive parasitic NPN bipolar transistors. In other words, when part of the current flows through the p + well region under the N + emitter region, the P + well region of the structure A is larger than the p + well region of the structure C, so

The lateral resistance value is smaller than the structure c 'Finally, the lateral voltage drop will also decrease by V. Finally, the structures A, B, and c are sorted out in a table. When different bias voltages and different ion impact positions occur,' whether or not SEL phenomenon occurs, I It is proved that the adopted structure (Structure A) can indeed achieve the & improvement of the anti-sag capability of the trough-shaped interstellar insulation gate bipolar transistor. The results are shown in Table 1, Table 2 and Table 3. Table 1 shows the measurement results of the structure A of the present invention with different collector bias and no SEL phenomenon at different locations. As can be seen from this table, when heavy ions (LET = 0.4 pC /// m) are struck at different positions of structure A under different collector biases, they only occur when the collector bias is greater than 24 (^ SEL phenomenon. To complete this table, two methods can be followed. The first is to fix the position where the ions strike, and then use the collector voltage of structure A as a loop to sweep from 2 60V to 170V, and then observe the collector current. For the time curve, if the collector current has a large current phenomenon, then record it as ¥ (that is, the occurrence of the SEL phenomenon). Conversely, if the collector current returns to the equilibrium leakage current, then It is recorded as the occurrence of no SEL phenomenon) 'The second is to first fix the collector voltage of structure A, and then change the impact position of the ions =, 6 // m, 10 // m, 14 # m) , And then record whether there is SEL phenomenon according to the previous method. In Table 2, heavy ions (LET = 0.4 pC /// m) are struck at different positions of structure B under different collector biases. When the collector bias is greater than 80 volts,

Page 13 122743 V. Description of invention (ίο) Superficial SEL · See the pixels into this table 'You can follow two methods, the same operation method as in Table 1' Only change the voltage range to from 170V to 80V . In Table 3, heavy ions (LET = 0 4 pC // Zm) are collided at different positions of the structure c under different collector biases. When the collector bias is greater than 70 volts, SEL phenomena will occur. To complete this table, you can follow two methods. The operation is the same as that in Table 1. Only the voltage range is changed from 22 ¥ to 17oy, and then the collector current versus time is observed. Comparing the above tables (Table 1, Table 2 and Table 2), it can be found that the structure A can indeed improve the bias of the SEL phenomenon. In addition, from Tables 1, 2, and 3, it can also be found that the structure is more likely to have sel in the place where the ion impact is closer to the channel, but the SEL phenomenon does not occur in a relatively remote place. < Figure 7 is the sum of Tables I, II and III. It is the sensitivity of the ion to the SEL phenomenon at different ion impact sites under different drain bias voltages of the company ’s A, B, and C; the structure can be found. "The voltage produced by the SEL is the highest. The best reference examples of the present invention are each in a specific field, so those skilled in the art should be able to understand the present invention and only implement appropriate and slight adjustments. And the application will still be without losing the present invention. The scope of the subsequent patent application includes the application and adjustment of the meaning of the present invention.

1222743 Illustration on page 14

[Brief description of the diagram] Figure 1 is a vertical section of the structure A in the embodiment of the present invention. Figure 2 is a vertical section of the structure B in the embodiment of the present invention. ^ Figure 3 is a vertical section of the structure C in the embodiment of the present invention. ^. FIG. 4 shows three structures A to c in the embodiment of the present invention. Curve of collector current vs. gate voltage. Figure 5 of the same structure is the same re-bias bias used in the embodiment of the present invention and hits the same position of the structures B and C.

The sensitivity of the phenomenon. Direction ,,, "material, C vs. SEL" Figure 6 shows the sensitivity of the SEL phenomenon when the same biasing voltage is used in the embodiment of the present invention and it strikes the same position of structures A and C.

Heavy ions, with the same structure A and C pairs

Table 1 shows the different positions of the ion impact on the structure A and the extreme bias voltage in the examples of the present invention, and its sensitivity to the SEL phenomenon is observed. Table 2 shows the ion impact on the structure B in the examples of the present invention: Observe the sensitivity to the SEL phenomenon at different positions under the extreme bias. Table 3 shows the different positions of the ion impacted by the structure c in the embodiment of the present invention, and observe its sensitivity to the SEL phenomenon. Degree 'Fig. 7 shows the ion impact on the structures A, β, (

Observe the sensitivity to the SEL phenomenon at different positions under different drain bias voltages. Drawing number description: 10 P + substrate 11 N + buffer layer 12 N- drift region

1222743 Schematic description 13 P + plug area 16 N + emitter 19 emitter metal 2 2 N-drift area 2 6 N + emitter 2 9 emitter metal 3 2 N-drift area 3 5 slot gate 3 8 gate Oxide layer 14 P base 1 7 Oxide layer 20 P + substrate 2 4 P base 2 7 Oxide layer 3 0 P + substrate 33 P + plug area 3 6 N + emitter 3 9 emitter metal 1 5 slot gate 1 8 gate oxide layer 21 N + buffer layer 2 5 slot-shaped gate 28 gate oxide layer 31 N + buffer layer 34 P base 3 7 upper oxide layer

Page 16

Claims (1)

1222743 VI. Scope of patent application1. A method for manufacturing a trough-gate insulated gate bipolar transistor includes the steps of: (a) taking a semiconductor substrate and forming a p + substrate (P + substrate) after the doping step; (b) ) Forming a P + plug (P + plug) in the p + substrate using a diffusion method (diff); (c) forming a P beside the p + plug using an ionization method (implantati) -well, wherein the p-weii is a p-base region; ❿ (d) a gate oxide layer (gateox) is formed next to the p-base region as a lower layer of a polycrystalline silicon gate (poly gate) An oxide layer; (e) fabricating the polycrystalline silicon gate on the gate oxide layer; (0) forming an N + emitter on the p-base region: (g) on the polycrystalline silicon An upper oxide layer is formed above the gate; and (emitter) metallization is performed above the P base region. 2 · Slot-shaped gate insulated gate bipolar as described in the first patent claim Method for fabricating a transistor, wherein the doping concentration of the P + plug is higher than that of the p-baSe region Concentration, so that the lateral resistance can be reduced by the formation of the p + piUg. 3 · As described in Item 丨 of the declared patent, the grooved gate insulated gate bipolar transistor ^ ^ The method of operation, wherein the P + PlUg The size of the area is inversely proportional to the lateral resistance generated by the trough gate in the bipolar transistor. Once the P + Piug area increases, the parasitic gate fluid is less likely to be driven. Page 17 1222743, the scope of the patent application ^ 2 = the right side of the 5 horizontal axis of the slot-shaped insulating pole bipolar transistor described in item 3 increases the Ptplug area to increase the p + plug to the rightmost μ, And off, without affecting the original operating characteristics and reach of 70 pieces. Second, under the principle of reducing lateral resistance, you can do a lateral extension to the right, such as 5 to improve radiation resistance. The method of increasing the area of the P + PlUg area can increase the ice degree of the P + W called = without affecting the original component of the element. Some operating characteristics and the maximum reduction of ^^ can be vertically extended downward under the principle of directional resistance, so that the anti-radiation ability of 6 cubs is further improved. The manufacturing method of the slotted gate insulated gate bipolar transistor described in item 1 of the patent scope, wherein the slotted gate insulated gate bipolar transistor can be an n-channel slotted gate insulated gate bipolar transistor and One of the p-channel channel-shaped interrogated insulated gate bipolar transistors. 7 · The manufacturing method of the trough-shaped gate insulated gate bipolar transistor as described in item 1 of the scope of the patent application, wherein the P + substrate system in step (a) includes N + buffer iayer and N-drift Area (N-driftregion). 8. The manufacturing method of the trough-shaped gate insulated gate bipolar electric crystal as described in item 1 of the scope of the patent application, wherein the p + plug formed in step (b) can also be ion implantation. 9 · A trench gate insulated gate bipolar transistor (TIGBT) structure mainly includes: a P + substrate (P + substrate); Page 18, 122743, patent application scope: a slot gate in the P + substrate; an N + emitter (N + effli tter) in the P + substrate and connected to the slot gate; a P base (P base) is under the N + emitter and is connected to the slot-shaped gate; a P + plug is connected to the N + emitter and P base; 10. as described in item 9 of the scope of patent application Slot-shaped gate insulated gate bipolar structure. The small A of the P + plug area is inversely related to the lateral resistance value generated by the slot-shaped insulated pole polar transistor. · Therefore, the area of P + Plug increases. At this time, the parasitic brake fluid is relatively difficult to be driven by the field. 11. = = Slot-shaped gate insulated gate bipolar transistor, as described in item 9 of the patent scope. Structure, without affecting the original operating characteristics of the P + Plug, the size of the p + Plug can be selected to extend laterally to the left and right, which makes the radiation resistance better. ^ Jinzhi k 12.: The bipolar transistor with the gate-shaped gate insulation gate described in item 9 in the range m. The doping of Plug is formed by diffusion. 13 '^ (Patent Scope) Item 1 of the trough-shaped inter-pole insulating bipolar transistor. The doping of the P + plug uses an ion implantation method. 14. = :: patent Slot-shaped gate insulated gate bipolar transistor described in item 9! . Structure, the P base is doped using an ion implantation method. 1 5 · As for the scope of patent application No. 9 ji #, +, ^ Slot-shaped gate insulated gate bipolar transistor as traced by Le Xiang, page 19 1222743 6. The scope of patent application body structure 'where the concentration of the P + plug is doped Higher than the doping of the P-base region; so the degree of lateral resistance can be reduced by the formation of the p + p 1 ug. 16 · As described in item 9 of the scope of the patent application, the trench-gate insulated gate bipolar electric crystal structure is composed of an upper gate oxide layer, a polycrystalline silicon gate and a lower oxide layer. 1 7 · —Trench Insulated Gate Bipolar Transistor (TIGBT) structure mainly includes: an N + substrate (N + substrate); a slot gate on the N + substrate A P + emitter in the N + substrate and connected to the slot gate; an N base under the P + emitter and connected to the slot gate; N + A plug (N + plug) is connected to the P + emitter and the N base; 1 8 · As described in the patent application No. 丨 7, the slot-shaped gate insulated gate bipolar transistor structure, the size of the N + plug area and The trough gate bipolar transistor produces an inverse relationship with the lateral resistance value. When the area of N + p 1 ug increases, the parasitic households are not easy to call the gate body. Driven 19. If the 17th family of the patent application claims the slot-shaped closed-pole insulated double crystal structure, the N + plug can be extended to the left and right and lowered without affecting the original operation. P 1 ug Delay Page 20 1227743 6. One way to extend the scope of patent application is to make it resistant to radiation. 20. As described in item 17 of the scope of patent application = knife right 冋 crystal structure, the weight of the N + plug; ^ shape field leisure pole insulation closed double Polarization (diffusion) formation. Multi-Knowledge Diffusion Method 21 If you apply for the patent No. 7 crystal structure, the N + plug's field gate insulated gate bipolar electric ^ Plantation) / § ^ # # ^ ^ ^ ^ ^ ^ (i 〇n 22 利; The bipolar electricity of the slot-shaped gate insulation idler described in Λ item / 7, said the body's structure. The doping of the base electrode is formed by using ion implantation. Formula 23 * Doping concentration in the region For example, if two gs are used, the resistance is lower than the P-base resistance. ^ Ρ 1 ug is formed so that the side 24. Li: The bipolar electric body between the slot gate insulation described in item 17, , "冓" The grooved gate is composed of the upper 1 ± electrode and the lower oxide layer. Emulsified layer, polycrystalline silicon gate