CN102324434A - Schottky barrier metal oxide semiconductor (MOS) transistor and preparation method thereof - Google Patents
Schottky barrier metal oxide semiconductor (MOS) transistor and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a Schottky barrier metal oxide semiconductor (MOS) transistor, which comprises a ring-shaped gate electrode (3), a ring-shaped gate dielectric layer (2), a ring-shaped gate electrode side wall (4), a semiconductor substrate, a source region (5) and a ring-shaped drain region (6). The Schottky barrier MOS transistor is characterized in that: the semiconductor substrate is provided with a convex step structure; the source region is positioned on a high plane of a convex step; the ring-shaped drain region surrounds the convex step and is positioned on a low plane; the gate dielectric layer and the gate electrode are positioned at a corner of the convex step, surrounds the step and is raised into a ring shape; and the gate electrode side wall is ring-shaped, surrounds on the outer side of the gate electrode and has a certain thickness to serve as a shelter to form an underlap structure of a drain terminal. The Schottky barrier MOS transistor adopts a step structure combining a ring-shaped gate structure and an asymmetric source/drain structure, so on the basis of inheriting advantages of traditional SB-MOSFET, the on-state conduction current is improved, a dipolar effect is inhibited, and the process is simplified.
Description
Technical field
The invention belongs to FET logic device and circuit field in the CMOS super large integrated circuit (ULSI), be specifically related to a kind of Schockley barrier MOS transistor that combines ledge structure, annular grid structure and asymmetric source/drain structure and preparation method thereof.
Background technology
As far back as late 1960s, Lepselter and Sze have just proposed Schockley barrier MOS field-effect transistor (Schottky Barrier MOSFET) structure.Utilize metal or silicide to replace traditional doping the source leakage, utilize the direct Tunneling potential barrier of the charge carrier of source end to realize conducting.Along with the size of Metal-oxide-silicon field-effect transistor (MOSFET) is constantly dwindled, short-channel effect is increasing to the influence of device.For traditional M OS field-effect transistor, in order to suppress short-channel effect, the source/drain region that must adopt ultra shallow junction and abrupt change to mix.And Schottky-barrier source/drain region technology realizes ultra shallow junction and low dead resistance source-drain area owing to it can utilize simple low temperature technology, thereby becomes a kind of attractive substitute technology to highly doped source-drain area.And in the traditional handicraft the required temperature of activator impurity, realize that the required low temperature process of Schottky barrier source-drain area requires less heat budget, for the use of high K and metal gate material provides possible solution.
Yet traditional Schockley barrier MOS field-effect transistor (SB-MOSFET) also exists certain problem.At first, because the conducting electric current is mainly derived from the tunnelling of source end charge carrier, thereby has limited the size of ON state conducting electric current, less ON state current becomes the one of the main reasons that restriction SB-MOSFET uses; Secondly, there is more serious dipolar effect in SB-MOSFET, and promptly when grid added reverse biased, device also can produce bigger conducting electric current, thereby makes and all present bigger conducting electric current when grid adds certain forward, reverse biased.This is because when grid applies reverse biased (is that example describes with N type substrate); Because grid bias and drain terminal bias voltage are in the opposite direction; Bigger electrical potential difference can be fallen on the schottky junction between drain terminal raceway groove-leakage; Thereby form very thin drain terminal potential barrier, impel channel electrons to be tunneling to drain terminal, produce the conducting electric current.
Summary of the invention
The present invention is a kind of Schockley barrier MOS field-effect transistor that combines ledge structure, annular grid structure and asymmetric source/drain structure and preparation method thereof.With existing CMOS process compatible and kept under the condition of the various advantages of traditional SB-MOSFET, this structure is utilized ledge structure, annular grid structure to improve ON state current, has been simplified technological process, and utilizes asymmetric source/drain structure to suppress dipolar effect.
Technical scheme of the present invention is following:
A kind of Schockley barrier MOS transistor that combines ledge structure, annular grid structure and asymmetric source/drain structure comprises an annular grid electrode, an annular grid dielectric layer; Annular grid electrode side wall; The Semiconductor substrate that the projection ledge structure is arranged, a source region, a ring-type drain region.Said Semiconductor substrate has the raised step structure; The metal suicide source district is positioned on the higher plane of raised step; Annular metal silicide drain region is around raised step and be positioned on the lower plane; Gate dielectric layer and gate electrode are positioned at the corner of raised step and center on the step convexity in the form of a ring; The gate electrode side wall is trapped among the gate electrode outside in the form of a ring and certain thickness is arranged, with as the underlap structure of sheltering the formation drain terminal.
Drain terminal underlap structure refers to grid and does not cover raceway groove fully and exposed a part of raceway groove and covering grid oxide layer above that in the side near drain terminal.
Said source region (5) and drain region (6) can be the compound that any conductivity good metal or metal and backing material form.
The preparation method of MOS transistor according to the invention may further comprise the steps:
(1) on Semiconductor substrate, defines active area through shallow-trench isolation;
(2) photoetching and etch ledge structure;
(3) growth gate dielectric layer;
(4) deposit gate electrode layer then utilizes side wall technology to form annular grating electrode;
(5) deposit side wall layer then utilizes side wall technology to form annular side wall;
(6) float natural oxidizing layer; Make source/drain region (being higher plane of step and step) expose backing material than the zone of not sheltered on the low degree by gate electrode and side wall; The sputter layer of metal forms metal and semi-conductive compound through process annealing, then removes unreacted metal; Because the masking action of side wall layer can be formed self-aligned asymmetric Schottky source/drain region, i.e. drain terminal underlap structure;
(7) get into the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
Among the above-mentioned preparation method, the semiconductor substrate materials in the said step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, silicon (SOI) on the binary of III-V and IV-IV family or ternary semiconductor, the insulator or the germanium (GOI) on the insulator.
Among the above-mentioned preparation method, the gate dielectric layer material in the said step (3) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Among the above-mentioned preparation method, the method for the growth gate dielectric layer in the said step (3) is: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition or physical vapor deposition.
Among the above-mentioned preparation method, the gate electrode layer material in the said step (4) is selected from DOPOS doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
Among the above-mentioned preparation method, the side wall layer material in the said step (5) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Among the above-mentioned preparation method, the metal material in the said step (6) is selected from Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material through annealing.
Advantage of the present invention and good effect:
(1) the present invention has inherited the advantage of traditional schottky barrier MOS transistor (SB-MOSFET), for example ultra shallow junction, low source-drain area dead resistance etc.
(2) the present invention adopts ledge structure, has eliminated among the conventional planar SB-MOSFET owing to lean on the uncovered area between source-raceway groove that the distolateral wall in source brings, thereby has made that the potential barrier between source-raceway groove is thinner under the ON state, has increased tunnelling probability, has improved the conducting electric current.
(3) the present invention has adopted the annular grid electrode structure, has increased the contact area of source and raceway groove, thereby has increased the tunnelling area of source end, has improved ON state conducting electric current.
(4) the present invention has adopted asymmetric source/drain structure; It is drain terminal underlap structure; Slow down the electric field change at raceway groove-drain junction place, thereby increased the barrier width on raceway groove-drain junction, suppressed SB-MOSFET occurs in drain terminal when grid applies reverse biased tunnelling current; Source end tunnelling conducting electric current when simultaneously this can't influence grid and applies forward bias, thus the dipolar effect of SB-MOSFET suppressed.
(5) because the formation of gate electrode is to have utilized side wall technology, and the formation that leak in the source also is to utilize the metallized process of autoregistration, has therefore reduced the photoetching number of times in the whole process flow, has simplified technical process.
Generally speaking, this device architecture has adopted ledge structure to combine annular grid structure and asymmetric source/drain structure, on the basis of the advantage of inheriting tradition SB-MOSFET, has improved ON state conducting electric current, has suppressed dipolar effect, and has simplified technology.
Description of drawings
Fig. 1 (a) be photoetching and etch ledge structure after device along the profile of Fig. 1 (b) dotted line direction, Fig. 1 (b) is the corresponding devices vertical view;
Fig. 2 (a) be device behind growth gate dielectric layer and the deposit gate electrode layer along the profile of Fig. 2 (b) dotted line direction, Fig. 2 (b) is the corresponding devices vertical view;
Fig. 3 (a) utilizes side wall technology to form device after the annular grating electrode along the profile of Fig. 3 (b) dotted line direction, and Fig. 3 (b) is the corresponding devices vertical view;
Fig. 4 (a) be device behind the deposit side wall layer along the profile of Fig. 4 (b) dotted line direction, Fig. 4 (b) is the corresponding devices vertical view;
Fig. 5 (a) be utilize side wall technology to form annular side wall and cross the gate dielectric layer of carving perforated surface, source after device along the profile of Fig. 5 (b) dotted line direction, Fig. 5 (b) is corresponding vertical view;
Fig. 6 (a) is that splash-proofing sputtering metal annealing forms device behind the metal silicide along the profile of Fig. 6 (b) dotted line direction, and Fig. 6 (b) is the corresponding devices vertical view;
Fig. 6 (b) is the final vertical view of this structure devices, and Fig. 6 (a) is the profile of Fig. 6 (b) along the dotted line direction.
1-----------Semiconductor substrate 2-------------gate dielectric layer
3-----------gate electrode layer 4-------------side wall layer
6-------------Schottky drain region, 5-----------Schottky source region
Embodiment
Basic principle of the present invention is following: (describing with N type substrate)
When gate electrode and drain terminal applied forward bias SB-MOSFET is opened, the conduction band of channel region descended, thus make be with of source-channel junction place bend down severity more; Reduced source-raceway groove barrier width; When source end metal Fermi level was higher than at the bottom of the conduction band of channel region, source end electronics can tunnelling be crossed potential barrier and is got in the channel region conduction band, and then has reduced under the condition of raceway groove-drain junction place barrier height in the drain terminal forward bias; To drain terminal, produce electric current by the conduction band heat emission.In this whole process; The barrier width of source end has directly determined the size of conducting electric current; And among traditional planar S B-MOSFET because side wall essential, making has a bit of raceway groove directly not covered (but being sheltered by side wall) by gate electrode near source-channel junction, this a bit of uncovering area can slow down the steepness of conduction band bending; Thereby reduced the tunneling barrier width at source-channel junction place; The present invention has then adopted ledge structure, makes the source metal end can directly contact trench edges (also promptly having eliminated not by directly actuated that section uncovered area of gate electrode), and so the tunneling barrier of source end will be thinner under the ON state; Tunnelling probability increases, and the conducting electric current also is improved.In addition, when grid adds reverse biased, can make the valence band of raceway groove rise; Adding that forward bias that drain terminal applies makes the metal Fermi level of drain terminal descend, when drain terminal metal Fermi level is lower than the top of valence band of raceway groove, the electronics in the raceway groove valence band can tunnelling to drain terminal; Produce electric current; And because the electrical potential difference on raceway groove-drain junction is bigger, at this moment potential barrier will be very thin, so tunnelling current will be bigger; Produce the conducting electric current of comparable ON state current size, this is the dipolar effect of SB-MOSFET just.If can increase the width of the potential barrier on raceway groove-drain junction, the conducting electric current in the time of just can suppressing to add reverse biased effectively.The present invention has adopted the underlap structure (description technique scheme place is seen in the structure explanation) of drain terminal, thereby can slow down the steepness that raceway groove leans near the valence band of drain terminal to change effectively, thereby increases corresponding tunneling barrier width, the conducting electric current when suppressing to add reverse biased.
Be specific embodiment of the present invention below:
Embodiment 1:
Adopt following method to prepare MOS transistor according to the invention:
(1) be to adopt shallow-trench isolation fabrication techniques active area isolation layer on the body silicon silicon chip silicon substrate 1 of (100) in the crystal orientation, substrate doping is a N type light dope; Make step cutting pattern then by lithography, etch ledge structure, the high about 500nm of step is shown in Fig. 1 (a), 1 (b);
(2) heat growth gate dielectric layer, deposit gate electrode layer then, gate dielectric layer is SiO
2, thickness is 1-5nm, and gate electrode layer is the highly doped polysilicon layer, and thickness is about 200nm, like Fig. 2 (a), shown in 2 (b);
(3) utilize side wall technology to form annular grating electrode 3, gate electrode thickness is about 200nm, shown in Fig. 3 (a), 3 (b);
(4) deposit side wall layer, side wall layer are Si
3N
4, thickness is about 100nm, like Fig. 4 (a), shown in 4 (b);
(5) utilize side wall technology to form side wall 4, the thickness of side wall is about 100nm, shown in Fig. 5 (a), 5 (b);
(6) float natural oxidizing layer, expose the source-drain area backing material, sputter layer of metal layer Ni; Anneal through low-temperature heat; With the Schottky source/drain region of the self aligned formation metal silicide of silicon as device, because the masking action of side wall layer, source/drain region is asymmetric; Be that drain terminal forms the underlap structure, shown in Fig. 6 (a), 6 (b);
(7) get into the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the Schockley barrier MOS field-effect transistor of described combination ledge structure, annular grid structure and asymmetric source/drain structure.
Embodiment 2:
Like embodiment 1, difference is:
● shoulder height is about 200nm in the step (1);
● gate electrode thickness is about 100nm in step (2), (3);
● side wall thicknesses is about 50nm in step (4), (5);
● splash-proofing sputtering metal is the less metal of hole Schottky barrier in the step (6), like Pt.
Embodiment 3:
Like embodiment 1, difference is:
● substrate is doped to P type light dope in the step (1);
● splash-proofing sputtering metal is the less metal of electronics Schottky barrier in the step (6), like rare earth metal Er or Yb.
Claims (10)
1. a Schockley barrier MOS transistor comprises an annular grid electrode (3), an annular grid dielectric layer (2); Annular grid electrode side wall (4), a Semiconductor substrate (1), a source region (5); A ring-type drain region (6) is characterized in that, said Semiconductor substrate (1) has the raised step structure is arranged; Source region (5) is positioned on the higher plane of raised step; Ring-type drain region (6) is around raised step and be positioned on the lower plane; Gate dielectric layer (2) and gate electrode are positioned at the corner of raised step and center on the step convexity in the form of a ring; Gate electrode side wall (4) is trapped among the gate electrode outside in the form of a ring and certain thickness is arranged, with as the underlap structure of sheltering the formation drain terminal.
2. Schockley barrier MOS transistor as claimed in claim 1 is characterized in that, said source region (5) and drain region (6) are the compound of any conductivity good metal or metal and backing material formation.
3. Schockley barrier MOS transistor as claimed in claim 1 is characterized in that, said shoulder height is 200nm-500nm.
4. the preparation method of Schockley barrier MOS transistor according to claim 1 is characterized in that, comprises the steps:
(1) on Semiconductor substrate, defines active area through shallow-trench isolation;
(2) photoetching and etch ledge structure;
(3) growth gate dielectric layer;
(4) deposit gate electrode layer then utilizes side wall technology to form annular grating electrode;
(5) deposit side wall layer then utilizes side wall technology to form annular side wall;
(6) float natural oxidizing layer; Make source/drain region expose backing material; The sputter layer of metal forms metal and semi-conductive compound through process annealing, then removes unreacted metal; Because the masking action of side wall layer can be formed self-aligned asymmetric Schottky source/drain region, i.e. drain terminal underlap structure;
(7) get into the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
5. preparation method as claimed in claim 4; It is characterized in that; Semiconductor substrate materials in the said step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, silicon (SOI) on the binary of III-V and IV-IV family or ternary semiconductor, the insulator or the germanium (GOI) on the insulator.
6. preparation method as claimed in claim 4 is characterized in that, the gate dielectric layer material in the said step (3) is selected from silicon dioxide, hafnium oxide, hafnium nitride.
7. preparation method as claimed in claim 4 is characterized in that, the method for the growth gate dielectric layer in the said step (3) is conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition or physical vapor deposition.
8. preparation method as claimed in claim 4 is characterized in that, the gate electrode layer material in the said step (4) is selected from DOPOS doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
9. preparation method as claimed in claim 4 is characterized in that, the side wall layer material in the said step (5) is selected from silicon dioxide, hafnium oxide, hafnium nitride.
10. preparation method as claimed in claim 4 is characterized in that, the metal material in the said step (6) is selected from Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material through annealing.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390538A (en) * | 2015-12-04 | 2016-03-09 | 哈尔滨工业大学深圳研究生院 | Layout design method of TFET (Tunneling Field Effect Transistor) digital standard unit |
| CN106531622A (en) * | 2016-12-29 | 2017-03-22 | 中国科学院微电子研究所 | Preparation method of gallium arsenide-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate medium |
| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186636A (en) * | 1990-11-16 | 1992-07-03 | Matsushita Electric Ind Co Ltd | Schottky gate field-effect transistor |
| CN100448027C (en) * | 2006-12-08 | 2008-12-31 | 北京大学 | An asymmetric Schottky barrier MOS transistor and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4186636B2 (en) * | 2003-01-30 | 2008-11-26 | 株式会社日立製作所 | Superconducting magnet |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186636A (en) * | 1990-11-16 | 1992-07-03 | Matsushita Electric Ind Co Ltd | Schottky gate field-effect transistor |
| CN100448027C (en) * | 2006-12-08 | 2008-12-31 | 北京大学 | An asymmetric Schottky barrier MOS transistor and its manufacture method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390538A (en) * | 2015-12-04 | 2016-03-09 | 哈尔滨工业大学深圳研究生院 | Layout design method of TFET (Tunneling Field Effect Transistor) digital standard unit |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
| CN106531622A (en) * | 2016-12-29 | 2017-03-22 | 中国科学院微电子研究所 | Preparation method of gallium arsenide-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate medium |
| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
| CN107785437B (en) * | 2017-10-31 | 2020-05-29 | 沈阳工业大学 | Bracket-shaped grid-control source-drain resistance-variable bidirectional switch transistor and manufacturing method thereof |
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