CN101165916A

CN101165916A - Semiconductor device and method for fabricating the same

Info

Publication number: CN101165916A
Application number: CNA2007101368294A
Authority: CN
Inventors: 金子佐一郎
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2006-10-17
Filing date: 2007-07-17
Publication date: 2008-04-23

Abstract

The present invention relates to a semiconductor device and a method for fabricating the same. A resurf region of N type and a base region of P type adjacent to each other are formed in surface portions of a semiconductor substrate of the P type. A N emitter region is formed in the base region to be spaced from the resurf region. A gate insulating film is formed to cover a portion of the base region disposed between the emitter region and the resurf region, and a gate electrode is formed on the gate insulating film. A top semiconductor layer of P type electrically connected to the base region is formed in a surface portion of the resurf region. A collector region of the P type is formed in a surface portion of the resurf region to be spaced from the top semiconductor layer. The collector region and the top semiconductor layer have substantially the same impurity concentration and are disposed at substantially the same depth. Thus, the invention provides a high pressuretight semiconductor device for reducing the loss on the whole range from light to heavy load.

Description

Semiconductor device and manufacture method thereof

Technical field

The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly be used for the semiconductor device and the manufacture methods thereof such as high withstand voltage landscape insulation bar type bipolar transistor of switching power unit.

Background technology

In recent years, because the position of global warming countermeasure, this thing of power of awaiting orders of attenuating household appliances etc. receives much concern the switching power unit that the power consumption when people's strong request is awaited orders is very low.

Below, existing switching power unit is described.

Figure 36, one of circuit structure of the existing switching power unit of expression example.As shown in figure 36, existing switching power unit has upstream rectifying filter circuit 411, main body circuit 412, transformer 404 and downstream current rectifying and wave filtering circuit 421.

Particularly, be input to the alternating voltage between the

input

416 and 417 of upstream rectifying filter circuit 411, carried out rectifying and wave-filtering, be provided for main body circuit 412 as input direct voltage by upstream rectifying filter circuit 411.At this, upstream rectifying filter circuit 411 has diode bridge 431 and input capacitor 432, is carried out voltage after the full-wave rectification by diode bridge 431 and is transfused to capacitor 432 and carries out filtering, is provided for main body circuit 412 again.

In main body circuit 412, be provided with thyristor 413 and voltage control circuit 414.Described thyristor 413 and voltage control circuit 414 can be integrated in the chip piece.Be provided with winding 441 in transformer 404 one time, a described winding 441 and thyristor 413 are connected in series, and are provided for the described circuit that is connected in series from the input direct voltage of upstream rectifying filter circuit 411.

The control end of thyristor 413 is connected on the voltage control circuit 414, constitutes like this, that is: the conducting state of thyristor 413 and cut-off state are subjected to the control of the signal that voltage control circuit 414 exported.

In transformer 404, be provided with winding 441 and have the secondary winding 442 of magnetic coupling relation and have the auxiliary winding 443 of magnetic coupling relation with winding 441 and secondary winding 442.If thyristor 413 carries out switch work, discontinuous current ground flows through winding 441 one time, is just brought out on secondary winding 442 and auxiliary winding 443 and produces voltage.

Downstream current rectifying and wave filtering circuit 421 to being carried out rectifying and wave-filtering by the voltage that brings out and be created on the secondary winding 442, generates VD, again from

output

426 and 427 these VD of output.Particularly, downstream current rectifying and wave filtering circuit 421 has diode 422, choking-winding 423, first output capacitor 424 and second output capacitor 425.The choking-winding 423 and first output capacitor 424 and second output capacitor 425, be connected to each other shape for π, be made as such, that is: carried out halfwave rectifier by the voltage that brings out and be created on the secondary winding 442 by diode 422, carried out filtering by choking-winding 423, first output capacitor 424 and second output capacitor 425 again.

Be created in the voltage at auxiliary winding 443 two ends, be imported into by voltage control circuit 414 in the control end of thyristor 413.In other words, switching power unit shown in Figure 36 is that (ringing choke converter: the device of mode ring chokes converter), thyristor 413 carries out self-energizing switches work according to the voltage that is created on the auxiliary winding 443 to RCC.

Voltage between the

output

426 and 427 feeds back to voltage control circuit 414 by optical coupler 429.Such as, under the situation that voltage between

output

426 and 427 has descended, voltage control circuit 414 prolongs the ON time of thyristor 413 forcibly, on the contrary, under the situation that the voltage between

output

426 and 427 has risen, voltage control circuit 414 shortens the ON time of thyristor 413 forcibly.Like this, the voltage that appears on

output

426 and 427 just is maintained certain constant value.

Because in voltage control circuit 414 inside, utilize the voltage brought out and to be created on the auxiliary winding 443 to generate complementary direct voltage, so when starting except switching power unit, this complementary direct voltage of voltage control circuit 414 usefulness carries out work.

Remark additionally, when switching power unit starts, when promptly beginning between

input

416 and 417, to apply alternating voltage, because thyristor 413 does not also carry out switch work, so auxiliary winding 443 is not brought out the generation of voltage, thereby voltage control circuit 414 is in non-powered state.Therefore, begin to carry out switch work, provide the low-voltage that is suitable for making voltage control circuit 414 startups from upstream rectifying filter circuit 411 by being arranged on outside resistance 451 (high withstand voltage, high-power) in order to make thyristor 413.

In above-mentioned Switching Power Supply, loss is main generation in thyristor 413.Under normal conditions, with MOSFET (Metal Oxide Semiconductor Field-EffectTransistor: mos field effect transistor) as this switch element 413.In general, in bipolar transistor, the switching losses when conducting state switches to cut-off state is bigger, and in MOSFET, because switching speed is very fast, so switching losses is less.But then, in MOSFET, because conducting resistance is bigger, so can not ignore the conducting loss, this point is different with bipolar transistor.Therefore, flow through under the situation of MOSFET, cause bigger loss at big electric current.

In recent years, except one pole type MOSFET, in addition minority carrier is injected into ambipolar IGBT (the Insulated Gate Bipolar Transistor: igbt) receive much concern in the drift layer in the switch power technology field.In existing switching power unit shown in Figure 36, use under the situation of IGBT as switch element 413, because with bipolar transistor conductivity modulation takes place the samely, so conducting resistance is less, but because utilize minority carrier, so switching speed is slower, consequently switching losses is bigger.

In the Switching Power Supply of above-mentioned RCC mode, be connected under the bigger situation of load on

output

426 and 427, the switching frequency of switch element 413 reduces, and the ON time of switch element 413 prolongs.Consequently, big electric current flows through winding 441 one time, thereby the voltage between output 426 and the output 427 is maintained certain constant value.On the contrary, as standby, load less in, the switching frequency of switch element 413 raises, ON time shortens.Consequently, the electric current that flows through a winding 441 reduces, thereby the voltage between output 426 and the output 427 is maintained certain constant value.

Therefore, considering that synthetically switching losses and conducting lose under the situation of these two kinds of losses, under the very big situation of load,, help IGBT so be unfavorable for MOSFET because frequency is low, electric current is big.On the contrary, as standby, load very little in because frequency height, electric current are little, be unfavorable for IGBT so help MOSFET.

Figure 37 is to be illustrated in MOSFET (laterally, drift region have reduction surface field (RESURF) structure) and IGBT (laterally) are respectively applied under the situation in the Switching Power Supply, to load and the result's that compares of the relation between losing figure.As shown in figure 37, in that side of power output little (load is little), because the switching frequency height, so the loss of IGBT is bigger; In that side of power output big (load is big), because switching frequency is low, so the loss of MOSFET is bigger.

[patent documentation 1] Japanese publication communique spy opens flat 7-153951 communique

[patent documentation 2] Japanese publication communique spy opens the 2002-345242 communique

The special fair 6-52791 communique (No. 5072268 specification of United States Patent (USP)) of [patent documentation 3] Japan bulletin patent gazette

No. 2629437 communique of [patent documentation 4] Japan Patent

No. 4811075 specification of [patent documentation 5] United States Patent (USP)

No. 5313082 specification of [patent documentation 6] United States Patent (USP)

[patent documentation 7] Japanese publication communique spy opens flat 8-213617 communique

[patent documentation 8] Japanese publication communique spy opens 2007-115871 communique (U.S. Patent application 11/582441)

[non-patent literature 1] D.S.Byeon and other, The separated shorted-anodeinsulated gate bipolar transistor with the suppressed negativedifferntial resistance regime, Microelectronics Journal 30,1999, p.571-575

As mentioned above, under with the situation of MOSFET as switch element, the conducting loss when load is very big is bigger; With under the situation of IGBT as switch element, when awaiting orders and the switching losses of load when very little bigger.Therefore, in existing thyristor, be difficult to lowering loss to load in the gamut till when very big when very little from load.

In patent documentation 1, there is people's motion to cross and makes vertical IGBT and vertical power MOSFET be present in the interior structure of chip piece of switch element jointly.Yet in described structure, vertically the current capacity of the driving force of the vertical relatively IGBT of power MOSFET is too little.Consequently, actual using just is difficult to driving power MOSFET when load is very little.And, in this structure, because need form step at the Semiconductor substrate back side, so in manufacturing process, have any problem.

In patent documentation 2, there is people's motion to cross the structure as switch element with Schottky junction type IGBT.But in this Schottky junction type IGBT, because the loss specific power MOSFET of load when very little is big, the loss when load is very big is also bigger than existing IGBT, so not necessarily can be regarded as the structure that gets along with aspect the loss attenuating based on the structure of patent documentation 2.

And, because patent documentation 1 and 2 disclosed switch elements all have vertical structure, so for example under with the described situation of switch element with vertical structure, be difficult to voltage control circuit 414 and thyristor 413 are formed in the chip piece as the thyristor 413 of existing switching power unit shown in Figure 36.This also is a problem.

Though purpose do not lie in be made as can utilize an element use selectively MOSFET and IGBT the two, but in non-patent literature 1 and patent documentation 3, the transversal I GBT that has people's motion to cross to have the anode in short circuit structure is as the semiconductor element of the intermediateness effect between performance MOSFET and the IGBT.

Figure 38 is a profile, one of transversal I GBT that the expression patent documentation is 3 disclosed, have anode in short circuit structure example.In structure shown in Figure 38, P ⁺Type bag district (pocket) 514 and N ⁺ Type bag district 515 is by drain electrode 513 short circuits.In this anode in short circuit transversal I GBT, when applying forward bias between drain electrode 513 and source electrode 505, and when being applied to positive voltage on the gate electrode 512, electric current begins from N ⁺ Type bag district 515 is through N ⁺ Type source region 507 flows to source electrode 505 (MOSFET work).Afterwards, be positioned at P in the N type well region 503 ⁺The current potential of the part of type bag district 514 downsides descends to such an extent that compare P ⁺When the 0.6V left and right sides was hanged down in type bag district 514, the hole began from P ⁺ Type bag district 514 is injected in the N type well region 503, becomes the IGBT operating state.Because when signal was ended, electronics was discharged to N from N type well region 503 ⁺In the type bag district 515, so anode in short circuit transversal I GBT shown in Figure 38 has very fast these characteristics of switch work.And this switch element has transversary, thereby, also voltage control circuit 414 and thyristor 413 can be formed in the chip piece for example under the situation as thyristor shown in Figure 36 413 with this switch element.

Yet,, also be difficult to lowering loss to load in the gamut till when very big when very little from load even adopt anode in short circuit transversal I GBT shown in Figure 38 as switch element.Its reason is: because in this switch element, have only the P of establishing ⁺The length 523 in type bag district 514 is bigger value, and switch element could be transferred to IGBT work from MOSFET work easily, so also carry out MOSFET work at the load area that preferably carries out IGBT work originally, consequently loss increases.If establish P ⁺The length 523 in type bag district 514 is bigger value, at P ⁺Just be easy to generate potential difference between type bag district 514 and the N type well region 503, switch element is transferred to IGBT work easily.But, establishing P ⁺The length 523 in type bag district 514 is that the unit are of element is bigger under the situation of bigger value.Consequently, all very big when MOSFET works and during IGBT work in the conducting resistance of element, increase causes damage.

Therefore, from practical aspect,, also be difficult to lowering loss to load in the gamut till when very big when very little from load even anode in short circuit transversal I GBT that will be as shown in figure 38 is used for switching power unit.

Summary of the invention

The present invention, described problem researchs and develops out in order to solve just.Its purpose is: provide a kind of can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

In order to reach above-mentioned purpose, first semiconductor device involved in the present invention, comprise: second conductivity type reduces surface field zone, the first conductivity type base region, the second conductivity type emitter region, first grid dielectric film, first grid electrode, the first conductivity type top semiconductor layer, the first conductive collector zone, collector electrode and emitter electrode, and this second conductivity type reduces the surface field zone and is formed in the surface portion of the first conductive-type semiconductor substrate; This first conductivity type base region is formed in the described Semiconductor substrate in the mode adjacent with described reduction surface field zone; This second conductivity type emitter region is formed in the described base region in the mode with described reduction surface field zone isolation; This first grid dielectric film forms the part between described emitter region and described reduction surface field zone that covers in the described base region; This first grid electrode is formed on the described first grid dielectric film; This first conductivity type top semiconductor layer is formed in the surface portion in described reduction surface field zone, and is electrically connected with described base region; This first conductive collector zone is formed in the surface portion in described reduction surface field zone in the mode with described top semiconductor layer isolation, and have identical with described top semiconductor layer basically impurity concentration, be positioned at the same with described top semiconductor layer basically dark position; This collector electrode is formed on the described Semiconductor substrate, and is electrically connected with described collector region; This emitter electrode is formed on the described Semiconductor substrate, and is electrically connected with described base region and described emitter region.

In other words, first semiconductor device of the present invention is transversal I GBT, and the impurity concentration of establishing the collector region in this IGBT is the low concentration roughly the same with the impurity concentration of top semiconductor layer.Therefore, compare with the situation that has formed the collector region with the high impurity concentration layer, the amount that can will be injected into the excess carrier in the Semiconductor substrate when IGBT works suppresses manyly.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Forming with the high impurity concentration layer under the situation of collector region, need and reduce that second conductivity type buffer layer that impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in first semiconductor device of the present invention,,, operation can be simplified so do not need to be provided with second conductivity type buffer layer because formed the collector region with low impurity concentration.

Remark additionally, in this case specification, " having substantially the same impurity concentration " is meant that the impurity concentration difference is 1 * 10 ¹/ cm ³About following (that is, the both is in the scope of same exponential order during with exponential representation), " being positioned at equally dark basically position " be meant depth difference be about 1 μ m below.

Second semiconductor device involved in the present invention, comprise: second conductivity type reduces surface field zone, the first conductivity type base region, second conductivity type emitter source region, first grid dielectric film, first grid electrode, the first conductivity type top semiconductor layer, the first conductive collector zone, the second conductivity type drain region, collector electrode drain electrode and the emitter source electrode of holding concurrently of holding concurrently of holding concurrently, and this second conductivity type reduces surface field zone and is formed in the surface portion of the first conductive-type semiconductor substrate; This first conductivity type base region is formed in the described Semiconductor substrate in the mode adjacent with described reduction surface field zone; This second conductivity type emitter source region of holding concurrently is formed in the described base region in the mode with described reduction surface field zone isolation; This first grid dielectric film form cover in the described base region in hold concurrently part between source region and the described reduction surface field zone of described emitter; This first grid electrode is formed on the described first grid dielectric film; This first conductivity type top semiconductor layer is formed in the surface portion in described reduction surface field zone, and is electrically connected with described base region; This first conductive collector zone is formed in the surface portion in described reduction surface field zone in the mode with described top semiconductor layer isolation, and have identical with described top semiconductor layer basically impurity concentration, be positioned at the same with described top semiconductor layer basically dark position; This second conductivity type drain region is formed in the surface portion in described reduction surface field zone in the mode with described top semiconductor layer isolation; This collector electrode drain electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described collector region and described drain region respectively; This emitter source electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described base region and the described emitter source region of holding concurrently respectively.

In other words, second semiconductor device of the present invention is the semiconductor device that how much carries out MOSFET work or IGBT work according to the collector current amount.In this semiconductor device, the impurity concentration of establishing the collector region is the low concentration roughly the same with the impurity concentration of top semiconductor layer.Therefore, compare with the situation that has formed the collector region with the high impurity concentration layer, the amount that can will be injected into the excess carrier in the Semiconductor substrate when IGBT works suppresses manyly.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Forming with the high impurity concentration layer under the situation of collector region, need and reduce that second conductivity type buffer layer that impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in second semiconductor device of the present invention,,, operation can be simplified so do not need to be provided with second conductivity type buffer layer because formed the collector region with low impurity concentration.And, can avoid the generation of following situation, that is: because be provided with second conductivity type buffer layer, so more difficult from the work switching of IGBT work of MOSFET.

In second semiconductor device of the present invention, preferably such, described collector region and described drain region are made of a plurality of parts of keeping apart respectively; With from described collector region on described emitter is held concurrently the vertical direction of the direction of source region, be arranged alternately the various piece of described collector region and the various piece of described drain region.

In such event, just can be in the semiconductor device that how much carries out MOSFET work or IGBT work according to the collector current amount, the length of the various piece by changing the collector region is easily adjusted the collector voltage Vch when MOSFET work switches to IGBT work.

In of the present invention first or second semiconductor device, preferably such, described semiconductor device also comprises second grid dielectric film and second grid electrode, this second grid dielectric film is formed on the described reduction surface field zone, extends on the described top semiconductor layer from described collector region; This second grid electrode is formed on the described second grid dielectric film.

In such event, the second grid electrode is conducting when described first or second semiconductor device ends just, thereby can further extract excess carrier out from top semiconductor layer, thereby can further shorten to the required time of extraction of charge carrier.Therefore, can further improve switching speed.

In this case, be more preferably such, described semiconductor device also comprises the first conductivity type flush type semiconductor layer, this first conductivity type flush type semiconductor layer is formed in the described reduction surface field zone in the mode that contacts with described top semiconductor layer, and is electrically connected with described base region.

In such event, because in reducing the surface field zone, also be formed with the flush type semiconductor layer, so IGBT work by the time, except from top semiconductor layer, can also from the flush type semiconductor layer, extract out efficiently and residue in the excess carrier that reduce in the surface field zone, thereby can further shorten to the required time of extraction of charge carrier.Therefore, can further improve switching speed.Compare with the situation that in reducing the surface field zone, has only formed top semiconductor layer, because can form depletion layer from both direction about the flush type semiconductor layer edge, so can make the impurity concentration that reduces the surface field zone higher, thereby can seek the improvement of switching speed and the attenuating of conducting resistance.

First manufacturing method for semiconductor device involved in the present invention is in order to make of the present invention first or the method for second semiconductor device, to comprise the operation that forms described top semiconductor layer and described collector region by same implanted dopant process at least.

According to first manufacturing method for semiconductor device of the present invention, because form top semiconductor layer and collector region by same implanted dopant process, so compare with separating the situation that forms semiconductor layer and collector region, can make operation quantity still less, thereby can seek the attenuating of cost.

The 3rd semiconductor device involved in the present invention, comprise: second conductivity type reduces surface field zone, the first conductivity type base region, the second conductivity type emitter region, gate insulating film, gate electrode, the first conductivity type flush type semiconductor layer, the first conductive collector zone, the first conductive collector contact area, collector electrode and emitter electrode, and this second conductivity type reduces the surface field zone and is formed in the surface portion of the first conductive-type semiconductor substrate; This first conductivity type base region is formed in the described Semiconductor substrate in the mode adjacent with described reduction surface field zone; This second conductivity type emitter region is formed in the described base region in the mode with described reduction surface field zone isolation; This gate insulating film forms the part between described emitter region and described reduction surface field zone that covers in the described base region; This gate electrode is formed on the described gate insulating film; This first conductivity type flush type semiconductor layer is formed in the described reduction surface field zone, and is electrically connected with described base region; This first conductive collector zone is formed in the described reduction surface field zone in the mode with described flush type semiconductor layer isolation, and have basically and the identical impurity concentration of described flush type semiconductor layer, be positioned at the same with described flush type semiconductor layer basically dark position; This first conductive collector contact area is formed in the surface portion in described reduction surface field zone in the mode that contacts with described collector region; This collector electrode is formed on the described Semiconductor substrate, and is electrically connected with described collector contact area; This emitter electrode is formed on the described Semiconductor substrate, and is electrically connected with described base region and described emitter region.

In other words, the 3rd semiconductor device of the present invention is transversal I GBT.Because in this IGBT, if the impurity concentration of collector region is the low concentration roughly the same with the impurity concentration of flush type semiconductor layer, so compare with the situation that has formed the collector region with the high impurity concentration layer, the amount that can will be injected into the excess carrier in the Semiconductor substrate when IGBT works suppresses manyly.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

According to the 3rd semiconductor device of the present invention, because in reducing the surface field zone, be formed with the flush type semiconductor layer, so can form depletion layer from both direction about the flush type semiconductor layer edge.Therefore, can make the impurity concentration that reduces the surface field zone higher, thereby can seek the improvement of switching speed and the attenuating of conducting resistance.

Forming with the high impurity concentration layer under the situation of collector region, need and reduce that second conductivity type buffer layer that impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the 3rd semiconductor device of the present invention,,, operation can be simplified so do not need to be provided with second conductivity type buffer layer because formed the collector region with low impurity concentration.

The 4th semiconductor device involved in the present invention, comprise: second conductivity type reduces surface field zone, the first conductivity type base region, second conductivity type emitter source region, gate insulating film, gate electrode, the first conductivity type flush type semiconductor layer, the first conductive collector zone, the first conductive collector contact area, the second conductivity type drain region, collector electrode drain electrode and the emitter source electrode of holding concurrently of holding concurrently of holding concurrently, and this second conductivity type reduces surface field zone and is formed in the surface portion of the first conductive-type semiconductor substrate; This first conductivity type base region is formed in the described Semiconductor substrate in the mode adjacent with described reduction surface field zone; This second conductivity type emitter source region of holding concurrently is formed in the described base region in the mode with described reduction surface field zone isolation; This gate insulating film form cover in the described base region in hold concurrently part between source region and the described reduction surface field zone of described emitter; This gate electrode is formed on the described gate insulating film; This first conductivity type flush type semiconductor layer is formed in the described reduction surface field zone, and is electrically connected with described base region; This first conductive collector zone is formed in the described reduction surface field zone in the mode with described flush type semiconductor layer isolation, and have basically and the identical impurity concentration of described flush type semiconductor layer, be positioned at the same with described flush type semiconductor layer basically dark position; This first conductive collector contact area is formed in the surface portion in described reduction surface field zone in the mode that contacts with described collector region; This second conductivity type drain region is formed in the surface portion in described reduction surface field zone in the mode with described flush type semiconductor layer isolation; This collector electrode drain electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described collector contact area and described drain region respectively; This emitter source electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described base region and the described emitter source region of holding concurrently respectively.

In other words, the 4th semiconductor device of the present invention is the semiconductor device that how much carries out MOSFET work or IGBT work according to the collector current amount.Because in this semiconductor device, if the impurity concentration of collector region is the low concentration roughly the same with the impurity concentration of flush type semiconductor layer, so compare with the situation that has formed the collector region with the high impurity concentration layer, the amount that can will be injected into the excess carrier in the Semiconductor substrate when IGBT works suppresses manyly.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

According to the 4th semiconductor device of the present invention, because in reducing the surface field zone, be formed with the flush type semiconductor layer, so can form depletion layer from both direction about the flush type semiconductor layer edge.Therefore, can make the impurity concentration that reduces the surface field zone higher, thereby can seek the improvement of switching speed and the attenuating of conducting resistance.

Forming with the high impurity concentration layer under the situation of collector region, need and reduce that second conductivity type buffer layer that impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the 4th semiconductor device of the present invention,,, operation can be simplified so do not need to be provided with second conductivity type buffer layer because formed the collector region with low impurity concentration.And, can avoid the generation of following situation, that is: because be provided with second conductivity type buffer layer, so more difficult from the work switching of IGBT work of MOSFET.

In the 4th semiconductor device of the present invention, preferably such, described collector region and described drain region are made of a plurality of parts of keeping apart respectively; With from described collector region on described emitter is held concurrently the vertical direction of the direction of source region, be arranged alternately the various piece of described collector region and the various piece of described drain region.

Second manufacturing method for semiconductor device involved in the present invention is in order to make the of the present invention the 3rd or the method for the 4th semiconductor device, to comprise the operation that forms described flush type semiconductor layer and described collector region by same implanted dopant process at least.

According to second manufacturing method for semiconductor device of the present invention, because form flush type semiconductor layer and collector region by same implanted dopant process, so with separate the situation that forms flush type semiconductor layer and collector region and compare, operation quantity can be made still less, thereby the attenuating of cost can be sought.

Remark additionally, in first to the 4th semiconductor device of the present invention, if gate insulating film is (in first and second semiconductor device of the present invention, be the first grid dielectric film) be formed into emitter region (in the of the present invention second and the 4th semiconductor device, be the emitter source region of holding concurrently) on, gate electrode and emitter region short circuit just can be prevented.

The effect of-invention-

According to the present invention, residue in the amount of the excess carrier in the Semiconductor substrate because can lower when ending, extract the required time of charge carrier out so can shorten to, thereby can improve switching speed, thereby can seek the attenuating of switching losses.Therefore, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Description of drawings

Fig. 1 is the profile of the related semiconductor device of the first embodiment of the present invention.

Fig. 2 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 3 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 4 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 5 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 6 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 7 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression first embodiment of the present invention is related.

Fig. 8 (a) is the profile (along the profile of the C-C ' line among Fig. 8 (b)) of the related semiconductor device of the second embodiment of the present invention; Fig. 8 (b) is the plane graph of the related semiconductor device of the second embodiment of the present invention.

Fig. 9 is the profile (along the profile of the D-D ' line among Fig. 8 (b)) of the related semiconductor device of the second embodiment of the present invention.

Figure 10 is expression to be changed to object with related semiconductor device of the second embodiment of the present invention and the related semiconductor device of comparative example and to have measured fall time tf to the result's of dependence on temperature figure.

Figure 11 is that expression is changed to object with related semiconductor device of the second embodiment of the present invention and the related semiconductor device of comparative example and has measured the figure of conducting resistance Ron to the result of dependence on temperature.

Figure 12 (a) is the profile (along the profile of the E-E ' line among Figure 12 (b)) of the related semiconductor device of the third embodiment of the present invention; Figure 12 (b) is the plane graph of the related semiconductor device of the third embodiment of the present invention.

Figure 13 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 14 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 15 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 16 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 17 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 18 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression third embodiment of the present invention is related.

Figure 19 is the profile of the related semiconductor device of the fourth embodiment of the present invention.

Figure 20 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 21 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 22 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 23 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 24 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 25 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fourth embodiment of the present invention is related.

Figure 26 is the profile of the related semiconductor device of the fifth embodiment of the present invention.

Figure 27 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 28 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 29 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 30 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 31 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 32 is a profile, the one procedure of the manufacture method of the semiconductor device that the expression fifth embodiment of the present invention is related.

Figure 33 (a) is the profile (along the profile of the A-A ' line among Figure 33 (b)) of the related semiconductor device of comparative example; Figure 33 (b) is the plane graph of the related semiconductor device of comparative example.

Figure 34 is the profile (along the profile of the B-B ' line among Figure 33 (b)) of the related semiconductor device of comparative example.

Figure 35 is the collector voltage in the related semiconductor device of expression comparative example and the figure of the relation between the collector current.

Figure 36 is the figure of one of the circuit structure example of the existing switching power unit of expression.

Figure 37 is to be illustrated in MOSFET (laterally, drift region have reduce the surface field structure) and IGBT (laterally) are respectively applied under the situation in the Switching Power Supply, to load and the result's that compares of the relation between losing figure.

Figure 38 is a profile, one of existing anode in short circuit transversal I GBT of expression example.

Symbol description

The 101-Semiconductor substrate; 102-reduces the surface field zone; The 103-gate insulating film; 104-electric field dielectric film; The 105-top semiconductor layer; The 106-base region; The 107-gate electrode; The 108-emitter source region of holding concurrently; The 109-collector region; The 110-contact area; 111-interlayer film; The 112-collector electrode drain electrode of holding concurrently; The 113-emitter source electrode of holding concurrently; The 114-diaphragm; The 116-drain electrode; The 201-Semiconductor substrate; 202-reduces the surface field zone; 203-gate insulating film (first grid dielectric film); 204-electric field dielectric film; The 205-top semiconductor layer; The 206-base region; 207-gate electrode (first grid electrode); 208-emitter region (emitter hold concurrently source region); The 209-collector contact area; The 210-contact area; 211-interlayer film; 212-collector electrode (collector electrode hold concurrently drain electrode); 213-emitter electrode (emitter hold concurrently source electrode); 214-protects and expands film; The 215-collector region; The 216-drain region; 217-flush type semiconductor layer; The 218-collector region; The 219-collector contact area; 220-second grid dielectric film; 221-second grid electrode; The 222-top semiconductor layer.

Embodiment

(first embodiment)

Below, with reference to accompanying drawing to the first embodiment of the present invention related semiconductor device, particularly high-breakdown voltage semiconductor switching device is described.

Fig. 1 represents the cross-section structure of the semiconductor device that first embodiment is related.As shown in Figure 1, for example be P ^-(impurity concentration for example is 1 * 10 to the Semiconductor substrate 201 of type ¹⁴/ cm ³) surface portion in, for example be formed with that (impurity concentration for example is 1 * 10 for the reduction surface field zone 202 of N type ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, also being formed with in the mode adjacent with reducing surface field zone 202 in the surface portion of Semiconductor substrate 201 for example is that (impurity concentration for example is 1 * 10 for the base region 206 of P type ¹⁶/ cm ³, the degree of depth has 4 μ m).

In base region 206, for example be P to be formed with the mode that reduces by 202 isolation of surface field zone ⁺(impurity concentration for example is 1 * 10 to the contact area 210 of type ¹⁹/ cm ³, the degree of depth has 2 μ m) and for example be N ⁺(impurity concentration for example is 1 * 10 to the emitter region 208 of type ²⁰/ cm ³, the degree of depth has 0.5 μ m).In addition, be formed with the gate insulating film 203 that covers the part between emitter region 208 and reduction surface field zone 202 in the base region 206, on gate insulating film 203, be formed with gate electrode 207.

Remark additionally,, just can prevent gate electrode 207 and emitter region 208 short circuits if gate insulating film 203 is formed on the emitter region 208.

In the surface portion that reduces surface field zone 202, be formed with that for example (impurity concentration for example is 1 * 10 for the top semiconductor layer 205 of P type ¹⁶/ cm ³, the degree of depth has 1 μ m).Though do not show in the accompanying drawings, this top semiconductor layer 205 is electrically connected with base region 206 via established part that reduces surface field zone 202 or the wiring etc. that is positioned at the upper strata.

In the surface portion that reduces surface field zone 202, being formed with in the mode of isolating with top semiconductor layer 205 for example is that (impurity concentration for example is 1 * 10 for the collector region 215 of P type ¹⁶/ cm ³, the degree of depth has 1 μ m).At this, collector region 215 has basically the impurity concentration identical with top semiconductor layer 205, is positioned at basically and top semiconductor layer 205 the same dark positions.

In the surface portion of collector region 215, being formed with for example is P ⁺(impurity concentration for example is 1 * 10 to the collector contact area 209 of type ¹⁹/ cm ³, the degree of depth has 0.5 μ m).Remark additionally, also can not form collector contact area 209.

Be formed with on the Semiconductor substrate 201 of above-mentioned each extrinsic region etc., be formed with interlayer film 211 across being formed on the lip-deep electric field dielectric film 204 that reduces surface field zone 202.

On Semiconductor substrate 201, be formed with collector electrode 212 and emitter electrode 213, this collector electrode 212 has run through interlayer film 211, is electrically connected with collector contact area 209 (that is, the collector region 215); This emitter electrode 213 has run through interlayer film 211, all is electrically connected with contact area 210 (that is, base region 206) and emitter region 208.

On the interlayer film 211 that is formed with collector electrode 212 and emitter electrode 213, be formed with diaphragm 214.

In the semiconductor device of present embodiment, (make collector electrode 212 1 sides become high potential) forward bias being put between collector electrode 212 and the emitter electrode 213, again positive voltage is applied under the situation on the gate electrode 207, when the current potential of collector region 215 and when reducing potential difference between the current potential of the part of surrounding collector region 215 in the surface field zone 202 and reaching 0.6V approximately, the hole 215 is injected into and reduces surface field zone 202 from the collector region, and this semiconductor device begins to carry out IGBT work.

In other words, the semiconductor device of present embodiment (switch element) is transversal I GBT.In this IGBT, the impurity concentration of establishing collector region 215 is the low concentration roughly the same with the impurity concentration of top semiconductor layer 205.Therefore, with usefulness high impurity concentration layer (P ⁺Layer) situation that has formed the collector region is compared, and can will be injected into the excess carrier amount that comprises in the Semiconductor substrate 201 that reduces surface field zone 202 and suppress manyly when IGBT works.Consequently, can lower the excess carrier amount that when ending, residues in the Semiconductor substrate 201.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Forming with the high impurity concentration layer under the situation of collector region, need be in the collector region and reduce be provided with between the surface field zone impurity concentration be higher than reduce the surface field zone, for example be the resilient coating of N type, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the semiconductor device of present embodiment,,, operation can be simplified so do not need to be provided with N type resilient coating because formed collector region 215 with low impurity concentration.

Below,, one of the manufacture method of switch element shown in Figure 1, present embodiment example is described to these profiles of Fig. 7 with reference to Fig. 2.

At first, in operation shown in Figure 2, for example injecting in impurity concentration by phosphonium ion for example is 1 * 10 ¹⁴/ cm ³About P ^-Optionally forming in the surface portion of N-type semiconductor N substrate 201 for example is the reduction surface field zone 202 of N type.The impurity concentration that reduces surface field zone 202 for example is 1 * 10 ¹⁶/ cm ³About, the formation degree of depth that reduces surface field zone 202 for example is about 7 μ m.

Then, in operation shown in Figure 3, inject to form simultaneously and optionally by the boron ion and for example be the top semiconductor layer 205 of P type and for example be the collector region 215 of P type at the surface portion that reduces surface field zone 202.At this, top semiconductor layer 205 and collector region 215 are formed the state of keeping apart mutually.The impurity concentration of the impurity concentration of top semiconductor layer 205 and collector region 215 for example is respectively 1 * 10 ¹⁶/ cm ³About, the formation degree of depth of top semiconductor layer 205 and collector region 215 for example is respectively about 1 μ m.

Remark additionally, though do not show in the accompanying drawings, top semiconductor layer 205 forms with base region 206 described later and is electrically connected.

Then, in operation shown in Figure 4, injecting the surface portion formation in Semiconductor substrate 201 by the boron ion for example is the base region 206 of P type.Base region 206 forms with to reduce surface field zone 202 adjacent.The impurity concentration of base region 206 for example is 1 * 10 ^16/Cm ³About, the formation degree of depth of base region 206 for example is 4 μ m.In addition, for example wait to come on the surface that reduces surface field zone 202, optionally to form thickness and for example be the electric field dielectric film 204 of 500nm by wet oxidation.At this moment, the diffusion of impurities of top semiconductor layer 205 makes the impurity concentration of top semiconductor layer 205 descend a bit.

Remark additionally, in the present embodiment, in order to form order that ion that each extrinsic region implements injects and unrestricted.

Then, in operation shown in Figure 5, for example form the gate insulating film 203 that covers the part between emitter region 208 described later and reduction surface field zone 202 in the base region 206 by thermal oxidation.Afterwards, on gate insulating film 203, optionally form the gate electrode 207 that for example constitutes by polysilicon.In addition, as mask, for example waiting next optionally formation with self-aligned by the arsenic ion injection in base region 206 for example is N with gate electrode 207 ⁺The emitter region 208 of type.Emitter region 208 forms and reduces by 202 isolation of surface field zone.The impurity concentration of emitter region 208 for example is 1 * 10 ²⁰/ cm ³About, the formation degree of depth of emitter region 208 for example is about 0.5 μ m.

Then, in operation shown in Figure 6, for example injecting next formation by the boron ion in base region 206 for example is P ⁺The contact area 210 of type.Contact area 210 forms and reduces surface field zone 202 and isolate.The impurity concentration of contact area 210 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of contact area 210 for example is 2 μ m.Afterwards, for example injecting in the collector region 215 surface portion to form by the boron ion for example is P ⁺The collector contact area 209 of type.The impurity concentration of collector contact area 209 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of collector contact area 209 for example is 0.5 μ m.Remark additionally, also can omit and do not form collector contact area 209.

Then, in operation shown in Figure 7, for example utilize atmospheric pressure cvd (chemical vapordeposition: chemical vapour deposition (CVD)) method comprise on the electric field dielectric film 204 and gate electrode 207 on Semiconductor substrate 201 on film 211 between cambium layer, then make the established part opening of interlayer film 211, on Semiconductor substrate 201, form collector electrode 212 and emitter electrode 213 more respectively, this collector electrode 212 is electrically connected with collector contact area 209 (that is, the collector region 215); This emitter electrode 213 all is electrically connected with contact area 210 (that is, base region 206) and emitter region 208.At last, after forming the diaphragm 214 that for example constitutes on the interlayer film 211, make the liner in the diaphragm 214 form regional opening by the plasma silicon nitride film.Switch element like this, shown in Figure 1, present embodiment just forms and is over.

Manufacture method according to the present embodiment that describes previously, because form top semiconductor layer 205 and collector region 215 by same implanted dopant process, so form top semiconductor layer 205 and compare with separating with the situation of collector region 215, can make operation quantity still less, can reduce the cost.

(comparative example)

As to high voltage and powerful electricity usage, conducting resistance is very low and cut-off speed is very fast semiconductor device, someone crosses following apparatus at motion, that is: the two structure of lateral double diffusion metal oxide semiconductor (LDMOS) and lateral insulated gate bipolar transistor (LIGBT) is formed on the device (for example, with reference to patent documentation 7) that forms in the same substrate.

Patent documentation 7 disclosed semiconductor devices have double-gate structure, promptly separately are provided with the structure that the drain electrode of the anode of the grid of the grid of LIGBT and LDMOS and LIGBT and LDMOS is kept apart by ditch pocket well (trench well).

This case inventor, once in patent documentation 8, carried and the different structure of patent documentation 7 disclosed semiconductor devices, this structure is can be under the state that does not adopt the ditch pocket well to isolate, and carries out work single grid transversal I GBT structure of these two kinds of work of MOSFET work and IGBT with simple structure.

Below, as a comparative example, with reference to description of drawings this this case inventor semiconductor device disclosed mistake, that have the IGBT structure.Figure 33 (a) and Figure 34 are the profiles of the related semiconductor device of comparative example, and Figure 33 (b) is the plane graph of the related semiconductor device of comparative example.Remark additionally, Figure 33 (a) is the profile along the A-A ' line among Figure 33 (b); Figure 34 is the profile along the B-B ' line among Figure 33 (b).In Figure 33 (b), omitted the diagram of a part of structural factor.

As Figure 33 (a), Figure 33 (b) and shown in Figure 34, at P ^-(impurity concentration for example is 1 * 10 to N-type semiconductor N substrate 101 ¹⁴/ cm ³) surface portion in, be formed with the N type and reduce surface field zone 102 (impurity concentration for example is 1 * 10 ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, in the surface portion of Semiconductor substrate 101, (impurity concentration for example is 1 * 10 also to be formed with P type base region 106 in the mode adjacent with reducing surface field zone 102 ¹⁶/ cm ³, the degree of depth has 4 μ m).

In base region 106, to be formed with P with the mode that reduces by 102 isolation of surface field zone ⁺(impurity concentration for example is 1 * 10 to type contact area 110 ¹⁹/ cm ³, the degree of depth has 2 μ m) and N ⁺The type emitter is held concurrently, and (impurity concentration for example is 1 * 10 in source region 108 ²⁰/ cm ³, the degree of depth has 0.5 μ m).In addition, be formed with the gate insulating film 103 of holding concurrently the part between source region 108 and the reduction surface field zone 102 at emitter in the covering base region 106, on gate insulating film 103, be formed with gate electrode 107.

In the surface portion that reduces surface field zone 102, (impurity concentration for example is 1 * 10 to be formed with the P type top semiconductor layer 105 that is electrically connected with base region 106 ¹⁶/ cm ³, the degree of depth has 1 μ m).

In the surface portion that reduces surface field zone 102, be formed with P in mode with top semiconductor layer 105 isolation ⁺(impurity concentration for example is 1 * 10 to type contact area 109 ¹⁹/ cm ³, the degree of depth has 1 μ m) (especially with reference to Figure 33 (a)).At this, contact area 109 forms its impurity concentration and is higher than top semiconductor layer 105 far away, to lower conducting resistance.

In addition, in the surface portion that reduces surface field zone 102, be formed with the N that is electrically connected with collector region 109 in mode with top semiconductor layer 105 isolation ⁺(impurity concentration for example is 1 * 10 in type drain region 116 ²⁰/ cm ³, the degree of depth has 0.5 μ m) (especially with reference to Figure 34).

At this, shown in Figure 33 (b), collector region 109 and drain region 116 are made of a plurality of parts of keeping apart respectively.With from collector region 109 on emitter is held concurrently the vertical direction of the direction of source region 108, be arranged alternately the various piece of collector region 109 and the various piece of drain region 116.

Be formed with on the Semiconductor substrate 101 of above-mentioned each extrinsic region etc., be formed with interlayer film 111 across being formed on the lip-deep electric field dielectric film 104 that reduces surface field zone 102.

On Semiconductor substrate 101, be formed with collector electrode drain electrode 112 and the emitter source electrode 113 of holding concurrently of holding concurrently, this collector electrode drain electrode 112 of holding concurrently has run through interlayer film 111, all is electrically connected with collector region 109 and drain region 116; This emitter source electrode 113 of holding concurrently has run through interlayer film 111, all is electrically connected with contact area 110 (that is, base region 106) and the emitter source region 108 of holding concurrently.

Hold concurrently on the interlayer film 111 of source electrode 113 being formed with hold concurrently drain electrode 112 and emitter of collector electrode, be formed with diaphragm 114.

In the related semiconductor device of comparative example, when hold concurrently at collector electrode drain electrode 112 and emitter hold concurrently apply between the source electrode 113 forward bias (below, also some place is called collector voltage with this forward bias), and when on gate electrode 107, applying positive voltage, electron stream (below, also some place is called collector current with this electron stream) 116 flow to the emitter source electrode 113 of holding concurrently from the drain region, this semiconductor device carries out MOSFET work thus.When flowing to the hold concurrently electron stream of source electrode 113 of emitter is that the size of collector current acquires a certain degree, when the potential difference in the current potential of collector region 109 and the reduction surface field zone 102 between the current potential of the part of encirclement collector region 109 reaches 0.6V approximately, the hole 109 is injected into and reduces surface field zone 102 from the collector region, and this semiconductor device is transferred to IGBT work from MOSFET work thus.Figure 35 represents collector voltage in the related semiconductor device of this comparative example and the relation between the collector current.

Like this, in the related semiconductor device of comparative example, can hour make this semiconductor device carry out MOSFET work when the collector current that flows through element, make this semiconductor device carry out IGBT work after acquiring a certain degree in the size of the collector current that flows through element.In other words, can realize that basis flows through the semiconductor device that how much carries out MOSFET work or IGBT work of the collector current amount of element.

Remark additionally, in the related semiconductor device of comparative example, collector region 109 and drain region 116 are made of a plurality of parts of keeping apart respectively, with from collector region 109 on emitter is held concurrently the vertical direction of the direction of source region 108, be arranged alternately the various piece of collector region 109 and the various piece of drain region 116.Like this, can make the length on vertical direction (that is, collector region 109 and drain region 116 are arranged direction) of collector region 109 shorter.Therefore, can easily make collector voltage when IGBT work is transferred in MOSFET work (, the collector voltage (for example being about 1V) the when potential difference between the current potential of the current potential of collector region and the part that reduces the encirclement collector region in the surface field zone reaches 0.6V approximately because of the decline of voltage) increase.Therefore, can be by adjusting the collector voltage value that switches to IGBT work from MOSFET work, carry out more practical design, for example enlarge the collector voltage scope (the MOSFET work that is designed to have the speed-sensitive switch function proceed to collector voltage for example reach) in other words, of the MOSFET work can have the speed-sensitive switch performance etc. greater than till the magnitude of voltage about 1V.In other words, for example can freely design the distribution of the lower IGBT work of good MOSFET work of switching characteristic and conducting resistance.

Yet, that related as a comparative example in front semiconductor device describes, carry out in the IGBT course of work, following problems being arranged in the semiconductor device of MOSFET work or IGBT work.

Because the same with bipolar transistor, conductivity modulation takes place in IGBT, thus can seek the attenuating of conducting loss, thereby compare with the much the same MOSFET of its chip size and the chip size of IGBT, can make the power loss of IGBT littler.

But, in the related semiconductor device of comparative example, collector region 109 is formed its impurity concentration is higher than top semiconductor layer 105 far away, to lower conducting resistance.Therefore, when switch to from conducting state the blocking state by the time, the extraction that residues in the excess carrier in Semiconductor substrate 101 inside needs the long time.Therefore, such problem can take place, that is: the switching speed of IGBT is slower than the switching speed of MOSFET, and consequently switching losses is very big, can not lower power loss fully.

If will tackle described problem, just expect that employing limits the method for the ways such as technology in useful life as the switching speed of improving IGBT.But under the situation that has adopted this technology, the thing followed is the increase of cost and the sacrifices such as deterioration of characteristic.Therefore, this way is not really good solution.

In addition, in the related semiconductor device of comparative example, formed collector region 109 because be higher than the high impurity concentration of top semiconductor layer 105 far away with its concentration, so be necessary in collector region 109 and reduce its impurity concentration is set between the surface field zone 102 is higher than the N type resilient coating that reduces surface field zone 102, be injected into the hole injection efficiency that reduces surface field zone 102 to lower from the collector region 109.This can cause the increase of operation quantity, also causes simultaneously to be difficult to switch to IGBT this new problem of working from MOSFET work.

The semiconductor device that describes below, the second embodiment of the present invention is related is the device that solves the variety of issue of the related semiconductor device of above-mentioned comparative example under the state of the deterioration of increase that does not cause cost and characteristic etc.

(second embodiment)

Below, with reference to accompanying drawing, the semiconductor device related to the second embodiment of the present invention particularly describes high-breakdown voltage semiconductor switching device.

Fig. 8 (a) and Fig. 9 are the profiles of the related semiconductor device of second embodiment; Fig. 8 (b) is the plane graph of the related semiconductor device of second embodiment.Remark additionally, Fig. 8 (a) is the profile along the C-C ' line among Fig. 8 (b); Fig. 9 is the profile along the D-D ' line among Fig. 8 (b).In Fig. 8 (b), omitted the diagram of a part of structural factor.

As Fig. 8 (a), Fig. 8 (b) and shown in Figure 9, for example be P ^-(impurity concentration for example is 1 * 10 to the Semiconductor substrate 201 of type ¹⁴/ cm ³) surface portion in, for example be formed with that (impurity concentration for example is 1 * 10 for the reduction surface field zone 202 of N type ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, also being formed with in the mode adjacent with reducing surface field zone 202 in the surface portion of Semiconductor substrate 201 for example is that (impurity concentration for example is 1 * 10 for the base region 206 of P type ¹⁶/ cm ³, the degree of depth has 4 μ m).

In base region 206, for example be P to be formed with the mode that reduces by 202 isolation of surface field zone ⁺(impurity concentration for example is 1 * 10 to the contact area 210 of type ¹⁹/ cm ³, the degree of depth has 2 μ m) and for example be N ⁺The emitter of type is held concurrently, and (impurity concentration for example is 1 * 10 in source region 208 ²⁰/ cm ³, the degree of depth has 0.5 μ m).In addition, be formed with the gate insulating film 203 of holding concurrently the part between source region 208 and the reduction surface field zone 202 at emitter in the covering base region 206, on gate insulating film 203, be formed with gate electrode 207.

Remark additionally, hold concurrently on the source region 208, just can prevent source region 208 short circuits of holding concurrently of gate electrode 207 and emitter if gate insulating film 203 is formed into emitter.

In addition, in the surface portion that reduces surface field zone 202, being formed with in the mode with top semiconductor layer 205 isolation for example is N ⁺(impurity concentration for example is 1 * 10 in the drain region 216 of type ²⁰/ cm ³, the degree of depth has 0.5 μ m).

At this, shown in Fig. 8 (b), collector region 215 and drain region 216 are made of a plurality of parts of keeping apart respectively.With from collector region 215 towards emitter hold concurrently the vertical direction of the direction of source region 208 (below, also some place will this vertical direction be called vertical direction) on, be arranged alternately the various piece of collector region 215 and the various piece of drain region 216.The various piece of collector region 215 for example be about 60 μ m in the length on this vertical direction (length X shown in Fig. 8 (b)); The various piece of drain region 216 for example be about 30 μ m in the length on this vertical direction (the length Y shown in Fig. 8 (b)).

On Semiconductor substrate 201, be formed with collector electrode drain electrode 212 and the emitter source electrode 213 of holding concurrently of holding concurrently, this collector electrode drain electrode 212 of holding concurrently has run through interlayer film 211, all is electrically connected with collector contact area 209 (that is, the collector region 215) and drain region 216; This emitter source electrode 213 of holding concurrently has run through interlayer film 211, all is electrically connected with contact area 210 (that is, base region 206) and the emitter source region 208 of holding concurrently.

Hold concurrently on the interlayer film 211 of source electrode 213 being formed with hold concurrently drain electrode 212 and emitter of collector electrode, be formed with diaphragm 214.

In the related semiconductor device of present embodiment, when hold concurrently at collector electrode drain electrode 212 and emitter hold concurrently apply between the source electrode 213 forward bias (below, also some place is called collector voltage with this forward bias), and when on gate electrode 207, applying positive voltage, electron stream (below, also some place is called collector current with this electron stream) 216 flow to the emitter source electrode 213 of holding concurrently from the drain region, this semiconductor device carries out MOSFET work thus.When flowing to the hold concurrently electron stream of source electrode 213 of emitter is that the size of collector current acquires a certain degree, when the potential difference in the current potential of collector region 215 and the reduction surface field zone 202 between the current potential of the part of encirclement collector region 215 reaches 0.6V approximately, the hole 215 is injected into and reduces surface field zone 202 from the collector region, and this semiconductor device is transferred to IGBT work from MOSFET work thus.

Like this, in the related semiconductor device of present embodiment, can hour make this semiconductor device carry out MOSFET work when the collector current that flows through element, make this semiconductor device carry out IGBT work after acquiring a certain degree in the size of the collector current that flows through element.In other words, can realize that basis flows through the semiconductor device that how much carries out MOSFET work or IGBT work of the collector current amount of element.In the related semiconductor device of described present embodiment because the impurity concentration of establishing collector region 215 is the low concentration roughly the same with the impurity concentration of top semiconductor layer 205, so with high impurity concentration layer (P ⁺Layer) situation (comparative example) that has formed the collector region is compared, and can will be injected into the amount that comprises the excess carrier in the Semiconductor substrate 201 that reduces surface field zone 202 and suppress manyly when IGBT works.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate 201.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Figure 10 is that ((impurity concentration is 1 * 10 with p type semiconductor layer for semiconductor device with Fig. 8 (a), Fig. 8 (b) and present embodiment shown in Figure 9 ¹⁶/ cm ³, the degree of depth has 1 μ m) formed the element of collector region 215) and Figure 33 (a), Figure 33 (b) and the related semiconductor device of comparative example shown in Figure 34 (use P ⁺(impurity concentration is 1 * 10 to type semiconductor layer ¹⁹/ cm ³, the degree of depth has 1 μ m) formed the element of collector region 109) measure fall time tf (after grid ends for object, collector current from be about to by the time 90% value of the value process institute's time spent till dropping to 10% value) to the dependence of temperature (K), the pictorialization as a result that will measure again and the figure that obtains.Remark additionally, in Figure 10, transverse axis is represented temperature (K), and the longitudinal axis is represented tf fall time.Tf fall time (nsec) when temperature 398K in the semiconductor device that comparative example is related is assumed to be 100%, with represent each fall time value have this 100% o'clock fall time the tf value the mode of how many % represent tf fall time.

As shown in figure 10, to have formed in semiconductor device collector region 215, present embodiment with the roughly the same low impurity concentration of the impurity concentration of P type top semiconductor layer 205 and to have used P ⁺The comparative example that type semiconductor layer has formed the collector region by comparison, fall time, tf obtained remarkable improvement on all temps.

Figure 11 is that ((impurity concentration is 1 * 10 with p type semiconductor layer for semiconductor device with Fig. 8 (a), Fig. 8 (b) and present embodiment shown in Figure 9 ¹⁶/ cm ³, the degree of depth has 1 μ m) formed the element of collector region 215) and Figure 33 (a), Figure 33 (b) and the related semiconductor device of comparative example shown in Figure 34 (use P ⁺(impurity concentration is 1 * 10 to type semiconductor layer ¹⁹/ cm ³, the degree of depth has 1 μ m) formed the element of collector region 109) be that object is measured the dependence of conducting resistance Ron to temperature (K), the pictorialization as a result that will measure again and the figure that obtains.Remark additionally, in Figure 11, transverse axis is represented temperature (K), and the longitudinal axis is represented conducting resistance Ron.The conducting resistance Ron (Ω) when the temperature 223K in the semiconductor device of present embodiment is assumed to be 100%, has the mode of how many % of this conducting resistance Ron value of 100% o'clock to represent conducting resistance Ron to represent each conduction resistance value.

As shown in figure 11, to have formed in semiconductor device collector region 215, present embodiment, also can obtain and use P with the roughly the same low impurity concentration of the impurity concentration of P type top semiconductor layer 205 ⁺Type semiconductor layer has formed the roughly the same conduction resistance value of conduction resistance value in the comparative example of collector region.Though in temperature was lower than the scope of 250K, the conduction resistance value of the semiconductor device of present embodiment was higher slightly, the actual scope of application of this semiconductor device arrives 400K (about 20 ℃ to 140 ℃) about 250K greatly, thereby no problem.

By the measurement result of the Figure 10 that illustrates previously and Figure 11 as seen, to have formed in semiconductor device collector region 215, present embodiment, can access increasing hardly and result from the effect that lowers switching losses under the state of loss of conducting resistance Ron greatly with the roughly the same low impurity concentration of the impurity concentration of P type top semiconductor layer 205.

Using high impurity concentration layer (P ⁺Type semiconductor layer) formed in the comparative example of collector region, need and reduce that the N type resilient coating that its impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the semiconductor device of present embodiment,,, operation can be simplified so do not need to be provided with N type resilient coating because formed collector region 215 with low impurity concentration.And, can avoid the generation of following situation, that is: as comparative example, because be provided with N type resilient coating, so more difficult from the work switching of IGBT work of MOSFET.

Remark additionally, in the manufacture method of the semiconductor device (switch element) of Fig. 8 (a), Fig. 8 (b) and present embodiment shown in Figure 9, can with first embodiment in Fig. 2 be used for making (promptly to the same mode of each procedure shown in Figure 7 along the profile of the C-C ' line of Fig. 8 (b), Fig. 8 (a)) each procedure of structure, thereby the explanation of omitting these operations.If to be used for making profile along the D-D ' line of Fig. 8 (b) (that is, the operation of structure Fig. 9) is then done just passablely like this, changes the mask floor plan that is:, thus in the operation in first embodiment, shown in Figure 5, at formation N ⁺Form N in the time of type emitter region 208 ⁺Type drain region 216.Remark additionally, the impurity concentration of drain region 216 for example is 1 * 10 ²⁰/ cm ³About, the formation degree of depth of drain region 216 for example is about 0.5 μ m.

(the 3rd embodiment)

Below, with reference to accompanying drawing, the semiconductor device related to the third embodiment of the present invention particularly describes high-breakdown voltage semiconductor switching device.

Figure 12 (a) is the profile of the related semiconductor device of the 3rd embodiment; Figure 12 (b) is the plane graph of the related semiconductor device of the 3rd embodiment.Remark additionally, Figure 12 (a) is the profile along the E-E ' line among Figure 12 (b).Profile along the F-F ' line among Figure 12 (b), be the appearance the same with following figure, that is: in related profile semiconductor device, that be equivalent to Fig. 9 of Fig. 8 (a), Fig. 8 (b) and second embodiment shown in Figure 9, form that flush type semiconductor layer 217 described later replaces top semiconductor layer 205 and the figure that obtains.In Figure 12 (b), omitted the diagram of a part of structural factor.

As Figure 12 (a), Figure 12 (b) and shown in Figure 9, for example be P ^-(impurity concentration for example is 1 * 10 to the Semiconductor substrate 201 of type ¹⁴/ cm ³) surface portion in, for example be formed with that (impurity concentration for example is 2 * 10 for the reduction surface field zone 202 of N type ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, also being formed with in the mode adjacent with reducing surface field zone 202 in the surface portion of Semiconductor substrate 201 for example is that (impurity concentration for example is 1 * 10 for the base region 206 of P type ¹⁶/ cm ³, the degree of depth has 4 μ m).

In reducing surface field zone 202, be formed with that for example (impurity concentration for example is 2 * 10 for the flush type semiconductor layer 217 of P type ¹⁶/ cm ³).Flush type semiconductor layer 217 is that the surface with substrate 201 is a benchmark, and for example the degree of depth (Z of Figure 12 (a)) from about the 1 μ m forms along depth direction.The width of this flush type semiconductor layer 217 (W of Figure 12 (a)) for example has about 1 μ m.Though do not show in the accompanying drawings, this flush type semiconductor layer 217 is electrically connected with base region 206 via established part that reduces surface field zone 202 or the wiring etc. that is positioned at the upper strata.

In reducing surface field zone 202, being formed with in the mode of isolating with flush type semiconductor layer 217 for example is that (impurity concentration for example is 2 * 10 for the collector region 218 of P type ¹⁶/ cm ³).At this, collector region 218 has basically the impurity concentration identical with flush type semiconductor layer 217, is positioned at basically and flush type semiconductor layer 217 the same dark positions.In addition, in the surface portion that reduces surface field zone 202, being formed with in the mode that contacts with collector region 218 for example is P ⁺(impurity concentration for example is 1 * 10 to the collector contact area 219 of type ¹⁹/ cm ³, the degree of depth has 1 μ m).

In addition, in the surface portion that reduces surface field zone 202, being formed with in the mode with 217 isolation of flush type semiconductor layer for example is N ⁺(impurity concentration for example is 1 * 1020/cm in the drain region 216 of type ³, the degree of depth has 0.5 μ m).

At this, shown in Figure 12 (b), collector region 218 and drain region 216 are made of a plurality of parts of keeping apart respectively.With from collector region 218 towards emitter hold concurrently the vertical direction of the direction of source region 208 (below, also some place will this vertical direction be called vertical direction) on, be arranged alternately the various piece of collector region 218 and the various piece of drain region 216.The various piece of collector region 218 for example be about 60 μ m in the length on this vertical direction (length X shown in Figure 12 (b)); The various piece of drain region 216 for example be about 30 μ m in the length on this vertical direction (the length Y shown in Figure 12 (b)).

On Semiconductor substrate 201, be formed with collector electrode drain electrode 212 and the emitter source electrode 213 of holding concurrently of holding concurrently, this collector electrode drain electrode 212 of holding concurrently has run through interlayer film 211, all is electrically connected with collector contact area 219 (that is, the collector region 218) and drain region 216; This emitter source electrode 213 of holding concurrently has run through interlayer film 211, all is electrically connected with contact area 210 (that is, base region 206) and the emitter source region 208 of holding concurrently.

In the related semiconductor device of present embodiment, when hold concurrently at collector electrode drain electrode 212 and emitter hold concurrently apply between the source electrode 213 forward bias (below, also some place is called collector voltage with this forward bias), and when on gate electrode 207, applying positive voltage, electron stream (below, also some place is called collector current with this electron stream) 216 flow to the emitter source electrode 213 of holding concurrently from the drain region, this semiconductor device carries out MOSFET work thus.When flowing to the hold concurrently electron stream of source electrode 213 of emitter is that the size of collector current acquires a certain degree, when the potential difference in the current potential of collector region 218 and the reduction surface field zone 202 between the current potential of the part of encirclement collector region 218 reaches 0.6V approximately, the hole 218 is injected into and reduces surface field zone 202 from the collector region, and this semiconductor device is transferred to IGBT work from MOSFET work thus.

Like this, in the related semiconductor device of present embodiment, can hour make this semiconductor device carry out MOSFET work when the collector current that flows through element, make this semiconductor device carry out IGBT work after acquiring a certain degree in the size of the collector current that flows through element.In other words, can realize that basis flows through the semiconductor device that how much carries out MOSFET work or IGBT work of the collector current amount of element.In the related semiconductor device of described present embodiment because the impurity concentration of establishing collector region 218 is the low concentration roughly the same with the impurity concentration of flush type semiconductor layer 217, so with high impurity concentration layer (P ⁺Layer) situation (comparative example) that has formed the collector region is compared, and can will be injected into the amount that comprises the excess carrier in the Semiconductor substrate 201 that reduces surface field zone 202 and suppress manyly when IGBT works.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate 201.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

The semiconductor device of present embodiment (switch element) particularly is because be formed with flush type semiconductor layer 217 in the reduction surface field zone 202 in this semiconductor device, so can form depletion layer along both direction up and down from the flush type semiconductor layer.Therefore, (second embodiment) compares with the situation that has formed top semiconductor layer 205, can make the impurity concentration that reduces surface field zone 202 higher, thereby can seek the improvement of switching speed and the attenuating of conducting resistance.

Using high impurity concentration layer (P ⁺Type semiconductor layer) formed under the situation of collector region, need and reduce that the N type resilient coating that its impurity concentration is higher than reduction surface field zone being set between the surface field zone in the collector region, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the semiconductor device of present embodiment,,, operation can be simplified so do not need to be provided with N type resilient coating because formed collector region 218 with low impurity concentration.And, can avoid the generation of following situation, that is: as comparative example, because be provided with N type resilient coating, so more difficult from the work switching of IGBT work of MOSFET.

Remark additionally, explanation is the structure that has formed drain region 216 in the present embodiment, promptly switches to the structure of IGBT work from MOSFET work.But, as illustrating among first embodiment, in the structure that drain region 216 is not set, promptly constituted under the situation of transversal I GBT, also can access the effect the same with present embodiment, particularly, can access and to lower this effect of loss to load in the gamut till when very big from load when very little.

Below,, one of the manufacture method of the switch element of Figure 12 (a), 12 (b) and present embodiment shown in Figure 9 example is described to these profiles of Figure 18 with reference to Figure 13.

At first, in operation shown in Figure 13, preparing impurity concentration for example is 1 * 10 ¹⁴/ cm ³About P ^-N-type semiconductor N substrate 201.

Then, in operation shown in Figure 14, for example optionally forming by the next surface portion in Semiconductor substrate 201 of phosphonium ion injection for example is the reduction surface field zone 202 of N type.The impurity concentration that reduces surface field zone 202 for example is 2 * 10 ¹⁶/ cm ³About, the formation degree of depth that reduces surface field zone 202 for example is about 7 μ m.Afterwards, for example injecting the surface portion formation in Semiconductor substrate 201 by the boron ion for example is the base region 206 of P type.Base region 206 forms with to reduce surface field zone 202 adjacent.The impurity concentration of base region 206 for example is 1 * 10 ¹⁶/ cm ³About, the formation degree of depth of base region 206 for example is 4 μ m.In addition, for example wait to come on the surface that reduces surface field zone 202, optionally to form thickness and for example be the electric field dielectric film 204 of 500nm by wet oxidation.

Then, in operation shown in Figure 15, for example inject in reducing surface field zone 202 simultaneously by the high-energy boron ion and optionally formation for example be the flush type semiconductor layer 217 of P type and for example be the collector region 218 of P type.At this, flush type semiconductor layer 217 and collector region 218 are formed the state of keeping apart mutually.The impurity concentration of the impurity concentration of flush type semiconductor layer 217 and collector region 218 for example is respectively 2 * 10 ¹⁶/ cm ³About.Flush type semiconductor layer 217 and collector region 218 are to be benchmark with the surface of substrate 201 respectively, and for example the degree of depth (Z of Figure 12 (a)) from about the 1 μ m forms along depth direction.The width (W of Figure 12 (a)) of this flush type semiconductor layer 217 and this collector region 218 for example has about 1 μ m.At this moment, because inject, form flush type semiconductor layer 217, so the formation degree of depth of the formation depth ratio flush type semiconductor layer 217 of collector region 218 more greatly by carry out ion via electric field dielectric film 204.

Remark additionally, though do not show in the accompanying drawings, flush type semiconductor layer 217 forms with base region 206 and is electrically connected.

In the present embodiment, in order to form order that ion that each extrinsic region implements injects and unrestricted.

Then, in operation shown in Figure 16, for example form and cover the gate insulating film 203 of holding concurrently the part between source region 208 and the reduction surface field zone 202 at emitter described later in the base region 206 by thermal oxidation.Afterwards, on gate insulating film 203, optionally form the gate electrode 207 that for example constitutes by polysilicon.In addition, be mask with gate electrode 207 and the corrosion-resisting pattern that do not show, for example coming optionally to form in base region 206 with self-aligned by arsenic ion injection etc. for example is N ⁺The emitter of the type source region 208 of holding concurrently, optionally forming in reducing surface field zone 202 with self-aligned simultaneously for example is N ⁺The drain region 216 of type is (about drain region 216, with reference to Figure 12 (b) and Fig. 9).The emitter source region 208 of holding concurrently forms and reduces surface field zone 202 and isolate, and drain region 216 forms and flush type semiconductor layer 217 is isolated.The hold concurrently impurity concentration of source region 208 and drain region 216 of emitter for example is respectively 1 * 10 ²⁰/ cm ³About, the hold concurrently formation degree of depth of source region 208 and drain region 216 of emitter for example is respectively about 0.5 μ m.

Then, in operation shown in Figure 17, for example injecting next formation by the boron ion in base region 206 for example is P ⁺The contact area 210 of type.Contact area 210 forms and reduces surface field zone 202 and isolate.The impurity concentration of contact area 210 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of contact area 210 for example is 2 μ m.Afterwards, for example be infused in to form in the surface portion that reduces surface field zone 202 and for example be P by the boron ion ⁺ Collector contact area 219 type, that contact with collector region 218.The impurity concentration of collector contact area 219 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of collector contact area 219 for example is 1 μ m.

Then, in operation shown in Figure 180, for example utilize the atmospheric pressure cvd method comprise on the electric field dielectric film 204 and gate electrode 207 on Semiconductor substrate 201 on film 211 between cambium layer, then make the established part opening of interlayer film 211, on Semiconductor substrate 201, form collector electrode drain electrode 212 and the emitter source electrode 213 of holding concurrently of holding concurrently again respectively, hold concurrently drain electrode 212 of this collector electrode all is electrically connected with collector contact area 219 (that is, the collector region 218) and drain region 216; This emitter source electrode 213 and contact area 210 (that is, base region 206) and emitter source region 208 of holding concurrently of holding concurrently all is electrically connected.At last, after forming the diaphragm 214 that for example constitutes on the interlayer film 211, make the liner in the diaphragm 214 form regional opening by the plasma silicon nitride film.Like this, the switch element of Figure 12 (a), Figure 12 (b) and present embodiment shown in Figure 9 just forms and is over.

Manufacture method according to the present embodiment that describes previously, because form flush type semiconductor layer 217 and collector region 218 by same implanted dopant process, so form flush type semiconductor layer 217 and compare with separating with the situation of collector region 218, can make operation quantity still less, can reduce the cost.

(the 4th embodiment)

Below, with reference to accompanying drawing, the semiconductor device related to the fourth embodiment of the present invention particularly describes high-breakdown voltage semiconductor switching device.

Figure 19 represents the cross-section structure of the semiconductor device that the 4th embodiment is related.As shown in figure 19, for example be P ^-(impurity concentration for example is 1 * 10 to the Semiconductor substrate 201 of type ¹⁴/ cm ³) surface portion in, for example be formed with that (impurity concentration for example is 1 * 10 for the reduction surface field zone 202 of N type ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, also being formed with in the mode adjacent with reducing surface field zone 202 in the surface portion of Semiconductor substrate 201 for example is that (impurity concentration for example is 1 * 10 for the base region 206 of P type ¹⁶/ cm ³, the degree of depth has 4 μ m).

In base region 206, for example be P to be formed with the mode that reduces by 202 isolation of surface field zone ⁺(impurity concentration for example is 1 * 10 to the contact area 210 of type ¹⁹/ cm ³, the degree of depth has 2 μ m) and for example be N ⁺(impurity concentration for example is 1 * 10 to the emitter region 208 of type ²⁰/ cm ³, the degree of depth has 0.5 μ m).In addition, be formed with the first grid dielectric film 203 that covers the part between emitter region 208 and reduction surface field zone 202 in the base region 206, on first grid dielectric film 203, be formed with first grid electrode 207.

Remark additionally,, just can prevent first grid electrode 207 and emitter region 208 short circuits if first grid dielectric film 203 is formed on the emitter region 208.

Reducing on the surface field zone 202, be formed with the second grid dielectric film 220 that extends to from collector region 215 on the top semiconductor layer 205.In second grid dielectric film 220 on the part between collector region 215 and the top semiconductor layer 205, be formed with second grid electrode 221.Though do not show in the accompanying drawings, second grid electrode 221 is electrically connected with first grid electrode 207 with wiring or the wiring etc. that is positioned at the upper strata via gate electrode.

On the Semiconductor substrate 201 that is formed with above-mentioned each extrinsic region and gate electrode etc., be formed with interlayer film 211.

In the semiconductor device of present embodiment, between collector electrode 212 and emitter electrode 213, applied forward bias (make the current potential of collector electrode 212 1 sides higher), and applying on the first grid electrode 207 under the situation of positive voltage, when the current potential of collector region 215 and when reducing potential difference between the current potential of part of the encirclement collector region 215 in the surface field zone 202 and reaching 0.6V approximately, the hole 215 is injected into and reduces surface field zone 202 from the collector region, and this semiconductor device begins to carry out IGBT work.In other words, the semiconductor device of present embodiment (switch element) is transversal I GBT.

Semiconductor device (switch element) according to present embodiment, because (voltage as if emitter electrode 213 is 0V when switch element ends, just at the voltage of first grid electrode 207 and second grid electrode 221 all for example when 6V drops to 0V), the current potential in the part between collector region 215 and the top semiconductor layer 205 in the reduction surface field zone 202 (below, also some place is called collector potential with this current potential) raise, so the P channel mosfet conducting that utilizes the part of collector region 215 to form.Like this, just can be with 215 extracting out and residue in the excess carrier that reduce in the surface field zone 202 from the collector region through the path of described P channel mosfet, top semiconductor layer 205, base region 206 and contact area 210.And, can also extract out from top semiconductor layer 205 and residue in the excess carrier that reduce in the surface field zone 202.Therefore, can seek to shorten fall time (tf), in other words, can shorten to and extract the required time of charge carrier out and improve switching speed.Therefore, can seek the attenuating of switching losses.

Remark additionally, in the present embodiment, when by the time collector potential is raise extract out residue in the excess carrier (hole) that reduce in the surface field zone 202 after, depletion layer enlarges in reducing surface field zone 202 from top semiconductor layer 205, thereby can stop the hole current that flows through the described path that comprises described P channel mosfet from collector electrode 212.Therefore, the voltage endurance of element can not worsen.

According to the semiconductor device of present embodiment because the impurity concentration of establishing collector region 215 is the low concentration roughly the same with the impurity concentration of top semiconductor layer 205, so with high impurity concentration layer (P ⁺Layer) situation that has formed the collector region is compared, and can will be injected into the amount that comprises the excess carrier in the Semiconductor substrate 201 that reduces surface field zone 202 and suppress manyly when IGBT works.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate 201.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Forming with the high impurity concentration layer under the situation of collector region, need be in the collector region and reduce be provided with between the surface field zone its impurity concentration be higher than reduce the surface field zone, for example be the resilient coating of N type, to lower the hole injection efficiency that is injected into reduction surface field zone from the collector region.Relative therewith, in the semiconductor device of present embodiment,,, operation can be simplified so do not need to be provided with N type resilient coating because formed collector region 215 with low impurity concentration.

Remark additionally, explanation is the structure that does not form the drain region in the present embodiment, does not promptly switch to the structure of IGBT work from MOSFET work.But, as illustrating among second embodiment and the 3rd embodiment,, also can access the effect the same with present embodiment being provided with under the situation of drain region, particularly, can access and to lower this effect of loss to load in the gamut till when very big from load when very little.In this case, also can be such, collector region 215 and described drain region are made of a plurality of parts of keeping apart respectively, with 215 (in this case towards emitter region 208 from the collector region, be the emitter source region of holding concurrently) the vertical direction of direction on, be arranged alternately the various piece of collector region 215 and the various piece of described drain region.

Below,, one of the manufacture method of the switch element of present embodiment shown in Figure 19 example is described to these profiles of Figure 25 with reference to Figure 20.

At first, in operation shown in Figure 20, for example injecting in impurity concentration by phosphonium ion for example is 1 * 10 ¹⁴/ cm ³About P ^-Optionally forming in the surface portion of N-type semiconductor N substrate 201 for example is the reduction surface field zone 202 of N type.The impurity concentration that reduces surface field zone 202 for example is 1 * 10 ¹⁶/ cm ³About, the formation degree of depth that reduces surface field zone 202 for example is about 7 μ m.

Then, in operation shown in Figure 21, for example inject to form simultaneously and optionally and for example be the top semiconductor layer 205 of P type and for example be the collector region 215 of P type at the surface portion that reduces surface field zone 202 by the boron ion.At this, top semiconductor layer 205 and collector region 215 are formed the state of keeping apart mutually.The impurity concentration of the impurity concentration of top semiconductor layer 205 and collector region 215 for example is respectively 1 * 10 ¹⁶/ cm ³About.The formation degree of depth of top semiconductor layer 205 and collector region 215 for example is respectively about 1 μ m.

Then, in operation shown in Figure 22, for example injecting the surface portion formation in Semiconductor substrate 201 by the boron ion for example is the base region 206 of P type.Base region 206 forms with to reduce surface field zone 202 adjacent.The impurity concentration of base region 206 for example is 1 * 10 ¹⁶/ cm ³About, the formation degree of depth of base region 206 for example is 4 μ m.In addition, for example by wet oxidation wait come on the surface that reduces surface field zone 202, optionally to form from collector region 215 extend on the top semiconductor layer 205, thickness for example is the second grid dielectric film 220 of 500nm.At this moment, the diffusion of impurities of top semiconductor layer 205 makes the impurity concentration of top semiconductor layer 205 descend a bit.

Then, in operation shown in Figure 23, for example form the first grid dielectric film 203 that covers the part between emitter region 208 described later and reduction surface field zone 202 in the base region 206 by thermal oxidation.Afterwards, on first grid dielectric film 203, optionally form the first grid electrode 207 that for example constitutes by polysilicon.At this moment, the second grid electrode 221 that for example constitutes of formation optionally on the part between collector region 215 and the top semiconductor layer 205 in second grid dielectric film 220 when forming this first grid electrode 207 by polysilicon.In addition, as mask, for example coming optionally to form in base region 206 with self-aligned by arsenic ion injection etc. for example is N with first grid electrode 207 ⁺The emitter region 208 of type.Emitter region 208 forms and reduces by 202 isolation of surface field zone.The impurity concentration of emitter region 208 for example is 1 * 10 ²⁰/ cm ³About, the formation degree of depth of emitter region 208 for example is about 0.5 μ m.

Then, in operation shown in Figure 24, for example injecting next formation by the boron ion in base region 206 for example is P ⁺The contact area 210 of type.Contact area 210 forms and reduces surface field zone 202 and isolate.The impurity concentration of contact area 210 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of contact area 210 for example is 2 μ m.Afterwards, for example be infused in to form in the surface portion of collector region 215 and for example be P by the boron ion ⁺The collector contact area 209 of type.The impurity concentration of collector contact area 209 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of collector contact area 209 for example is 0.5 μ m.Remark additionally, also can omit and do not form collector contact area 209.

Then, in operation shown in Figure 25, for example utilize the atmospheric pressure cvd method at film 211 between cambium layer on the Semiconductor substrate 201 that is formed with described each extrinsic region and gate electrode etc., then make the established part opening of interlayer film 211, on Semiconductor substrate 201, form collector electrode 212 and emitter electrode 213 again, this collector electrode 212 is electrically connected with collector contact area 209 (that is, the collector region 215); This emitter electrode 213 all is electrically connected with contact area 210 (that is, base region 206) and emitter region 208.At last, after forming the diaphragm 214 that for example constitutes on the interlayer film 211, make the liner in the diaphragm 214 form regional opening by the plasma silicon nitride film.Switch element like this, shown in Figure 19, present embodiment just forms and is over.

(the 5th embodiment)

Below, with reference to accompanying drawing, the semiconductor device related to the fifth embodiment of the present invention particularly describes high-breakdown voltage semiconductor switching device.

Figure 26 represents the cross-section structure of the semiconductor device that the 5th embodiment is related.As shown in figure 26, for example be P ^-(impurity concentration for example is 1 * 10 to the Semiconductor substrate 201 of type ¹⁴/ cm ³) surface portion in, for example be formed with that (impurity concentration for example is 2 * 10 for the reduction surface field zone 202 of N type ¹⁶/ cm ³, the degree of depth has 7 μ m).In addition, also being formed with in the mode adjacent with reducing surface field zone 202 in the surface portion of Semiconductor substrate 201 for example is that (impurity concentration for example is 1 * 10 for the base region 206 of P type ¹⁶/ cm ³, the degree of depth has 4 μ m).

In the surface portion that reduces surface field zone 202, be formed with that for example (impurity concentration for example is 1 * 10 for the top semiconductor layer 222 of P type ¹⁶/ cm ³, the degree of depth has 1 μ m).

The downside of the top semiconductor layer 222 in reducing surface field zone 202, being formed with in the mode that contacts with top semiconductor layer 222 for example is that (impurity concentration for example is 2 * 10 for the flush type semiconductor layer 217 of P type ¹⁶/ cm ³).Flush type semiconductor layer 217 is that the surface with substrate 201 is a benchmark, and for example the degree of depth from about the 1 μ m forms along depth direction.The width of this flush type semiconductor layer 217 for example has about 1 μ m.Though do not show in the accompanying drawings, this flush type semiconductor layer 217 is electrically connected with base region 206 via established part that reduces surface field zone 202 or the wiring etc. that is positioned at the upper strata.In other words, top semiconductor layer 222 and base region 206 are electrically connected mutually via flush type semiconductor layer 217.

In the surface portion that reduces surface field zone 202, being formed with in the mode of isolating with top semiconductor layer 222 for example is that (impurity concentration for example is 1 * 10 for the collector region 215 of P type ¹⁶/ cm ³, the degree of depth has 1 μ m).At this, collector region 215 has basically the impurity concentration identical with top semiconductor layer 222, is positioned at basically and top semiconductor layer 222 the same dark positions.

Remark additionally, flush type semiconductor layer 217 be formed on reduce in the surface field zone 202 near collector region 215 near the part till the base region 206, and top semiconductor layer 222 only is formed near the collector region 215 that reduces in the surface field zone 202.With from collector region 215 on the vertical direction of the direction of base region 206, top semiconductor layer 222 is made of a plurality of parts of keeping apart mutually.This is to arrange in order to ensure the path that is used to extract out charge carrier described later.

Reducing on the surface field zone 202, be formed with the second grid dielectric film 220 that extends at least from the collector region 215 on the top semiconductor layer 222.In second grid dielectric film 220 on the part between collector region 215 and the top semiconductor layer 222, be formed with second grid electrode 221.Though do not show in the accompanying drawings, second grid electrode 221 is electrically connected with first grid electrode 207 with wiring or the wiring etc. that is positioned at the upper strata via gate electrode.

In the work of switch element that is the semiconductor device of present embodiment, the same with the 4th embodiment basically.In other words, between collector electrode 212 and emitter electrode 213, applied forward bias (make the current potential of collector electrode 212 1 sides higher), and applying on the first grid electrode 207 under the situation of positive voltage, when the current potential of collector region 215 and when reducing potential difference between the current potential of part of the encirclement collector region 215 in the surface field zone 202 and reaching 0.6V approximately, the hole 215 is injected into and reduces surface field zone 202 from the collector region, and this semiconductor device begins to carry out IGBT work.In other words, the semiconductor device of present embodiment (switch element) is transversal I GBT.

Semiconductor device (switch element) according to present embodiment, because (voltage as if emitter electrode 213 is 0V when switch element ends, just at the voltage of first grid electrode 207 and second grid electrode 221 all for example when 6V drops to 0V), the current potential in the part between collector region 215 and the top semiconductor layer 222 in the reduction surface field zone 202 (below, also some place is called collector potential with this current potential) raise, so the P channel mosfet conducting that utilizes the part of collector region 215 to form.Like this, just can be with 215 extracting out and residue in the excess carrier that reduce in the surface field zone 202 from the collector region through the path of described P channel mosfet, top semiconductor layer 222, flush type semiconductor layer 217, base region 206 and contact area 210.And, can also extract the excess carrier that residue in the reduction surface field zone 202 out from top semiconductor layer 222 and flush type semiconductor layer 217.Therefore, can seek to shorten fall time (tf), in other words, can shorten to and extract the required time of charge carrier out and improve switching speed.Therefore, can seek the attenuating of switching losses.

Remark additionally, in the present embodiment, when by the time collector potential is raise extract out residue in the excess carrier (hole) that reduce in the surface field zone 202 after, depletion layer enlarges in reducing surface field zone 202 from top semiconductor layer 222 and flush type semiconductor layer 217, thereby can stop the hole current that flows through the described path that comprises described P channel mosfet from collector electrode 212.Therefore, the voltage endurance of element can not worsen.

According to the semiconductor device of present embodiment because the impurity concentration of establishing collector region 215 is the low concentration roughly the same with the impurity concentration of top semiconductor layer 222, so with high impurity concentration layer (P ⁺Layer) situation that has formed the collector region is compared, and can will be injected into the amount that comprises the excess carrier in the Semiconductor substrate 201 that reduces surface field zone 202 and suppress manyly when IGBT works.Consequently, can lower the amount that when ending, residues in the excess carrier in the Semiconductor substrate 201.Therefore, can shorten to and extract the required time of charge carrier out, thereby can improve switching speed, thereby can seek the attenuating of switching losses.In other words, can realize can be at the high-voltage-resistant semiconductor device that lowers loss from load when very little to load in the gamut till when very big.

Semiconductor device according to present embodiment, because in reducing surface field zone 202, also be formed with flush type semiconductor layer 217, so can form depletion layer from both direction about flush type semiconductor layer 217 edges, thereby compare with the situation (the 4th embodiment) that in reducing surface field zone 202, has only formed top semiconductor layer 205, can make the impurity concentration that reduces surface field zone 202 higher, thereby can seek the improvement of switching speed and the attenuating of conducting resistance.

Below,, one of the manufacture method of the switch element of present embodiment shown in Figure 26 example is described to these profiles of Figure 32 with reference to Figure 27.

At first, in operation shown in Figure 27, for example injecting in impurity concentration by phosphonium ion for example is 1 * 10 ¹⁴/ cm ³About P ^-Optionally forming in the surface portion of N-type semiconductor N substrate 201 for example is the reduction surface field zone 202 of N type.The impurity concentration that reduces surface field zone 202 for example is 2 * 10 ¹⁶/ cm ³About, the formation degree of depth that reduces surface field zone 202 for example is about 7 μ m.

Then, in operation shown in Figure 28, for example inject to form simultaneously and optionally and for example be the top semiconductor layer 222 of P type and for example be the collector region 215 of P type at the surface portion that reduces surface field zone 202 by the boron ion.At this, top semiconductor layer 222 and collector region 215 are formed the state of keeping apart mutually.The impurity concentration of the impurity concentration of top semiconductor layer 222 and collector region 215 for example is respectively 1 * 10 ¹⁶/ cm ³About.The formation degree of depth of top semiconductor layer 222 and collector region 215 for example is respectively about 1 μ m.

Then, in operation shown in Figure 29, for example injecting the surface portion formation in Semiconductor substrate 201 by the boron ion for example is the base region 206 of P type.Base region 206 forms with to reduce surface field zone 202 adjacent.The impurity concentration of base region 206 for example is 1 * 10 ¹⁶/ cm ³About, the formation degree of depth of base region 206 for example is 4 μ m.In addition, for example by wet oxidation wait come on the surface that reduces surface field zone 202, optionally to form from collector region 215 extend on the top semiconductor layer 222 at least, thickness for example is the second grid dielectric film 220 of 500nm.At this moment, the diffusion of impurities of top semiconductor layer 222 makes the impurity concentration of top semiconductor layer 222 descend a bit.

Afterwards, for example injecting by the high-energy boron ion that downside with mode the top semiconductor layer 222 during reducing surface field zone 202 adjacent with top semiconductor layer 222 optionally forms for example is the flush type semiconductor layer 217 of P type.The impurity concentration of flush type semiconductor layer 217 for example is 2 * 10 ¹⁶/ cm ³About.Flush type semiconductor layer 217 is that the surface with substrate 201 is a benchmark, and for example the degree of depth from about the 1 μ m forms along depth direction.The width of this flush type semiconductor layer 217 for example has about 1 μ m.Remark additionally, though do not show in the accompanying drawings, flush type semiconductor layer 217 forms with base region 206 described later and is electrically connected.

Then, in operation shown in Figure 30, for example form the first grid dielectric film 203 that covers the part between emitter region 208 described later and reduction surface field zone 202 in the base region 206 by thermal oxidation.Afterwards, on first grid dielectric film 203, optionally form the first grid electrode 207 that for example constitutes by polysilicon.At this moment, the second grid electrode 221 that for example constitutes of formation optionally on the part between collector region 215 and the top semiconductor layer 222 in second grid dielectric film 220 when forming this first grid electrode 207 by polysilicon.In addition, as mask, for example waiting next optionally formation with self-aligned by the arsenic ion injection in base region 206 for example is N with first grid electrode 207 ⁺The emitter region 208 of type.Emitter region 208 forms and reduces by 202 isolation of surface field zone.The impurity concentration of emitter region 208 for example is 1 * 10 ²⁰/ cm ³About, the formation degree of depth of emitter region 208 for example is about 0.5 μ m.

Then, in operation shown in Figure 31, for example injecting next formation by the boron ion in base region 206 for example is P ⁺The contact area 210 of type.Contact area 210 forms and reduces surface field zone 202 and isolate.The impurity concentration of contact area 210 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of contact area 210 for example is 2 μ m.Afterwards, for example injecting in the collector region 215 surface portion to form by the boron ion for example is P ⁺The collector contact area 209 of type.The impurity concentration of collector contact area 209 for example is 1 * 10 ¹⁹/ cm ³About, the formation degree of depth of collector contact area 209 for example is 0.5 μ m.Remark additionally, also can omit and do not form collector contact area 209.

Then, in operation shown in Figure 32, for example utilize the atmospheric pressure cvd method at film 211 between cambium layer on the Semiconductor substrate 201 that is formed with described each extrinsic region and gate electrode etc., then make the established part opening of interlayer film 211, on Semiconductor substrate 201, form collector electrode 212 and emitter electrode 213 again, this collector electrode 212 is electrically connected with collector contact area 209 (that is, the collector region 215); This emitter electrode 213 all is electrically connected with contact area 210 (that is, base region 206) and emitter region 208.At last, after forming the diaphragm 214 that for example constitutes on the interlayer film 211, make the liner in the diaphragm 214 form regional opening by the plasma silicon nitride film.Switch element like this, shown in Figure 26, present embodiment just forms and is over.

Manufacture method according to the present embodiment that describes previously, because form top semiconductor layer 222 and collector region 215 by same implanted dopant process, so form top semiconductor layer 222 and compare with separating with the situation of collector region 215, can make operation quantity still less, can reduce the cost.

-industrial applicibility-

The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly the present invention is being used for In the situation of the high-breakdown voltage semiconductor switching device that in switching power unit, uses, can be by lowering Residue in the excess carriers amount in the Semiconductor substrate during cut-off, it is required to shorten to the extraction carrier Time, can improve this effect of switching speed thereby can access, very useful.

Claims

1. semiconductor device is characterized in that:

Comprise:

Second conductivity type reduces the surface field zone, is formed in the surface portion of the first conductive-type semiconductor substrate,

The first conductivity type base region is formed in the described Semiconductor substrate in the mode adjacent with described reduction surface field zone,

The second conductivity type emitter region is formed in the described base region in the mode with described reduction surface field zone isolation,

The first grid dielectric film forms the part between described emitter region and described reduction surface field zone that covers in the described base region,

The first grid electrode is formed on the described first grid dielectric film,

The first conductivity type top semiconductor layer is formed in the surface portion in described reduction surface field zone, and is electrically connected with described base region,

The first conductive collector zone, be formed in the surface portion in described reduction surface field zone in mode with described top semiconductor layer isolation, and have identical with described top semiconductor layer basically impurity concentration, be positioned at the same with described top semiconductor layer basically dark position

Collector electrode is formed on the described Semiconductor substrate, and is electrically connected with described collector region, and

Emitter electrode is formed on the described Semiconductor substrate, and is electrically connected with described base region and described emitter region.

2. semiconductor device is characterized in that:

Comprise:

The second conductivity type emitter source region of holding concurrently is formed in the described base region in the mode with described reduction surface field zone isolation,

The first grid dielectric film, form cover in the described base region in hold concurrently part between source region and the described reduction surface field zone of described emitter,

The first grid electrode is formed on the described first grid dielectric film,

The second conductivity type drain region is formed in the surface portion in described reduction surface field zone in the mode with described top semiconductor layer isolation,

The collector electrode drain electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described collector region and described drain region respectively, and

The emitter source electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described base region and the described emitter source region of holding concurrently respectively.

3. semiconductor device according to claim 2 is characterized in that:

Described collector region and described drain region are made of a plurality of parts of keeping apart respectively;

With from described collector region on described emitter is held concurrently the vertical direction of the direction of source region, be arranged alternately the various piece of described collector region and the various piece of described drain region.

4. according to each the described semiconductor device in the claim 1 to 3, it is characterized in that:

Also comprise:

The second grid dielectric film is formed on the described reduction surface field zone, extend to from described collector region on the described top semiconductor layer and

The second grid electrode is formed on the described second grid dielectric film.

5. semiconductor device according to claim 4 is characterized in that:

Also comprise the first conductivity type flush type semiconductor layer, be formed in the described reduction surface field zone, and be electrically connected with described base region in the mode that contacts with described top semiconductor layer.

6. the manufacture method of a semiconductor device, the manufacture method of this semiconductor device are in order to making each described semiconductor device in the claim 1 to 3, it is characterized in that:

At least comprise the operation that forms described top semiconductor layer and described collector region by same implanted dopant process.

7. semiconductor device is characterized in that:

Comprise:

Gate insulating film forms the part between described emitter region and described reduction surface field zone that covers in the described base region,

Gate electrode is formed on the described gate insulating film,

The first conductivity type flush type semiconductor layer is formed in the described reduction surface field zone, and is electrically connected with described base region,

The first conductive collector zone, be formed in the described reduction surface field zone in mode with described flush type semiconductor layer isolation, and have basically and the identical impurity concentration of described flush type semiconductor layer, be positioned at the same with described flush type semiconductor layer basically dark position

The first conductive collector contact area is formed in the mode that contacts with described collector region in the surface portion in described reduction surface field zone,

Collector electrode is formed on the described Semiconductor substrate, and is electrically connected with described collector contact area, and

8. semiconductor device is characterized in that:

Comprise:

Gate insulating film, form cover in the described base region in hold concurrently part between source region and the described reduction surface field zone of described emitter,

Gate electrode is formed on the described gate insulating film,

The second conductivity type drain region is formed in the surface portion in described reduction surface field zone in the mode with described flush type semiconductor layer isolation,

The collector electrode drain electrode of holding concurrently is formed on the described Semiconductor substrate, and is electrically connected with described collector contact area and described drain region respectively, and

9. semiconductor device according to claim 8 is characterized in that:

10. the manufacture method of a semiconductor device, the manufacture method of this semiconductor device are in order to making each described semiconductor device in the claim 7 to 9, it is characterized in that:

At least comprise the operation that forms described flush type semiconductor layer and described collector region by same implanted dopant process.