CN219286406U - High electrostatic protection split gate MOSFET device - Google Patents
High electrostatic protection split gate MOSFET device Download PDFInfo
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- CN219286406U CN219286406U CN202320816126.0U CN202320816126U CN219286406U CN 219286406 U CN219286406 U CN 219286406U CN 202320816126 U CN202320816126 U CN 202320816126U CN 219286406 U CN219286406 U CN 219286406U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model provides a split gate MOSFET device with high electrostatic protection capability, which comprises: a heavily doped first conductivity type silicon substrate, on which a first conductivity type epitaxial layer is provided; the surface of the first conductive type epitaxial layer, which faces away from the silicon substrate, is a first main surface, and the surface of the silicon substrate, which faces away from the first conductive type epitaxial layer, is a second main surface; a first type trench is arranged in the first conductive type epitaxial layer; the inner wall in the first type groove is respectively provided with a thick oxide layer and a grid oxide layer from bottom to top; the thickness of the thick oxide layer is larger than that of the gate oxide layer; at least one group of back-to-back polysilicon diode structures are arranged in the first type of grooves; the utility model can improve the antistatic capability of the device.
Description
Technical Field
The utility model relates to a MOSFET power semiconductor device, in particular to a split gate MOSFET device with high electrostatic protection capability.
Background
The power MOSFET device is an electronic device capable of realizing high-speed switching, plays an important role in the power conversion process, and has higher requirements on the power MOSFET device along with the continuous improvement of the requirements of people on the power conversion efficiency and the efficiency.
The power consumption of a power MOSFET device is composed of two parts, switching loss and conduction loss, the conduction loss is mainly limited by the on-resistance of the MOSFET device, and the switching damage is mainly limited by the gate charge of the MOSFET device. In order to continuously reduce the loss of the device and improve the power density, a split gate MOSFET device is generated, the split gate MOSFET device is a high-performance device which is derived on the basis of a common trench MOS device, the device can reduce the capacitance (Cgd) of a gate electrode and a drain electrode to a great extent, the on-resistance of a unit area can be reduced, and generally, two split electrodes are isolated through an oxide medium.
The grid electrode and the source electrode of the MOSFET device are separated by only a thin oxide layer, the oxide layer is generally within 100nm, when the MOSFET device is not protected by a special structure, the ESD resistance is very low, and in a relatively dry environment, the ESD resistance is far lower than the static value generated by a common human body, and the permanent damage of the device is very easy to cause.
Disclosure of Invention
Aiming at the defects existing in the prior art, the embodiment of the utility model provides a split gate MOSFET device with high electrostatic protection capability, and an electrostatic discharge channel between a gate and a source is increased, so that the antistatic capability of the device is improved. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the utility model is as follows:
the embodiment of the utility model provides a split gate MOSFET device with high electrostatic protection capability, which comprises the following components:
a heavily doped first conductivity type silicon substrate, on which a first conductivity type epitaxial layer is provided; the surface of the first conductive type epitaxial layer, which faces away from the silicon substrate, is a first main surface, and the surface of the silicon substrate, which faces away from the first conductive type epitaxial layer, is a second main surface;
a first type trench is arranged in the first conductive type epitaxial layer; the inner wall in the first type groove is respectively provided with a thick oxide layer and a grid oxide layer from bottom to top; the thickness of the thick oxide layer is larger than that of the gate oxide layer; at least one group of back-to-back polysilicon diode structures are arranged in the first type of grooves;
forming a second conductivity type well region and a heavily doped first conductivity type injection region which are distributed from bottom to top on the top of the first conductivity type epitaxial layer;
a gate oxide layer and an insulating medium layer are arranged on the first main surface; the insulating medium layer fills the top of the first type groove; a source electrode metal and a grid electrode metal are arranged on the insulating medium layer; the source metal is connected with the polysilicon of the lower end electrode of the back-to-back polysilicon diode structure in the first type groove through a source contact hole; the grid metal is connected with the upper end electrode polysilicon of the back-to-back polysilicon diode structure in the first type of groove through the grid contact hole; the source metal is also connected with the second conductive type well region through the injection layer contact hole;
a drain metal is provided on the second main surface.
Specifically, the set of back-to-back polysilicon diode structures is a first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structure.
Further, the thick oxide layer has a thickness of 2000 to 8000 a.
Further, the thickness of the gate oxide layer is 500-1000 a.
Further, two groups of back-to-back polysilicon diode structures are arranged in the first type of grooves; the two groups of back-to-back polysilicon diode structures are first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structures.
The technical scheme provided by the embodiment of the utility model has the beneficial effects that:
1) And an electrostatic discharge channel is added between the grid electrode and the source electrode of the MOSFET device, so that the antistatic capability of the MOSFET device is improved.
2) Compared with the prior split gate MOSFET device, the gate-source isolation method has the advantages that the gate-source isolation is realized through the oxide layer, and the manufacturing difficulty and the manufacturing cost are reduced.
Drawings
Fig. 1 is a schematic diagram of a typical split gate MOSFET device structure.
Fig. 2 is a schematic diagram of a split gate MOSFET device according to a first embodiment of the utility model.
Fig. 3 is a schematic diagram of a split gate MOSFET device according to a first embodiment of the utility model.
Fig. 4 is a schematic diagram of a split gate MOSFET device according to a second embodiment of the present utility model.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
In the embodiment of the utility model, taking an N-type MOSFET device as an example, the first conduction type is N-type, and the second conduction type is P-type;
as shown in fig. 1, a split gate MOSFET device, comprising:
a heavily doped first conductivity type silicon substrate 1, on which a first conductivity type epitaxial layer 2 is provided on the silicon substrate 1; the surface of the first conductive type epitaxial layer 2 facing away from the silicon substrate 1 is a first main surface, and the surface of the silicon substrate 1 facing away from the first conductive type epitaxial layer 2 is a second main surface;
a first type trench 201 is provided in the first conductivity type epitaxial layer 2; a thick oxide layer 3 and a gate oxide layer 4 are respectively arranged on the inner wall in the first type groove 201 from bottom to top; the thickness of the thick oxide layer 3 is larger than that of the gate oxide layer 4; a first type conductive polysilicon 5 and a second type conductive polysilicon 6 are arranged in the first type trench 201; the second type of conductive polysilicon 6 is positioned above the first type of conductive polysilicon 5, and an isolation oxide layer 7 is arranged between the second type of conductive polysilicon and the first type of conductive polysilicon;
forming a second conductivity type well region 8 and a heavily doped first conductivity type injection region 9 distributed from bottom to top on top of the first conductivity type epitaxial layer 2;
a gate oxide layer 4 and an insulating dielectric layer 10 are provided on the first main surface; the insulating dielectric layer 10 fills the top of the first type trench 201; source metal and gate metal are arranged on the insulating medium layer 10; the source metal is connected with the first type conductive polysilicon 5 in the first type trench 201 through a source contact hole; the gate metal is connected with the second type conductive polysilicon 6 in the first type trench 201 through a gate contact hole; the source metal is also connected with the second conductive type well region 8 through the injection layer contact hole 11;
a drain metal 13 is provided on the second main surface;
the first type of conductive polysilicon 5 is used as source polysilicon, and the second type of conductive polysilicon 6 is used as gate polysilicon;
note that in fig. 1, the source metal, the gate metal, the source contact hole, and the gate metal contact hole are not separately shown; in fig. 1, a metal 12 is shown deposited on an insulating dielectric layer 10 on a first main surface, said metal 12 being further etched to produce a source metal and a gate metal; the source contact, gate contact and implant contact 11 may be made prior to depositing the metal 12.
First embodiment, the present embodiment is modified based on the split gate MOSFET device described above, as shown in fig. 2;
an embodiment of the present utility model provides a split gate MOSFET device with high electrostatic protection capability, including:
a heavily doped first conductivity type silicon substrate 1, on which a first conductivity type epitaxial layer 2 is provided on the silicon substrate 1; the surface of the first conductive type epitaxial layer 2 facing away from the silicon substrate 1 is a first main surface, and the surface of the silicon substrate 1 facing away from the first conductive type epitaxial layer 2 is a second main surface;
a first type trench 201 is provided in the first conductivity type epitaxial layer 2; a thick oxide layer 3 and a gate oxide layer 4 are respectively arranged on the inner wall in the first type groove 201 from bottom to top; the thickness of the thick oxide layer 3 is larger than that of the gate oxide layer 4; a set of back-to-back polysilicon diode structures 14 are provided in the first type trenches 201;
forming a second conductivity type well region 8 and a heavily doped first conductivity type injection region 9 distributed from bottom to top on top of the first conductivity type epitaxial layer 2;
a gate oxide layer 4 and an insulating dielectric layer 10 are provided on the first main surface; the insulating dielectric layer 10 fills the top of the first type trench 201; source metal and gate metal are arranged on the insulating medium layer 10; the source metal is connected with the polysilicon of the lower end electrode of the back-to-back polysilicon diode structure 14 in the first type trench 201 through a source contact hole; the gate metal is connected with the upper end electrode polysilicon of the back-to-back polysilicon diode structure 14 in the first type trench 201 through a gate contact hole; the source metal is also connected with the second conductive type well region 8 through the injection layer contact hole 11;
a drain metal 13 is provided on the second main surface;
note that in fig. 2, the source metal, the gate metal, the source contact hole, and the gate metal contact hole are not shown separately; in fig. 2, a metal 12 is shown deposited on the insulating dielectric layer 10 of the first main surface, said metal 12 further being etched to produce a source metal and a gate metal; source contact holes, gate contact holes and implant layer contact holes 11 may be made prior to depositing metal 12;
specifically, the set of back-to-back polysilicon diode structures 14 is a first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structure.
In the embodiment shown in fig. 2, the set of back-to-back polysilicon diode structures 14 is of an N-P-N type structure, with the first conductivity type polysilicon at the upper end serving as both the gate polysilicon of the MOSFET device and one of the first conductivity type electrode polysilicon of the back-to-back polysilicon diode structures, and the first conductivity type polysilicon at the lower end serving as both the source polysilicon of the MOSFET device and the other of the first conductivity type electrode polysilicon of the back-to-back polysilicon diode structures.
Referring to fig. 3, in the split gate MOSFET device with high electrostatic protection capability according to the first embodiment of the present utility model, a back-to-back polysilicon diode is added between the gate and the source of the MOSFET device, and the back-to-back diode not only ensures isolation of the gate and the source, but also increases the electrostatic discharge channel between the gate and the source, thereby improving the antistatic capability of the device.
Specifically, the thickness of the thick oxide layer 3 is 2000-8000A; the withstand voltage of the device can be remarkably improved.
Specifically, the thickness of the gate oxide layer 4 is 500-1000 a; the gate oxide layer may serve as an insulator.
In the embodiment of the utility model, the electrostatic discharge channel is arranged in the deep groove, namely the first groove 201, so that the photoetching times are not required to be increased during manufacturing, meanwhile, the area of an active region of a device is not occupied, and the gate polysilicon and the source polysilicon are not isolated by a specially manufactured oxide layer, so that the manufacturing difficulty and the manufacturing cost are reduced.
In the second embodiment, as shown in fig. 4;
in contrast to the first embodiment, in the second embodiment, two sets of back-to-back polysilicon diode structures 14 are provided in the first type trenches 201; the two sets of back-to-back polysilicon diode structures 14 are first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structures;
the rest is the same as the first embodiment.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same, and although the present utility model has been described in detail with reference to the examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present utility model without departing from the spirit and scope of the technical solution of the present utility model, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present utility model.
Claims (5)
1. A high electrostatic protection split gate MOSFET device comprising:
a heavily doped first conductivity type silicon substrate (1), on which silicon substrate (1) a first conductivity type epitaxial layer (2) is provided; the surface of the first conductive type epitaxial layer (2) facing away from the silicon substrate (1) is a first main surface, and the surface of the silicon substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface;
a first type trench (201) is provided in the first conductivity type epitaxial layer (2); the inner wall in the first groove (201) is respectively provided with a thick oxide layer (3) and a grid oxide layer (4) from bottom to top; the thickness of the thick oxide layer (3) is larger than that of the grid oxide layer (4); at least one set of back-to-back polysilicon diode structures (14) are provided in the first type of trench (201);
forming a second conductivity type well region (8) and a heavily doped first conductivity type injection region (9) which are distributed from bottom to top on the top of the first conductivity type epitaxial layer (2);
a gate oxide layer (4) and an insulating dielectric layer (10) are arranged on the first main surface; the insulating medium layer (10) fills the top of the first type groove (201); a source metal and a grid metal are arranged on the insulating medium layer (10); the source metal is connected with the lower end electrode polysilicon of the back-to-back polysilicon diode structure (14) in the first type groove (201) through a source contact hole; the grid metal is connected with the upper end electrode polysilicon of the back-to-back polysilicon diode structure (14) in the first type groove (201) through a grid contact hole; the source metal is also connected with the second conduction type well region (8) through the injection layer contact hole (11);
a drain metal (13) is provided on the second main surface.
2. The high electrostatic protection split gate MOSFET device of claim 1,
the set of back-to-back polysilicon diode structures (14) are first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structures.
3. The high electrostatic protection split gate MOSFET device of claim 1,
the thickness of the thick oxide layer (3) is 2000-8000A.
4. The high electrostatic protection split gate MOSFET device of claim 1,
the thickness of the gate oxide layer (4) is 500-1000A.
5. The high electrostatic protection split gate MOSFET device of claim 1,
two groups of back-to-back polysilicon diode structures (14) are arranged in the first type of grooves (201); the two sets of back-to-back polysilicon diode structures (14) are first conductivity type polysilicon-second conductivity type polysilicon-first conductivity type polysilicon structures.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320816126.0U CN219286406U (en) | 2023-04-13 | 2023-04-13 | High electrostatic protection split gate MOSFET device |
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| CN202320816126.0U CN219286406U (en) | 2023-04-13 | 2023-04-13 | High electrostatic protection split gate MOSFET device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116825850A (en) * | 2023-08-25 | 2023-09-29 | 江苏应能微电子股份有限公司 | Isolated gate trench MOS device integrated with ESD protection device and process |
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- 2023-04-13 CN CN202320816126.0U patent/CN219286406U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116825850A (en) * | 2023-08-25 | 2023-09-29 | 江苏应能微电子股份有限公司 | Isolated gate trench MOS device integrated with ESD protection device and process |
| CN116825850B (en) * | 2023-08-25 | 2023-11-17 | 江苏应能微电子股份有限公司 | Isolated gate trench MOS device integrated with ESD protection device and process |
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