CN105336779B - LDMOS device and forming method thereof - Google Patents
LDMOS device and forming method thereof Download PDFInfo
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- CN105336779B CN105336779B CN201410381705.2A CN201410381705A CN105336779B CN 105336779 B CN105336779 B CN 105336779B CN 201410381705 A CN201410381705 A CN 201410381705A CN 105336779 B CN105336779 B CN 105336779B
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Abstract
A kind of LDMOS device and forming method thereof, the LDMOS device include：Silicon substrate in insulation, the second substrate including buried layer, on buried layer；Ldmos transistor on second substrate, including：The depth in the well region in the second substrate, source region and drain region in well region, source region and drain region is less than the depth of well region, and the doping type in source region and drain region is opposite with the doping type of well region；The first doped region in the well region in source region bottom, first doped region are identical with the doping type of well region；Through the first through hole of the buried layer, the first doped region, well region and source region；Form the first metal plug of the full first through hole of filling.The LDMOS device of the present invention overcomes the influence of floater effect.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of LDMOS device and forming method thereof.
Background technology
Power field effect pipe mainly includes vertical bilateral diffusion field-effect pipe (VDMOS, Vertical Double-Diffused
) and horizontal dual pervasion field effect pipe (LDMOS, Lateral Double-Diffused MOSFET) two types MOSFET.Its
In, compared to vertical bilateral diffusion field-effect pipe (VDMOS), horizontal dual pervasion field effect pipe (LDMOS) has many advantages, such as, example
Such as, the latter has better thermal stability and frequency stability, higher gain and durability, lower feedback capacity and heat
Resistance and constant input impedance and simpler biasing circuit.
Silicon-on-insulator (SOI, Silicon On Insulator) substrate is a kind of substrate for IC manufacturing.
Compared with the body silicon substrate widely applied at present, SOI substrate has many advantages：Using integrated circuit made of SOI substrate
Parasitic capacitance is small, integration density is high, short-channel effect is small, speed is fast, and can also realize Jie of component in integrated circuit
Matter is isolated, and completely eliminates the parasitic latch-up in body silicon integrated circuit.
With reference to figure 1, Fig. 1 is the structure diagram of the ldmos transistor of N-type formed using silicon-on-insulator substrate, institute
Ldmos transistor is stated to include：Silicon-on-insulator substrate 100, the silicon-on-insulator substrate 100 include the first substrate 11, are located at
Buried layer 13 on first substrate 11, the second substrate 12 on buried layer 13；P type trap zone in the second substrate 12
(not shown)；N-type drift region 101 in P type trap zone；Fleet plough groove isolation structure in N-type drift region 101
104, the fleet plough groove isolation structure 104 is used to increase the path of horizontal dual pervasion field effect pipe conducting, expands so that increase is laterally double
Dissipate the breakdown voltage of field-effect tube；Positioned at the P type trap zone NeiPXing Ti areas 106 of 101 side of N-type drift region；It is served as a contrast positioned at semiconductor
Gate structure 105 on bottom, the gate structure 105 is across the PXing Ti areas 106 and N-type drift region 101, and part is located at
On fleet plough groove isolation structure 104, the gate structure 105 includes the gate dielectric layer being located on the second substrate 12, positioned at gate medium
Gate electrode on layer, the side wall on gate dielectric layer and gate electrode both sides side wall；P-type body positioned at 105 side of gate structure
Source region 102 in area 106 and the drain region 103 in the N-type drift region 101 of the opposite side of gate structure 105,102 He of source region
The doping type in drain region 103 is N-type.
The ldmos transistor performance that existing silicon-on-insulator substrate is formed is still to be improved.
Invention content
The present invention solves the problems, such as it is how to prevent floater effect to the ldmos transistor that is formed in silicon-on-insulator substrate
Performance influence.
To solve the above problems, the present invention provides a kind of forming method of LDMOS device, including：There is provided insulation upper silicon lining
Bottom, the silicon-on-insulator substrate include the first substrate, the second substrate and the burial between the first substrate and the second substrate
Layer；Ldmos transistor is formed on second substrate, the ldmos transistor includes：Well region in the second substrate,
The depth in source region and drain region in well region, source region and drain region is less than the depth of well region, the doping type in source region and drain region with
The doping type of well region is opposite；First substrate is removed, exposes the backside surface of buried layer；It is right from the back side of buried layer
The well region of source region bottom carries out ion implanting, forms the first doped region in the well region of source region bottom, first doped region with
The doping type of well region is identical；Form the first through hole through the buried layer, the first doped region, well region and source region；It is formed
First metal plug of the full first through hole of filling.
Optionally, the doping type of the well region and the first doped region be p-type, the doping class of drift region, source region and drain region
Type is N-type.
Optionally, the doping type of the well region and the first doped region be N-type, the doping class of drift region, source region and drain region
Type is p-type.
Optionally, the width of first through hole is less than the width of source region and the first doped region.
Optionally, the front face of first doped region and buried layer.
Optionally, the depth of the ion implanting injection is less than the thickness of the second substrate.
Optionally, the injection depth of the ion implanting is 0~0.3 micron, and dosage is 1E14~1E16atom/cm2, angle
Spend is 0~10 degree.
Optionally, after carrying out ion implanting, annealing process is carried out.
Optionally, first metal plug includes：Diffusion impervious layer positioned at first through hole side wall and bottom, positioned at expansion
Dissipate the metal layer of the full through-hole of barrier layer surface filling.
Optionally, it further includes：While forming first through hole, buried layer described in through part, drift region and drain region
Second through-hole.
Optionally, the second metal plug of full second through-hole of filling is formed；It is formed and covers the ldmos transistor and second
The first medium layer of substrate surface；The first metal layer is formed on the first medium layer；It is formed through the buried layer, second
First silicon hole of substrate, first medium layer, the bottom-exposed of first silicon hole go out the bottom surface of the first metal layer；
Metal is filled in first silicon hole and forms the first silicon through hole interconnection structure；The second metal is formed in the back surfaces of buried layer
First metal plug and the first silicon through hole interconnection structure are electrically connected by layer, the second metal layer.
Optionally, it further includes：The ldmos transistor includes：Well region in the second substrate；Grid on well region
Pole structure；Drift region in the well region of gate structure side, the doping type of the drift region and the doping type of well region
On the contrary；Drain region in drift region, the depth in drain region are less than the depth of drift region, the doping type in drain region and mixing for drift region
Miscellany type is identical；Source region in the well region of gate structure opposite side, the depth of source region are less than the depth of well region, and source region is mixed
Miscellany type is opposite with the doping type of well region.
The embodiment of the present invention also provides a kind of LDMOS device, including：Silicon substrate in insulation, the silicon-on-insulator substrate
The second substrate including buried layer, on buried layer；Ldmos transistor on second substrate, the LDMOS are brilliant
Body pipe includes：Well region in the second substrate；Gate structure on well region；In the well region of gate structure side
Drift region, the doping type of the drift region are opposite with the doping type of well region；Drain region in drift region, the depth in drain region
Less than the depth of drift region, the doping type in drain region is identical with the doping type of drift region；Positioned at the trap of gate structure opposite side
Source region in area, the depth of source region are less than the depth of well region, and the doping type of source region is opposite with the doping type of well region；Positioned at
The first doped region in the well region of source region bottom, first doped region are identical with the doping type of well region；Through the burial
The first through hole of layer, the first doped region, well region and source region；Form the first metal plug of the full first through hole of filling.
Optionally, the doping type of the well region and the first doped region be p-type, the doping class of drift region, source region and drain region
Type is N-type.
Optionally, the doping type of the well region and the first doped region be N-type, the doping class of drift region, source region and drain region
Type is p-type.
Optionally, the width of first through hole is less than the width of source region and the first doped region.
Optionally, first doped region is contacted with the surface of buried layer.
Optionally, first metal plug includes：Diffusion impervious layer positioned at first through hole side wall and bottom, positioned at expansion
Dissipate the metal layer of the full through-hole of barrier layer surface filling.
Optionally, it further includes：Buried layer, drift region and second through-hole in drain region described in through part；Filling full second
Second metal plug of through-hole；Through the buried layer, the second substrate, first medium layer the first silicon hole, first silicon
The bottom-exposed of through-hole goes out the bottom surface of the first metal layer；First silicon through hole interconnection structure of full first silicon hole of filling；Position
Second metal layer in the back surfaces of buried layer, the second metal layer is by the first metal plug and the first interconnecting silicon through holes
Structure is electrically connected.
Optionally, the ldmos transistor includes：Well region in the second substrate；Gate structure on well region；
Drift region in the well region of gate structure side, the doping type of the drift region are opposite with the doping type of well region；Position
In the drain region in drift region, the depth in drain region is less than the depth of drift region, the doping type in drain region and the doping type of drift region
It is identical；Source region in the well region of gate structure opposite side, the depth of source region are less than the depth of well region, the doping type of source region
It is opposite with the doping type of well region.
Compared with prior art, technical scheme of the present invention has the following advantages：
The forming method of the LDMOS device of the present invention, after forming ldmos transistor in the second substrate, removal described the
One substrate exposes the backside surface of buried layer；From the back side of buried layer, ion implanting is carried out to the well region of source region bottom,
The first doped region is formed in the well region of source region bottom, first doped region is identical with the doping type of well region；It is formed through institute
State the first through hole of buried layer, the first doped region, well region and source region；The first metal plug of the full first through hole of filling is formed,
Can be will be close to by the first doped region and the first metal plug the aggregation in the buried layer of source region hot carrier (N-type
Ldmos transistor aggregation be hole, p-type LSMOS transistors aggregation be electronics) export, prevent hot carrier (hole or
Electronics) aggregation in the buried layer by source area, improve the performance of LDMOS device；
In addition, the doping type of the first doped region formed is identical with the doping type of well region, this is brilliant with the LMDOS of formation
The type of body pipe is relevant, and when LMDOS transistors are N-type, the carrier assembled by the buried layer of source area is hole, N-type
LMDOS transistors well region for p-type, thus the type of corresponding first doped region 210 is also p-type, the first doped region of p-type
With positively charged foreign ion, be conducive to export in the hole of aggregation；Similarly, when LMDOS transistors are p-type, by source area
The carrier of buried layer aggregation be electronics, the well regions of the LMDOS transistors of p-type is N-type, thus corresponding first doped region
Type is also N-type, and the first doped region of N-type has electronegative foreign ion, is conducive to export the electronics of aggregation.
Further, the depth of the ion implanting injection is less than the thickness of the second substrate so that the first doped region of formation
It can will be close to the carrier assembled in the buried layer of source region or be gathered in cover convenient for the first doped region with the front face of buried layer
Carrier export in buried layer, in addition prevents the first doped region to be formed from being contacted with the bottom of source region, and to the electrical property of source region
It can have an impact.
Further, the injection depth of ion implanting is 0~0.3 micron, and dosage is 1E14~1E16 atom/cm2, make shape
Into the first doped region it is better to the export of the carrier of aggregation.
The LDMOS device of the present invention, the first doped region having in the well region of source region bottom, the first doped region are mixed
Miscellany type is identical with the doping type of well region, and the first doped region is electrically connected with the first metal plug, works in LDMOS device
When, the presence of the first doped region and the first metal plug can prevent carrier from assembling into the buried layer by source area, prevent office
The increase of portion's bulk potential so as to prevent the influence to grid cut-in voltage and output current, improves the performance of LDMOS device.
Description of the drawings
Fig. 1 is the structure diagram of the ldmos transistor of the prior art；
Fig. 2~Figure 15 is the structure diagram of the forming process of LDMOS device of the embodiment of the present invention.
Specific embodiment
The ldmos transistor that existing silicon-on-insulator substrate is formed punctures reduction and hot carrier etc. to ask there are source and drain
Topic.
It has been investigated that ldmos transistor is formed on the second substrate of silicon-on-insulator substrate, ldmos transistor is opposite
A capacitance is formed in the first substrate, charge accumulates on capacitance, and causes unfavorable effect, which is floater effect, with N
For the ldmos transistor of type, specific mechanism is：The highfield in drain region causes channel electrons to accelerate, accelerated electronics
After enough energy are obtained, by ionization by collision, new electron-hole pair is generated, new electron-hole pair is in chamber electric field
It is struggled under effect, electronics is collected by drain terminal, and hole is then gathered in the buried layer by source area, with the increasing in the hole of aggregation
Add, local bulk potential also increases, this can cause the reduction of the grid cut-in voltage at this, so that the output current of drain terminal
Unexpected increase, and the increase of bulk potential can cause the source and drain breakdown voltage of ldmos transistor to reduce.
For this purpose, the present invention provides a kind of LDMOS device and forming method thereof, after ldmos transistor is formed,
The first doped region, source region and the first doped region and the first metal plug electricity are formed in the well region of the source region bottom of ldmos transistor
It connects, thus the hot carrier of the aggregation in the buried layer of source region can be will be close to by the first doped region and the first metal plug
(the ldmos transistor aggregation of N-type is that the LSMOS transistors aggregation in hole, p-type is electronics) export, prevents hot carrier
The aggregation of (hole or electronics) in the buried layer by source area improves the performance of LDMOS device.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 2~Figure 15 is the structure diagram of the forming process of LDMOS device of the embodiment of the present invention.
With reference to figure 2, provide insulation upper silicon substrate 200, the silicon-on-insulator substrate 200 includes the first substrate 11, second
Substrate 12 and the buried layer 13 between the first substrate 11 and the second substrate 12.
Carrier of the silicon-on-insulator substrate 200 as subsequent technique, in the present embodiment, the first substrate 11 and the second lining
The material at bottom 12 is silicon, and the material of buried layer 13 is silica.In other embodiments of the invention, 11 He of the second substrate
The material of second substrate 12 can be SiGe, silicon carbide or germanium etc., the material of buried layer 13 can be silicon nitride, silicon oxynitride,
Fire sand etc..
Subsequently ldmos transistor is formed on the second substrate 12.
In the present embodiment, the silicon-on-insulator substrate 200 includes first area 21 and second area 22, first area 21
With second area 22 can it is adjacent can not also be adjacent, be subsequently formed on the second substrate 12 of first area 21 the first LDMOS crystalline substance
Body pipe is subsequently formed the second ldmos transistor on the second substrate 12 of second area 22.
The first isolation structure 201 is formed in second substrate 12, first isolation structure 201 is used for electric isolation
Adjacent active area.First isolation structure 201 be fleet plough groove isolation structure, the first isolation structure 201 can be silica,
One or more of silicon nitride, silicon oxynitride.
The second isolation structure (not shown) can also be formed in second substrate 12, the drift region packet being subsequently formed
Second isolation structure is enclosed, the second isolation structure can increase the guiding path of the ldmos transistor of formation.
It further includes：Ion implanting is carried out to second substrate 12, well region is formed in second substrate 12.According to treating
The difference of the type of the ldmos transistor of formation, the type of the well region of formation also differ, when ldmos transistor to be formed
During ldmos transistor for N-type, the well region of p-type is formed；When ldmos transistor to be formed is the ldmos transistor of p-type,
Form the well region of N-type.
The first ldmos transistor is subsequently formed on second substrate 12 of first area 21, in the present embodiment, with the of formation
One ldmos transistor is the ldmos transistor of N-type as an example, the impurity of 12 implanting p-type of the second substrate to first area 21
Ion forms P type trap zone in the second substrate 12 of first area 21.The bottom of the P type trap zone and the surface of buried layer 13
Contact, the p type impurity ion are one or more of boron ion, gallium ion, indium ion.
In other embodiments of the invention, first ldmos transistor can be the ldmos transistor of p-type, accordingly
Form N-type well region in the second substrate of first area.
The second ldmos transistor is subsequently formed in second substrate of the second area 22, in the present embodiment, with formation
Second ldmos transistor is the ldmos transistor of p-type as an example, injecting N into the second substrate 12 of the second area 22
The foreign ion of type forms N-type well region in the second substrate 12 of second area 22.The bottom of the N-type well region and buried layer
13 surface contact, the foreign ion of the N-type is one or more of phosphonium ion, arsenic ion, antimony ion.
In other embodiments of the invention, first ldmos transistor can be the ldmos transistor of N-type, accordingly
Form P type trap zone in the second substrate of second area.
It please refers to Fig.3, ldmos transistor is formed on the second substrate 12 of the silicon-on-insulator substrate 200, it is described
Ldmos transistor includes the first ldmos transistor 31 being located on the second substrate 12 of first area 21 and positioned at the secondth area
The second ldmos transistor 32 on second substrate 12 in domain 22.
The ldmos transistor includes：Well region in the second substrate 12；Gate structure on well region, it is described
Gate structure includes the gate dielectric layer 203 on the second substrate of position 12, the gate electrode 205 on gate dielectric layer 203, positioned at grid electricity
Side wall 204 on 203 both sides side wall of pole 205 and gate dielectric layer；Drift region 205 in the well region of gate structure side, institute
The doping type for stating drift region 205 is opposite with the doping type of well region；Drain region 206 in drift region 205, drain region 206
Depth is less than the depth of drift region 205, and the doping type in drain region 206 is identical with the doping type of drift region 205；Positioned at grid knot
Source region 207 in the well region of structure opposite side, the depth of source region 207 are less than the depth of well region, the doping type and well region of source region 207
Doping type it is opposite.
In the present embodiment, the first ldmos transistor 31 is formed on the second substrate 12 on first area 21, first
Ldmos transistor 31 is the ldmos transistor of N-type, and the doping type of the well region of the first ldmos transistor 31 is p-type, source region
207th, the doping type in drift region 205 and drain region is N-type.
The second ldmos transistor 32 is formed on the second substrate 12 on second area 22, the second ldmos transistor 32 is
The ldmos transistor of p-type, the doping type of the well region of the second ldmos transistor 32 are N-type, source region 207, drift region 205 and leakage
The doping type in area 206 is p-type.
In other embodiments of the invention, the ldmos transistor 31 formed on the second substrate 12 on first area 21
Can be the ldmos transistor of p-type, the doping type of the well region of the first ldmos transistor 31 is N-type, source region 207, drift region
205 and drain region 206 doping type be p-type.
In other embodiments of the invention, the 2nd LDMOS crystal is formed on the second substrate 12 on second area 22
Pipe 32 can be the ldmos transistor of N-type, and the doping type of the well region of the second ldmos transistor 32 is p-type, and source region 207 is floated
The doping type for moving area 205 and drain region 206 is N-type.
The forming process of the gate structure is：Gate dielectric material layer and gate electrode are sequentially formed in second substrate 12
Material layer；Etch the layer of gate electrode material and gate dielectric material layer；Gate dielectric layer 203 and position are formed on second substrate
In the gate electrode 205 on gate dielectric layer 203；Side wall 204 is formed on the side wall of 205 both sides of gate dielectric layer 203 and gate electrode.
The source region 207, drift region 205 and drain region 206 are formed by ion implanting, after gate structure is formed, are carried out
First ion implanting forms drift region 205 in the second substrate 12 of gate structure side；The second ion implanting is carried out, in grid
Source region 207 is formed in second substrate 12 of pole structure opposite side, drain region 206 is formed in drift region 205, the drain region 206
Depth is less than the depth of drift region 205.
In other embodiments of the invention, the source region 207, drift region 205 and the forming step in drain region 206 can be
The gate structure is formed before being formed.
In other embodiments of the invention, when forming the second isolation structure in second substrate 12, the grid
The second isolation structure of structure covering part, the drift region 205 surround second isolation structure, and the drain region 206 is located at the
In the drift region 206 of the side of two isolation structures.
It further includes, metal silicide layer, the metal is formed on the source region 207, drain region 206 and 205 surface of gate electrode
The material of silicide layer is nickle silicide etc., and the metal silicide layer is as quarter when being subsequently formed first through hole and the second through-hole
Lose stop-layer.
The forming process of metal silicide layer is：Form the metal for covering second substrate 12 and gate structure surface
Layer, such as nickel metal layer；It anneals to the metal layer, the metallic element in metal layer and source region 207, drain region 206 and grid
Element silicon reacts to form metal silicide layer in electrode 205, removes unreacted metal layer, in source region 207, drain region 206 and grid
205 surface of electrode forms metal silicide layer.
With reference to figure 4, the first medium layer 208 for covering the ldmos transistor and 12 surface of the second substrate is formed.
The forming process of the first medium layer 208 is：It is formed and covers the ldmos transistor and 12 surface of the second substrate
First medium material layer；The first medium material layer is planarized, forms first medium layer 208.
The material of the first medium layer 208 is silica, silica glass etc..
With reference to figure 5, the first medium layer 208 is etched, forms the etched hole 209 for exposing 205 top surface of gate electrode.
It etches the first medium layer 208 and uses dry etch process, metal, shape are subsequently filled in the etched hole 209
Into third metal plug.
With reference to figure 6, third metal plug 210 is formed in the etched hole 209 (with reference to figure 5)；In the first medium
The first metal layer 211 is formed on layer 208.
The third metal plug 210 includes diffusion impervious layer, the gold of full etched hole is filled positioned at diffusion barrier layer surface
Belong to layer.
The diffusion impervious layer is used to prevent the metallic atom in the metal layer from spreading into first medium layer 208.
The diffusion impervious layer can be with single-layer or multi-layer (be more than 1 layer) stacked structure, the material of the diffusion impervious layer
For Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
In one embodiment, the diffusion impervious layer is Ti layers/TiN layer or Ta layers/TaN layers of double stacked structure.
The material of the metal layer can be W, Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several.
Part the first metal layer 211 is electrically connected with third metal plug 210, and another part the first metal layer 211 is located at phase
On first medium layer 208 between adjacent gate structure, the first gold medal on first medium layer 208 between neighboring gate structures
Belonging to layer 211 can be electrically connected with the first metal layer 211 on third metal plug 210.
With reference to figure 7, the second dielectric layer 212 for covering the first metal layer 212 and 208 surface of first medium layer is formed.
The material of the second dielectric layer 212 is silica etc..
After second dielectric layer 212 is formed, support plate 213 is provided, support plate 213 is bonded with second dielectric layer 212, the load
Plate 213 to the first substrate 11 of silicon-on-insulator substrate 200 when subsequently carrying out back technique, for protecting second dielectric layer
212, and as bearing substrate.
The material of the support plate 213 can be silicon, germanium, SiGe, silicon carbide etc..Pass through the works such as Direct Bonding, anode linkage
Support plate 213 and second dielectric layer 212 are bonded together by skill.
With reference to figure 8, first substrate 11 (with reference to figure 7) is removed, exposes the backside surface of buried layer 13；Along buried layer
13 back side carries out ion implanting to the well region of 207 bottom of source region, the first doped region is formed in the well region of 207 bottom of source region
214, first doped region 214 is identical with the doping type of well region.
It should be noted that the buried layer 13 have front and with the opposite back side in front, define buried layer 13 with
For front, the face that buried layer 13 is not contacted with the second substrate 12 is the back side in the face of second substrate 12 contact.
First substrate 11 is removed using chemical mechanical milling tech.
The depth of the ion implanting injection is less than the thickness of the second substrate 12 so that 214 energy of the first doped region of formation
With the front face of buried layer 13, convenient for the first doped region 214 will be close to the carrier assembled in the buried layer 13 of source region 207 or
The carrier export being gathered in buried layer 13, in addition prevents the first doped region 214 to be formed from being contacted with the bottom of source region 207,
And the electric property of source region 207 is had an impact.
In the embodiment of the present invention, ion implanting is carried out along the back side of buried layer 13, the thickness of buried layer 13 is relatively thin, just
In the depth for the first doped region 214 that control is formed.
If the depth of ion implanting relatively depth, the first doped region 214 and the source region 207 of formation can partly overlap, due to
The doping type of one doped region 214 and source region 207 on the contrary, the first doped region 214 it is Chong Die with source region 207 be electricity to source region 207
Being affected for performance is learned, if the dosage that ion implanting is injected is larger, the foreign ion in the first doped region 214 is easily to source region
207 diffusions, and larger junction capacity can be formed between the first doped region 214 and source region 207, influence the property of ldmos transistor
Can, if the dosage of injection is too small, effect derived from carrier can be weakened by forming the first doped region 214.In the present embodiment, institute
The injection depth for stating ion implanting is 0~0.3 micron, and dosage is 1E14~1E16 atom/cm2, make the first doped region to be formed
The carrier export of 214 pairs of aggregations is better.It should be noted that the injection depth of the ion implanting refers to the second substrate
The back side (face contacted with buried layer) and 214 bottom of the first doped region between vertical range.
The ion of the ion implanting injection is N-type impurity ion or the foreign ion of p-type, specifically, the well region is N
During type well region, the foreign ion of ion implanting injection is the foreign ion of N-type, the foreign ion of the N-type is phosphonium ion,
One or more of arsenic ion, antimony ion, when the well region is P type trap zone, the foreign ion of the ion implanting injection is P
The foreign ion of type, the foreign ion of the p-type is one or more of boron ion, gallium ion, indium ion.
The doping type of the first doped region 214 formed is identical with the doping type of well region, this LMDOS crystal with formation
The type of pipe is relevant, and when LMDOS transistors are N-types, the carrier assembled by the buried layer 13 of source area 207 is hole, N
The well region of the LMDOS transistors of type is p-type, thus the type of corresponding first doped region 214 is also p-type, the first doping of p-type
Area 210 has positively charged foreign ion, is conducive to export in the hole of aggregation.Similarly, it is close when LMDOS transistors are p-types
The carrier that the buried layer 13 of source region 207 is assembled is electronics, and the well regions of the LMDOS transistors of p-type is N-type, thus corresponding the
The type of one doped region 214 is also N-type, and the first doped region 214 of N-type has electronegative foreign ion, is conducive to assemble
Electronics export.
After carrying out ion implanting, annealing process is carried out.
With reference to figure 9, the first through hole through the buried layer 13, the first doped region 214, well region and source region 207 is formed
215。
The buried layer 13, the first doped region 214, well region and source region 207 are sequentially etched using dry etch process,
Form first through hole 215.
The dry etch process can be anisotropic plasma etch process.The dry etch process includes
First etch step and the second etch step carry out the first etch step and etch first sub-through hole of the formation of buried layer 13, the
One sub-through hole exposes the back surfaces of the second substrate 12, specifically, the etching gas that the first etch step uses is CF4、C2F6
Or CHF3One or more of, etching cavity pressure is 20 millitorrs to 100 millitorrs, and source radio-frequency power is 500 watts to 2000 watts,
It is 50 watts to 300 watts to bias radio-frequency power；The second etch step is carried out, second substrate 12, shape are etched along the first sub-through hole
Into the second sub-through hole, the first sub-through hole and the second sub-through hole form first through hole, and the gas that the second etch step uses is Cl2With
HBr, reaction chamber pressure are 20 millitorrs to 100 millitorrs, and etching HFRF power is 150 watts to 1000 watts, and etching low frequency is penetrated
Frequency power is 0 watt to 150 watts, and HBr flows are 100sccm to 1000sccm, Cl2Flow is 10sccm to 500sccm.
In embodiments of the present invention, while first through hole 215 are formed, etch the buried layer 13, drift region 205,
Drain region 206 forms the second through-hole 219.
The width of first through hole 215 is less than the width of 207 and first doped region 214 of source region so that source region 207 has and can carry
Enough carriers when working for LDMOS so that the first doped region 214 has enough contacts area with buried layer 13, will
It is exported by the carrier assembled in the buried layer 13 of source area.
With reference to figure 10, the first metal plug 216 of the full first through hole 215 (with reference to figure 10) of filling is formed；It is full to form filling
Second metal plug 220 of the second through-hole 219 (with reference to figure 10).
First metal plug, 216 and second metal plug 220 includes：Positioned at first through hole and the second through-hole side wall and
The diffusion impervious layer of bottom, the metal layer that full through-hole is filled positioned at diffusion barrier layer surface.
The diffusion impervious layer is used to prevent the metallic atom in the metal layer into the second substrate 12 and buried layer 13
Diffusion.
The diffusion impervious layer can be with single-layer or multi-layer (be more than 1 layer) stacked structure, the material of the diffusion impervious layer
For Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
In one embodiment, the diffusion impervious layer is Ti layers/TiN layer or Ta layers/TaN layers of double stacked structure.
The material of the metal layer can be W, Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several.
The process that first metal plug, 216 and second metal plug 220 is formed is：It is formed and covers the first through hole
With the side wall and bottom surface of the second through-hole and the diffusion barrier material layer on 12 surface of buried layer, sputtering technology shape may be used
Into the diffusion barrier material layer；Metal material layer, the metal material layer filling are formed on the diffusion barrier material layer
Full first through hole and the second through-hole, may be used sputtering and electroplating technology form the metal material layer；Remove the buried layer
Extra metal material layer and diffusion barrier material layer, form the first metal plug, second in first through hole on 12 surfaces
The second metal plug is formed in through-hole.
In the present embodiment, first metal plug 216 is electrically connected with source region 207, by the first metal plug 216 to source
Area 207 applies voltage, and first metal plug 216 is also electrically connected with the first doped region 214, on the one hand the first metal plug
216 can to source region 207 provide operating voltage, on the other hand, the first metal plug 216 matched with the first doped region 214 by
By the buried layer 13 of source area 207 assemble or buried layer 13 in the carrier assembled export, prevent the change of local bulk potential
Change.
With reference to figure 11, the first silicon hole for running through the buried layer 13, the second substrate 12, first medium layer 208 is formed
217, the bottom-exposed of first silicon hole 217 goes out the bottom surface of the first metal layer 211.
Before dry etching, mask layer (not shown) is formed in the back surfaces of the buried layer 13, it is described to cover
Have in film layer and expose the opening of 13 position to be etched of buried layer, using the mask layer as mask, using dry etch process,
For example plasma etch process, bosch (Bosch) etching technics etc. etch the buried layer 13, the second substrate 12, first is situated between
Matter layer 208 forms the first silicon hole 217.
The material of the mask layer can be that hard mask materials, the materials of the mask layer such as silica, silicon nitride also may be used
Think the metal masks material such as TiN, TaN.
The mask layer can be single-layer or multi-layer stacked structure.
Since in the embodiment of the present invention, the depth for forming the first silicon hole 217 is deeper, in order to improve corrosion material to be etched with covering
The etching selection ratio of film layer, the consumption of mask layer when reducing etching, in the present embodiment, the mask layer is double stacked knot
Structure, in specific embodiment, including：Silicon nitride layer on buried layer 13, the silicon oxide layer on silicon nitride layer,
Or including being located at the silicon nitride layer on buried layer 13 and the TiN layer on silicon nitride layer.
With reference to figure 12, filling metal forms the first silicon through hole interconnection structure in the first silicon hole 217 (with reference to figure 11)
218。
First silicon through hole interconnection structure 218 includes the diffusion of the side wall and bottom surface positioned at the first silicon hole 217
Barrier layer and the metal layer that full first silicon hole 217 is filled on diffusion impervious layer.
The forming process of first silicon through hole interconnection structure 218 is：Form the side wall for covering first silicon hole 217 and bottom
The diffusion barrier material layer of 13 back surfaces of portion surface and buried layer may be used sputtering technology and form the diffusion barrier material
The bed of material；Metal material layer is formed on the diffusion barrier material layer, the metal material layer fills full first silicon hole 217,
Sputtering may be used and electroplating technology forms the metal material layer；Remove metal extra in 13 back surfaces of buried layer
Material layer and diffusion barrier material layer form the first silicon through hole interconnection structure 218 in the first silicon hole 217.
With reference to figure 13, second metal layer 221 is formed in the back surfaces of buried layer 13, the second metal layer 221 will
First metal plug 216 and the first silicon through hole interconnection structure 218 are electrically connected.
While second metal layer 221 are formed, third metal layer 222, the third metal are formed on buried layer 13
Layer 222 is electrically connected with the second metal plug 220.
With reference to figure 14, formed and cover the second metal layer 221 and 13 back table of third metal layer 222 and buried layer
The third dielectric layer 223 in face has the groove 224 for exposing 221 surface of second metal layer in the third dielectric layer 223.
The groove 224 exposes 221 surface of second metal layer, is electrically connected convenient for second metal layer 221 and external circuit
It connects.
With reference to figure 15, remove the support plate 213 (with reference to figure 14).
The embodiment of the present invention additionally provides a kind of LDMOS device, please refers to Fig.1 3, including：
Silicon substrate in insulation, the silicon-on-insulator substrate include buried layer 13, the second substrate on buried layer 13
12；
Ldmos transistor on second substrate 12, the ldmos transistor include：Positioned at the second substrate 12
Interior well region；Gate structure on well region；Drift region 205 in the well region of gate structure side, the drift region
205 doping type is opposite with the doping type of well region；Drain region 206 in drift region 205, the depth in drain region 206 are less than
The depth of drift region 205, the doping type in drain region 206 are identical with the doping type of drift region 205；Positioned at gate structure opposite side
Well region in source region 207, the depth of source region 207 is less than the depth of well region, the doping type of source region 207 and the doping class of well region
Type is opposite；
The first doped region 214 in the well region in 207 bottom of source region, first doped region 214 are mixed with well region
Miscellany type is identical；
Through the first through hole of the buried layer 13, the first doped region 214, well region and source region 207；
Form the first metal plug 216 of the full first through hole of filling.
It further includes：Cover the first medium layer 208 on 12 surface of the ldmos transistor and the second substrate；Positioned at described
The first metal layer 211 on one dielectric layer 208；Through the buried layer 13, the second substrate 12, first medium layer 208 first
Silicon hole, the bottom-exposed of first silicon hole go out the bottom surface of the first metal layer 211；The of full first silicon hole of filling
One silicon through hole interconnection structure 218；Second metal layer 221 in the back surfaces of buried layer 13, the second metal layer 221
First metal plug 216 and the first silicon through hole interconnection structure 218 are electrically connected.
In one embodiment, the doping type of the well region and the first doped region 214 be p-type, drift region 205, source region 207
Doping type with drain region 206 is N-type.
In another embodiment, the doping type of the well region and the first doped region 214 be N-type, drift region 205, source region
207 and drain region 206 doping type be p-type.
The ldmos transistor formed on second substrate 12 of first area 21 can be the ldmos transistor or p-type of N-type
Ldmos transistor；The ldmos transistor formed on second substrate 12 of second area 22 can be the ldmos transistor of N-type
Or the ldmos transistor of p-type.In the particular embodiment, the type of the ldmos transistor formed on the first area 21 with
The type of the ldmos transistor formed on second area 22 can be identical or differs.
The width of first through hole is less than the width of 207 and first doped region 217 of source region.
First doped region 214 is contacted with the surface of buried layer 13.
First metal plug 216 includes：Diffusion impervious layer positioned at first through hole side wall and bottom is hindered positioned at diffusion
The metal layer of the full through-hole of barrier surface filling.
It further includes：Buried layer 13, drift region 205 and second through-hole in drain region 206 described in through part；Filling full the
Second metal plug 220 of two through-holes.
Third metal layer 222 on 13 back side of buried layer, 222 and second metal plug 220 of third metal layer
Electrical connection.
It should be noted that other about LDMOS device limit or description, please refer to aforementioned LDMOS device and formed
The definitions relevant of journey part or description, details are not described herein.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of LDMOS device, which is characterized in that including：
Silicon-on-insulator substrate is provided, the silicon-on-insulator substrate includes the first substrate, the second substrate and positioned at the first substrate
And the second buried layer between substrate；
Ldmos transistor is formed on second substrate, the ldmos transistor includes：Well region in the second substrate,
The depth in source region and drain region in well region, source region and drain region is less than the depth of well region, the doping type in source region and drain region with
The doping type of well region is opposite；
First substrate is removed, exposes the backside surface of buried layer；
From the back side of buried layer, ion implanting is carried out to the well region of source region bottom, first is formed in the well region of source region bottom and is mixed
Miscellaneous area, first doped region are identical with the doping type of well region；
Form the first through hole through the buried layer, the first doped region, well region and source region, the width of the first through hole
Less than source region and the width of the first doped region；
Form the first metal plug of the full first through hole of filling.
2. the forming method of LDMOS device as described in claim 1, which is characterized in that the well region and the first doped region
Doping type is p-type, and the doping type of drift region, source region and drain region is N-type.
3. the forming method of LDMOS device as described in claim 1, which is characterized in that the well region and the first doped region
Doping type is N-type, and the doping type of drift region, source region and drain region is p-type.
4. the forming method of LDMOS device as described in claim 1, which is characterized in that first doped region and buried layer
Front face.
5. the forming method of LDMOS device as described in claim 1, which is characterized in that the depth of the ion implanting injection
Less than the thickness of the second substrate, the injection depth of the ion implanting refer to the second substrate the back side and the first doped region bottom it
Between vertical range.
6. the forming method of LDMOS device as claimed in claim 5, which is characterized in that the injection depth of the ion implanting
It it is 0~0.3 micron, dosage is 1E14~1E16atom/cm2。
7. the forming method of LDMOS device as claimed in claim 6, which is characterized in that after carrying out ion implanting, anneal
Technique.
8. the forming method of LDMOS device as described in claim 1, which is characterized in that first metal plug includes：Position
Diffusion impervious layer in first through hole side wall and bottom, the metal layer positioned at the full through-hole of diffusion barrier layer surface filling.
9. the forming method of LDMOS device as described in claim 1, which is characterized in that further include：Form the same of first through hole
When, form through part buried layer, drift region and second through-hole in drain region.
10. the forming method of LDMOS device as claimed in claim 9, which is characterized in that form the of full second through-hole of filling
Two metal plugs；Form the first medium layer for covering the ldmos transistor and the second substrate surface；In the first medium layer
Upper formation the first metal layer；Formed through the buried layer, the second substrate, first medium layer the first silicon hole, described first
The bottom-exposed of silicon hole goes out the bottom surface of the first metal layer；It is mutual that the first silicon hole of metal formation is filled in the first silicon hole
Link structure；Form second metal layer in the back surfaces of buried layer, the second metal layer is by the first metal plug and first
Silicon through hole interconnection structure is electrically connected.
11. the forming method of LDMOS device as described in claim 1, which is characterized in that the ldmos transistor includes：Position
Well region in the second substrate；Gate structure on well region；Drift region in the well region of gate structure side, it is described
The doping type of drift region is opposite with the doping type of well region；Drain region in drift region, the depth in drain region are less than drift region
Depth, the doping type in drain region is identical with the doping type of drift region；Source region in the well region of gate structure opposite side,
The depth of source region is less than the depth of well region, and the doping type of source region is opposite with the doping type of well region.
12. a kind of LDMOS device, which is characterized in that including：
Silicon-on-insulator substrate, the silicon-on-insulator substrate include buried layer, the second substrate on buried layer；
Ldmos transistor on second substrate, the ldmos transistor include：Well region in the second substrate,
The depth in source region and drain region in well region, source region and drain region is less than the depth of well region, the doping type in source region and drain region with
The doping type of well region is opposite；
The first doped region in the well region in source region bottom, first doped region are identical with the doping type of well region；
Through the first through hole of the buried layer, the first doped region, well region and source region, the width of the first through hole is less than
The width of source region and the first doped region；
Form the first metal plug of the full first through hole of filling.
13. LDMOS device as claimed in claim 12, which is characterized in that the doping type of the well region and the first doped region
For p-type, the doping type of drift region, source region and drain region is N-type.
14. LDMOS device as claimed in claim 12, which is characterized in that the doping type of the well region and the first doped region
For N-type, the doping type of drift region, source region and drain region is p-type.
15. LDMOS device as claimed in claim 12, which is characterized in that the surface of first doped region and buried layer connects
It touches.
16. LDMOS device as claimed in claim 12, which is characterized in that first metal plug includes：It is logical positioned at first
Hole side wall and the diffusion impervious layer of bottom, the metal layer positioned at the full through-hole of diffusion barrier layer surface filling.
17. LDMOS device as claimed in claim 12, which is characterized in that further include：Through part buried layer, drift region, with
And second through-hole in drain region；Second metal plug of full second through-hole of filling；Cover the ldmos transistor and the second substrate table
The first medium layer in face；The first metal layer on the first medium layer；Through the buried layer, the second substrate, first
First silicon hole of dielectric layer, the bottom-exposed of first silicon hole go out the bottom surface of the first metal layer；Filling full first
First silicon through hole interconnection structure of silicon hole；Second metal layer in the back surfaces of buried layer, the second metal layer
First metal plug and the first silicon through hole interconnection structure are electrically connected.
18. LDMOS device as claimed in claim 12, which is characterized in that the ldmos transistor includes：Positioned at the second lining
Well region in bottom；Gate structure on well region；Drift region in the well region of gate structure side, the drift region
Doping type is opposite with the doping type of well region；Drain region in drift region, the depth in drain region are less than the depth of drift region, leakage
The doping type in area is identical with the doping type of drift region；Source region in the well region of gate structure opposite side, the depth of source region
Degree is less than the depth of well region, and the doping type of source region is opposite with the doping type of well region.
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| CN109524355B (en) * | 2018-10-30 | 2020-11-10 | 上海集成电路研发中心有限公司 | Structure and forming method of semiconductor device |
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| CN103000626A (en) * | 2012-11-28 | 2013-03-27 | 深圳市明微电子股份有限公司 | High-voltage device in composite structure and starting circuit |
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| CN103000626A (en) * | 2012-11-28 | 2013-03-27 | 深圳市明微电子股份有限公司 | High-voltage device in composite structure and starting circuit |
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