CN105405879A - LDMOS device and forming method therefor - Google Patents
LDMOS device and forming method therefor Download PDFInfo
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- CN105405879A CN105405879A CN201410381682.5A CN201410381682A CN105405879A CN 105405879 A CN105405879 A CN 105405879A CN 201410381682 A CN201410381682 A CN 201410381682A CN 105405879 A CN105405879 A CN 105405879A
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Abstract
The invention discloses an LDMOS device and a forming method therefor, and the device comprises an insulating upper silicon substrate which comprises a first substrate, a second substrate, and a buried layer located between the first substrate and the second substrate; an LDMOS transistor which is located on the second substrate and comprises a well region in the second substrate, a source region in the well region and a drain region in the well region, wherein the depth of the source region and the depth of the drain region are less than the depths of the well region, and the doping type of the source region and the doping type of the drain region are opposite to the doping type of the well region; a first dielectric layer which covers the surface of the LDMOS transistor and the surface of the second substrate; a first through hole which passes through the first dielectric layer and the source region; a first doping region which is located in the well region at the bottom of the source region, wherein the doping type of the first doping region is the same as the doping type of the well region; and a first metal plug which is filled in the first through hole, and is electrically connected with the source region and the first doping region. The device overcomes the impact from a floating body effect.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of LDMOS device and forming method thereof.
Background technology
Power field effect pipe mainly comprises vertical bilateral diffusion field-effect pipe (VDMOS, VerticalDouble-DiffusedMOSFET) and horizontal dual pervasion field effect pipe (LDMOS, LateralDouble-DiffusedMOSFET) two type.Wherein, compared to vertical bilateral diffusion field-effect pipe (VDMOS), horizontal dual pervasion field effect pipe (LDMOS) has plurality of advantages, such as, the latter has better thermal stability and frequency stability, higher gain and durability, lower feedback capacity and thermal resistance, and constant input impedance and simpler biasing circuit.
Silicon-on-insulator (SOI, SiliconOnInsulator) substrate is a kind of substrate for IC manufacturing.Compared with the body silicon substrate widely applied at present, SOI substrate has a lot of advantage: the parasitic capacitance of the integrated circuit adopting SOI substrate to make is little, integration density is high, short-channel effect is little, speed is fast, and the medium isolation of components and parts in integrated circuit can be realized, completely eliminate the parasitic latch-up in body silicon integrated circuit.
With reference to figure 1, Fig. 1 is the structural representation of the ldmos transistor of the N-type utilizing silicon-on-insulator substrate to be formed, described ldmos transistor comprises: silicon-on-insulator substrate 100, and described silicon-on-insulator substrate 100 comprises the first substrate 11, the buried layer 13 be positioned on the first substrate 11, the second substrate 12 be positioned on buried layer 13; Be positioned at the P type trap zone (not shown) of the second substrate 12; Be positioned at the N-type drift region 101 of P type trap zone; Be arranged in the fleet plough groove isolation structure 104 of N-type drift region 101, described fleet plough groove isolation structure 104 for increasing the path of horizontal dual pervasion field effect pipe conducting, to increase the puncture voltage of horizontal dual pervasion field effect pipe; Be positioned at the P type tagma 106 of the P type trap zone of N-type drift region 101 side; Be positioned at the grid structure 105 in Semiconductor substrate, described grid structure 105 is across described P type tagma 106 and N-type drift region 101, and part is positioned on fleet plough groove isolation structure 104, described grid structure 105 comprises and is positioned at the gate dielectric layer on the second substrate 12, the gate electrode be positioned on gate dielectric layer, the side wall be positioned on gate dielectric layer and gate electrode both sides sidewall; Be positioned at the source region 102 in the P type tagma 106 of grid structure 105 side, and be positioned at the drain region 103 of N-type drift region 101 of opposite side of grid structure 105, the doping type in source region 102 and drain region 103 is N-type.
The ldmos transistor performance that existing silicon-on-insulator substrate is formed still has much room for improvement.
Summary of the invention
The problem that the present invention solves how to prevent floater effect on the impact of the ldmos transistor performance that silicon-on-insulator substrate is formed.
For solving the problem, the invention provides a kind of formation method of LDMOS device, comprising: provide insulation upper silicon substrate, described silicon-on-insulator substrate comprises the first substrate, the second substrate and the buried layer between the first substrate and the second substrate; Described second substrate forms ldmos transistor, described ldmos transistor comprises: the well region being positioned at the second substrate, be positioned at source region and the drain region of well region, the degree of depth in source region and drain region is less than the degree of depth of well region, and the doping type in source region and drain region is contrary with the doping type of well region; Form the first medium layer covering described ldmos transistor and the second substrate surface; Etch the second substrate of described first medium layer and segment thickness, form the first through hole, described first through hole runs through the thickness in first medium layer and source region, and exposes the well region bottom source region; Carry out ion implantation along the first through hole, form the first doped region in the well region bottom source region, the doping type of the first doped region is identical with the doping type of well region;
Form first metal plug of filling full first through hole.
Optionally, the doping type of described well region and the first doped region is P type, and the doping type in drift region, source region and drain region is N-type.
Optionally, the doping type of described well region and the first doped region is N-type, and the doping type in drift region, source region and drain region is P type.
Optionally, the degree of depth of described first through hole is greater than the degree of depth in source region, and the width of the first through hole is less than the width in source region.
Optionally, the described bottom of the first doped region and the surface contact of buried layer, the width of the first doped region is greater than the width of the first through hole.
The injection degree of depth of described ion implantation equals the thickness of the second substrate.
The degree of depth that described ion implantation is injected is 0.1 ~ 0.5 micron, and dosage is 1E14 ~ 1E16atom/cm
2, implant angle 0 ~ 10 degree
Optionally, after carrying out ion implantation, carry out annealing process.
Optionally, described first metal plug comprises: be positioned at the diffusion impervious layer of the first through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
Optionally, also comprise: etch described first medium layer, form the second through hole in first medium layer, described second through hole exposes the surface in drain region.
Optionally, second metal plug of filling full second through hole is formed; Form the metal interconnecting wires be electrically connected with the first metal plug and the second metal plug.
Optionally, described ldmos transistor comprises: the well region being positioned at the second substrate; Be positioned at the grid structure on well region; Be positioned at the drift region of the well region of grid structure side, the doping type of described drift region is contrary with the doping type of well region; Be positioned at the drain region of drift region, the degree of depth in drain region is less than the degree of depth of drift region, and the doping type in drain region is identical with the doping type of drift region; Be positioned at the source region of the well region of grid structure opposite side, the degree of depth in source region is less than the degree of depth of well region, and the doping type in source region is contrary with the doping type of well region.
Present invention also offers a kind of LDMOS device, comprising: silicon substrate in insulation, described silicon-on-insulator substrate comprises the first substrate, the second substrate and the buried layer between the first substrate and the second substrate; Be positioned at the ldmos transistor on the second substrate, described ldmos transistor comprises: the well region being positioned at the second substrate, be positioned at source region and the drain region of well region, the degree of depth in source region and drain region is less than the degree of depth of well region, and the doping type in source region and drain region is contrary with the doping type of well region; Cover the first medium layer of described ldmos transistor and the second substrate surface; Be positioned at the first through hole of the second substrate of first medium layer and segment thickness, described first through hole runs through the thickness in first medium layer and source region, and exposes the well region bottom source region; Be positioned at the first doped region of the well region bottom source region, the doping type of the first doped region is identical with the doping type of well region; Fill the first metal plug of full first through hole, the first metal plug is electrically connected with source region and the first doped region.
Optionally, the doping type of described well region and the first doped region is P type, and the doping type in drift region, source region and drain region is N-type.
Optionally, the doping type of described well region and the first doped region is N-type, and the doping type in drift region, source region and drain region is P type.
Optionally, the degree of depth of described first through hole is greater than the degree of depth in source region, and the width of the first through hole is less than the width in source region.
Optionally, the degree of depth of described first doped region equals the thickness of the second substrate, and the width of the first doped region is greater than the width of the first through hole, the described bottom of the first doped region and the surface contact of buried layer.
Optionally, described first metal plug comprises: be positioned at the diffusion impervious layer of the first through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
Optionally, also comprise: the second metal plug being arranged in first medium layer, the second metal plug is electrically connected with drain region; Be positioned at the metal interconnecting wires that first medium layer is electrically connected with the first metal plug and the second metal plug on the surface.
Optionally, described ldmos transistor comprises: the well region being positioned at the second substrate; Be positioned at the grid structure on well region; Be positioned at the drift region of the well region of grid structure side, the doping type of described drift region is contrary with the doping type of well region; Be positioned at the drain region of drift region, the degree of depth in drain region is less than the degree of depth of drift region, and the doping type in drain region is identical with the doping type of drift region; Be positioned at the source region of the well region of grid structure opposite side, the degree of depth in source region is less than the degree of depth of well region, and the doping type in source region is contrary with the doping type of well region.
Compared with prior art, technical scheme of the present invention has the following advantages:
The formation method of ldmos transistor of the present invention, after the second substrate of silicon substrate on insulator forms ldmos transistor, forms the first medium layer covering described ldmos transistor and the second substrate surface; Etch the second substrate of described first medium layer and segment thickness, form the first through hole, described first through hole runs through the thickness in first medium layer and source region, and exposes the well region bottom source region; Carry out ion implantation along the first through hole, form the first doped region in the well region bottom source region, the doping type of the first doped region is identical with the doping type of well region; Form first metal plug of filling full first through hole.The hot carrier of assembling in the buried layer in source region (the LSMOS transistor for hole, P type assembled of the ldmos transistor of N-type assemble be electronics) can be derived by the first doped region and the first metal plug, prevent the gathering of hot carrier (hole or electronics) in the buried layer near source region, prevent the increase of local bulk potential, thus prevent the impact on grid cut-in voltage and output current, improve the performance of LDMOS device;
In addition, the doping type of the first doped region formed is identical with the doping type of well region, this is relevant to the type of the LMDOS transistor formed, when LMDOS transistor is N-type, the charge carrier that buried layer near source region is assembled is hole, and the well region of the LMDOS transistor of N-type is P type, and thus the type of corresponding first doped region 210 is also P type, first doped region of P type has the foreign ion of positively charged, and being conducive to derives the hole of assembling; In like manner, when LMDOS transistor is P type, the charge carrier that buried layer near source region is assembled is electronics, the well region of the LMDOS transistor of P type is N-type, thus the type of corresponding first doped region is also N-type, first doped region of N-type has electronegative foreign ion, and being conducive to derives the electronics assembled.
Further, the degree of depth that described ion implantation is injected is the thickness equaling the second substrate, make the bottom of the first doped region and the surface contact of buried layer of formation, ldmos transistor operationally, when hot carrier (hole or electronics) is gathered in the buried layer near source region or when assembling to the buried layer near source region, charge carrier near mask layer is easily derived by the first doped region, and the width of the first doped region is greater than the width of the first through hole, first doped region is increased with the contact area of the buried layer near source region, more be conducive to the derivation of the charge carrier assembled.
Further, the degree of depth that described ion implantation is injected is 0.1 ~ 0.5 micron, and dosage is 1E14 ~ 1E16atom/cm
2, implant angle 0 ~ 10 degree, makes the first doped region of formation derive effect to the charge carrier assembled better.
LDMOS device of the present invention, the first doped region that the well region be positioned at bottom source region has, the doping type of the first doped region is identical with the doping type of well region, and the first doped region is electrically connected with the first metal plug, when LDMOS device works, the existence of the first doped region and the first metal plug, can prevent charge carrier from assembling in the buried layer near source region, prevent the increase of local bulk potential, thus prevent the impact on grid cut-in voltage and output current, improve the performance of LDMOS device.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art ldmos transistor;
Fig. 2 ~ Figure 10 is the structural representation of the forming process of embodiment of the present invention LDMOS device.
Embodiment
There is source and drain and puncture the problems such as reduction and hot carrier in the ldmos transistor that existing silicon-on-insulator substrate is formed.
Find after deliberation, ldmos transistor is formed on the second substrate of silicon-on-insulator substrate, ldmos transistor forms an electric capacity relative to the first substrate, electric charge accumulates on electric capacity, and cause disadvantageous effect, this effect is floater effect, for the ldmos transistor of N-type, its concrete mechanism is: the highfield in drain region makes channel electrons accelerate, accelerated electronics is after obtaining enough energy, pass through ionization by collision, produce new electron-hole pair, new electron-hole pair is separated under the effect of electric field, electronics is collected by drain terminal, hole is then gathered in the buried layer in source region, along with the increase in the hole of assembling, local bulk potential also increases, this can cause the reduction of the grid cut-in voltage at this place, make the unexpected increase of the output current of drain terminal, and the increase of bulk potential, the source and drain puncture voltage of ldmos transistor can be made to reduce.
For this reason, the invention provides a kind of LDMOS device and forming method thereof, after formation ldmos transistor, the first doped region is formed in well region bottom the source region of ldmos transistor, source region and the first doped region are electrically connected with the first metal plug, thus by the first doped region and the first metal plug can (what the ldmos transistor of N-type assembled be hole by the hot carrier of assembling in the buried layer in source region, what the LSMOS transistor of P type was assembled be electronics) derivation, prevent the gathering of hot carrier (hole or electronics) in the buried layer near source region, improve the performance of LDMOS device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 2 ~ Figure 10 is the structural representation of the forming process of embodiment of the present invention LDMOS device.
With reference to figure 2, provide insulation upper silicon substrate 200, described silicon-on-insulator substrate 200 comprises the first substrate 11, second substrate 12 and the buried layer 13 between the first substrate 11 and the second substrate 12.
Described silicon-on-insulator substrate 200 is as the carrier of subsequent technique, and in the present embodiment, the material of the first substrate 11 and the second substrate 12 is silicon, and the material of buried layer 13 is silica.In other embodiments of the invention, the material of described second substrate 11 and the second substrate 12 can be SiGe, carborundum or germanium etc., and the material of buried layer 13 can be silicon nitride, silicon oxynitride, fire sand etc.
Follow-uply on the second substrate 12, form ldmos transistor.
In the present embodiment, described silicon-on-insulator substrate 200 comprises first area 21 and second area 22, first area 21 and second area 22 can adjacent also can be non-conterminous, follow-up formation first ldmos transistor on second substrate 12 of first area 21, follow-up formation second ldmos transistor on the second substrate 12 of second area 22.
Be formed with the first isolation structure 201 in described second substrate 12, described first isolation structure 201 is for the adjacent active area of electric isolation.Described first isolation structure 201 is fleet plough groove isolation structure, and the first isolation structure 201 can be one or more in silica, silicon nitride, silicon oxynitride.
Can also form the second isolation structure (not shown) in described second substrate 12, the drift region of follow-up formation surrounds described second isolation structure, and the second isolation structure can increase the guiding path of the ldmos transistor formed.
Also comprise: ion implantation is carried out to described second substrate 12, in described second substrate 12, form well region.According to the difference of the type of ldmos transistor to be formed, the type of the well region of formation is not identical yet, when ldmos transistor to be formed is the ldmos transistor of N-type, forms the well region of P type; When ldmos transistor to be formed is the ldmos transistor of P type, form the well region of N-type.
Follow-up formation first ldmos transistor on second substrate 12 of first area 21, in the present embodiment, the ldmos transistor being N-type with the first ldmos transistor formed exemplarily, to the foreign ion of the second substrate 12 implanting p-type of first area 21, in the second substrate 12 of first area 21, form P type trap zone.The bottom of described P type trap zone and the surface contact of buried layer 13, described p type impurity ion is one or more in boron ion, gallium ion, indium ion.
In other embodiments of the invention, described first ldmos transistor can be the ldmos transistor of P type, forms N-type well region accordingly in the second substrate of first area.
Follow-up formation second ldmos transistor in second substrate of described second area 22, in the present embodiment, the ldmos transistor being P type with the second ldmos transistor formed exemplarily, in the second substrate 12 of described second area 22, inject the foreign ion of N-type, in the second substrate 12 of second area 22, form N-type well region.The bottom of described N-type well region and the surface contact of buried layer 13, the foreign ion of described N-type is one or more in phosphonium ion, arsenic ion, antimony ion.
In other embodiments of the invention, described first ldmos transistor can be the ldmos transistor of N-type, forms P type trap zone accordingly in the second substrate of second area.
Please refer to Fig. 3, second substrate 12 of described silicon-on-insulator substrate 200 forms ldmos transistor, described ldmos transistor comprises the first ldmos transistor 31 be positioned on the second substrate 12 of first area 21, and is positioned at the second ldmos transistor 32 on the second substrate 12 of second area 22.
Described ldmos transistor comprises: the well region being positioned at the second substrate 12; Be positioned at the grid structure on well region, described grid structure comprises the gate dielectric layer 203 on position second substrate 12, the gate electrode 205 be positioned on gate dielectric layer 203, the side wall 204 be positioned on gate electrode 205 and gate dielectric layer 203 both sides sidewall; Be positioned at the drift region 205 of the well region of grid structure side, the doping type of described drift region 205 is contrary with the doping type of well region; Be positioned at the drain region 206 of drift region 205, the degree of depth in drain region 206 is less than the degree of depth of drift region 205, and the doping type in drain region 206 is identical with the doping type of drift region 205; Be positioned at the source region 207 of the well region of grid structure opposite side, the degree of depth in source region 207 is less than the degree of depth of well region, and the doping type in source region 207 is contrary with the doping type of well region.
In the present embodiment, the second substrate 12 on first area 21 forms the first ldmos transistor 31, first ldmos transistor 31 is the ldmos transistor of N-type, and the doping type of the well region of the first ldmos transistor 31 is P type, and the doping type in source region 207, drift region 205 and drain region is N-type.
The second substrate 12 on second area 22 forms the second ldmos transistor 32, second ldmos transistor 32 is the ldmos transistor of P type, the doping type of the well region of the second ldmos transistor 32 is N-type, and the doping type in source region 207, drift region 205 and drain region 206 is P type.
In other embodiments of the invention, the ldmos transistor 31 that the second substrate 12 on first area 21 is formed can be the ldmos transistor of P type, the doping type of the well region of the first ldmos transistor 31 is N-type, and the doping type in source region 207, drift region 205 and drain region 206 is P type.
In other embodiments of the invention, the second substrate 12 on second area 22 being formed the second ldmos transistor 32 can be the ldmos transistor of N-type, the doping type of the well region of the second ldmos transistor 32 is P type, and the doping type in source region 207, drift region 205 and drain region 206 is N-type.
The forming process of described grid structure is: form gate dielectric material layer and layer of gate electrode material successively at described second substrate 12; Etch described layer of gate electrode material and gate dielectric material layer; The gate electrode 205 described second substrate 12 being formed gate dielectric layer 203 and is positioned on gate dielectric layer 203; The sidewall of gate dielectric layer 203 and gate electrode 205 both sides forms side wall 204.
Described source region 207, drift region 205 and drain region 206 are formed by ion implantation, after formation grid structure, carry out the first ion implantation, in the second substrate 12 of grid structure side, form drift region 205; Carry out the second ion implantation, in the second substrate 12 of grid structure opposite side, form source region 207, in drift region 205, form drain region 206, the degree of depth in described drain region 206 is less than the degree of depth of drift region 205.
In other embodiments of the invention, the forming step in described source region 207, drift region 205 and drain region 206 can be formed before described grid structure is formed.
In other embodiments of the invention, when forming the second isolation structure in described second substrate 12, described grid structure cover part second isolation structure, described drift region 205 surrounds described second isolation structure, and described drain region 206 is positioned at the drift region 206 of the side of the second isolation structure.
With reference to figure 4, form the first medium layer 208 covering described ldmos transistor and the second substrate 12 surface.
The forming process of described first medium layer 208 is: form the first medium material layer covering described ldmos transistor and the second substrate 12 surface; First medium material layer described in planarization, forms first medium layer 208.
The material of first medium layer 208 is silica, silex glass etc.
With reference to figure 5, etch the second substrate 12 of described first medium layer 208 and segment thickness, form the first through hole 209, described first through hole 209 runs through the thickness in first medium layer 208 and source region 207, and exposes the well region bottom source region 207.
The second substrate 12 etching described first medium layer 208 and segment thickness adopts dry etch process.Described dry etch process can be anisotropic plasma etch process.Described dry etch process comprises the first etch step and the second etch step, carry out the first etch step to etch described first medium layer and form the first sub-through hole, first sub-through hole exposes the surface of the second substrate 12, concrete, and the etching gas that the first etch step adopts is CF
4, C
2f
6or CHF
3in one or more, etching cavity pressure is 20 millitorr to 100 millitorrs, and source radio-frequency power is 500 watts to 2000 watts, and biased radio-frequency power is 50 watts to 300 watts; Carry out the second etch step, along the second substrate 12 described in the first sub-via etch, form the second sub-through hole, the first sub-through hole and the second sub-through hole form the first through hole, and the gas that the second etch step adopts is Cl
2and HBr, reaction chamber pressure is 20 millitorr to 100 millitorrs, and etching HFRF power is 150 watts to 1000 watts, and etching low frequency RF power is 0 watt to 150 watts, and HBr flow is 100sccm to 1000sccm, Cl
2flow is 10sccm to 500sccm.
The first through hole 209 formed is except running through the thickness of described first medium layer 208, also run through the thickness in described source region 207, the bottom-exposed of described first through hole 209 is made to go out well region between the bottom in source region 207 and buried layer 13, ion implantation formation is carried out along the first through hole 209 in the first doped region formed in follow-up well region bottom source region 207, therefore the relative position of the first doped region and the first through hole 209 can be controlled very accurately, when the first through hole 209 fills the first metal plug, the relative position (the first doped region surrounds the bottom of the first metal plug) of the first metal plug and the first doped region can be controlled very accurately, thus the first doped region made and the first metal plug and good point cantact performance, by formed the first doped region and the first metal plug hot carrier (hole or electronics) is derived, prevent hot carrier (hole or electronics) from assembling at the buried layer 13 near source region.
The degree of depth of described first through hole 209 is greater than the degree of depth in source region 207, and the width of the first through hole 209 is less than the width in source region 207.
With reference to figure 6, carry out ion implantation along the first through hole 209, the doping type forming the first doped region 210, doped region 210, first in the well region bottom source region 207 is identical with the doping type of well region.
The degree of depth that described ion implantation is injected is the thickness equaling the second substrate 12, make the bottom of the first doped region 210 and the surface contact of buried layer 13 of formation, ldmos transistor operationally, when hot carrier (hole or electronics) is gathered in the buried layer 13 near source region or when assembling to the buried layer 13 near source region 207, charge carrier near mask layer 13 is easily derived by the first doped region 210, and the width of the first doped region 210 is greater than the width of the first through hole 209, first doped region 210 is increased with the contact area of the buried layer 12 near source region 207, more be conducive to the derivation of the charge carrier assembled.It should be noted that the degree of depth that ion implantation is injected refers to the bottom of the first doped region 210 and the vertical range on the second substrate 12 surface.
Find through research, when carrying out ion implantation, the degree of depth that ion implantation is injected crosses the isolation performance that deeply can affect buried layer 13, when the degree of depth of injection is crossed shallow, the first doped region 210 formed has certain distance with buried layer 13, and the charge carrier assembled in buried layer 13 is not easily derived; The larger words of dosage that ion implantation is injected, foreign ion in first doped region 210 easily spreads to source region 207, and can form larger junction capacitance between the first doped region and source region 207, affects the performance of ldmos transistor, the dosage injected is too small, and the effect that charge carrier is derived can weaken; Owing to being carry out ion implantation along the first through hole 209, the words that implant angle is larger, the foreign ion injected effectively can not be injected into the second substrate 12 bottom the first through hole 209, the words of non-angular injection in this way, the first doped region 210 formed only can be positioned at the bottom of the first through hole 209, the width of the first doped region 210 is affected, and forming 210 pairs, the first doped region charge carrier derivation effect can weaken.Therefore, in the present embodiment, the degree of depth that described ion implantation is injected is 0.1 ~ 0.5 micron, and dosage is 1E14 ~ 1E16atom/cm
2, implant angle 0 ~ 10 degree, makes the first doped region 210 of formation derive effect to the charge carrier assembled better.It should be noted that, implant angle is the angle of ion implantation direction and the second substrate 12 surface normal.
The ion that described ion implantation is injected is the foreign ion of N-type impurity ion or P type, concrete, when described well region is N-type well region, the foreign ion that described ion implantation is injected is the foreign ion of N-type, the foreign ion of described N-type is one or more in phosphonium ion, arsenic ion, antimony ion, when described well region is P type trap zone, the foreign ion that described ion implantation is injected is the foreign ion of P type, and the foreign ion of described P type is one or more in boron ion, gallium ion, indium ion.
The doping type of the first doped region 210 formed is identical with the doping type of well region, this is relevant to the type of the LMDOS transistor formed, during LMDOS transistor during N-type, the charge carrier that buried layer 13 near source region 207 is assembled is hole, the well region of the LMDOS transistor of N-type is P type, thus the type of corresponding first doped region 210 is also P type, and the first doped region 210 of P type has the foreign ion of positively charged, and being conducive to derives the hole of assembling.In like manner, during LMDOS transistor during P type, the charge carrier that buried layer 13 near source region 207 is assembled is electronics, the well region of the LMDOS transistor of P type is N-type, thus the type of corresponding first doped region 210 is also N-type, first doped region 210 of N-type has electronegative foreign ion, and being conducive to derives the electronics assembled.
After carrying out ion implantation, carry out annealing process, activate the foreign ion injected.
With reference to figure 7, etch described first medium layer 208, form the second through hole 211 in first medium layer 208, described second through hole 211 exposes the surface in drain region 206.
Etch described first medium layer 208 and adopt dry etch process, described dry etch process can be plasma etch process, and the etching gas that plasma etch process adopts is the etching gas adopted is CF
4, C
2f
6or CHF
3in one or more.
With reference to figure 8, form first metal plug 212 of filling full first through hole, form second metal plug 213 of filling full second through hole.
Described first metal plug 212 and the second metal plug 213 comprise: be positioned at the diffusion impervious layer of the first through hole and the second through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
Described diffusion impervious layer spreads in first medium layer 208 for preventing the metallic atom in described metal level.
Described diffusion impervious layer can single or multiple lift (being greater than 1 layer) stacked structure, the material of described diffusion impervious layer is Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
In one embodiment, described diffusion impervious layer is the double stacked structure of Ti layer/TiN layer or Ta layer/TaN layer.
The material of described metal level can be W, Al, Cu, Ti, Ag, Au, Pt, Ni wherein one or more.
The process that described first metal plug 212 and the second metal plug 213 are formed is: formed and cover described first through hole and the sidewall of the second through hole and the diffusion barrier material layer on lower surface and first medium layer 208 surface, sputtering technology can be adopted to form described diffusion barrier material layer; Described diffusion barrier material layer forms metal material layer, and described metal material layer fills full first through hole and the second through hole, and sputtering and electroplating technology can be adopted to form described metal material layer; Remove described first medium layer 208 metal material layer unnecessary on the surface and diffusion barrier material layer, in the first through hole, form the first metal plug, in the second through hole, form the second metal plug.
In the present embodiment, described first metal plug 212 is electrically connected with source region 207, apply voltage by the first metal plug 212 to source region 207, described first metal plug 212 is also electrically connected with the first doped region 210, is derived by the charge carrier assembled by the first doped region 210.
With reference to figure 9, described first medium layer 208 forms the first metal interconnecting wires 214 and the second metal interconnecting wires 215.
Described first metal interconnecting wires 214 is electrically connected with the first metal plug 212, and described second metal interconnecting wires 215 is electrically connected with the second metal plug 213.
The forming process of the first metal interconnecting wires 214 and the second metal interconnecting wires 215 is: form the first diffusion impervious layer of the described first medium layer 208 of covering, the first diffusion impervious layer is formed metal material layer, on metal material layer, form the second diffusion impervious layer; Etch described second diffusion impervious layer, metal material layer and the first diffusion impervious layer successively, form the first metal interconnecting wires 214 and the second metal interconnecting wires 215.
With reference to Figure 10, form the second dielectric layer 216 covering described first metal interconnecting wires 214, second metal interconnecting wires 215 and first medium layer 208 surface.
The first interconnection structure (not shown) and the second interconnection structure (not shown) can be formed in described second dielectric layer 216, described first interconnection structure is electrically connected with the first metal interconnecting wires 214, and described second interconnection structure is electrically connected with the second metal interconnecting wires 215.
Described second dielectric layer 216 can be multilayer (being greater than 1 layer) stacked structure.
Continue, with reference to Figure 10, described second dielectric layer 216 to form top layer metallic layer 217; Form the top layer dielectric layer 218 covering upper described top layer metallic layer 217 and second dielectric layer 216, described top layer dielectric layer 218 has the groove 219 exposing Portions of top layer metal level 217 surface.
The described top layer metallic layer 217 of a part is electrically connected with the first interconnection structure (or first metal interconnecting wires 214), and a part of described top layer metallic layer 217 is electrically connected with the second interconnection structure (or second metal interconnecting wires 215).
Described groove 219 exposes Portions of top layer metal level 217, is convenient to the electrical connection of top layer metallic layer 217 and external circuit.
Present invention also offers a kind of LDMOS device, please refer to Fig. 9, comprising:
Silicon substrate 200 in insulation, described silicon-on-insulator substrate 200 comprises the first substrate 11, second substrate 12 and the buried layer 13 between the first substrate 11 and the second substrate 12;
Be positioned at the ldmos transistor on the second substrate 12, described ldmos transistor comprises: the well region being positioned at the second substrate; Be positioned at the grid structure on well region; Be positioned at the drift region 205 of the well region of grid structure side, the doping type of described drift region 205 is contrary with the doping type of well region; Be positioned at the drain region 206 of drift region 20, the degree of depth in drain region 206 is less than the degree of depth of drift region 205, and the doping type in drain region 206 is identical with the doping type of drift region 205; Be positioned at the source region 207 of the well region of grid structure opposite side, the degree of depth in source region 207 is less than the degree of depth of well region, and the doping type in source region 207 is contrary with the doping type of well region;
Cover the first medium layer 208 on described ldmos transistor and the second substrate 12 surface;
Be positioned at the first through hole of the second substrate 12 of first medium layer 208 and segment thickness, described first through hole runs through the thickness in first medium layer 208 and source region 207, and exposes the well region bottom source region 207;
The doping type being positioned at the first doped region 210, doped region 210, first of the well region bottom source region 207 is identical with the doping type of well region;
First metal plug 212, first metal plug 212 of filling full first through hole is electrically connected with source region 207 and the first doped region 210.
In one embodiment, the doping type of described well region and the first doped region 210 is P type, and the doping type in drift region 205, source region 207 and drain region 206 is N-type.
In one embodiment, the doping type of described well region and the first doped region 210 is N-type, and the doping type in drift region 205, source region 207 and drain region 206 is P type.
The ldmos transistor that second substrate 12 of first area 21 is formed can be the ldmos transistor of N-type or the ldmos transistor of P type; The ldmos transistor that second substrate 12 of second area 22 is formed can be the ldmos transistor of N-type or the ldmos transistor of P type.In the particular embodiment, the type of the ldmos transistor described first area 21 formed can be identical or not identical with the type of the ldmos transistor that second area 22 is formed.
The degree of depth of described first through hole is greater than the degree of depth in source region 207, and the width of the first through hole is less than the width in source region 207.
The degree of depth of described first doped region 210 equals the thickness of the second substrate 12, and the width of the first doped region 210 is greater than the width of the first through hole, the bottom of the first doped region 210 and the surface contact of buried layer 13.
The degree of depth of described first doped region 210 is 0.1 ~ 0.5 micron, and in the first doped region 210, the density of foreign ion is 1E14 ~ 1E16atom/cm
2.
Described first metal plug 212 comprises: be positioned at the diffusion impervious layer of the first through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
Also comprise: the second metal plug 213, second metal plug 213 being arranged in first medium layer 208 is electrically connected with drain region 206.
Also comprise: be positioned at the metal interconnecting wires (comprising the first metal interconnecting wires 214 be electrically connected with the first metal plug 212, the second metal interconnecting wires 215 be electrically connected with the second metal plug 213) that first medium layer is electrically connected with the first metal plug 212 and the second metal plug 213 on the surface.
It should be noted that, limit about other of above-mentioned LDMOS device and describe and please refer to definitions relevant and the description of aforementioned LDMOS device forming process part, do not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for LDMOS device, is characterized in that, comprising:
There is provided insulation upper silicon substrate, described silicon-on-insulator substrate comprises the first substrate, the second substrate and the buried layer between the first substrate and the second substrate;
Described second substrate forms ldmos transistor, described ldmos transistor comprises: the well region being positioned at the second substrate, be positioned at source region and the drain region of well region, the degree of depth in source region and drain region is less than the degree of depth of well region, and the doping type in source region and drain region is contrary with the doping type of well region;
Form the first medium layer covering described ldmos transistor and the second substrate surface;
Etch the second substrate of described first medium layer and segment thickness, form the first through hole, described first through hole runs through the thickness in first medium layer and source region, and exposes the well region bottom source region;
Carry out ion implantation along the first through hole, form the first doped region in the well region bottom source region, the doping type of the first doped region is identical with the doping type of well region;
Form first metal plug of filling full first through hole.
2. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, the doping type of described well region and the first doped region is P type, and the doping type in drift region, source region and drain region is N-type.
3. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, the doping type of described well region and the first doped region is N-type, and the doping type in drift region, source region and drain region is P type.
4. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, the degree of depth of described first through hole is greater than the degree of depth in source region, and the width of the first through hole is less than the width in source region.
5. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, the described bottom of the first doped region and the surface contact of buried layer, the width of the first doped region is greater than the width of the first through hole.
6. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, the injection degree of depth of described ion implantation equals the thickness of the second substrate.
7. the formation method of LDMOS device as claimed in claim 1, is characterized in that, the degree of depth that described ion implantation is injected is 0.1 ~ 0.5 micron, and dosage is 1E14 ~ 1E16atom/cm
2, angle is 0 ~ 10 degree.
8. the formation method of LDMOS device as claimed in claim 7, is characterized in that, after carrying out ion implantation, carry out annealing process.
9. the formation method of LDMOS device as claimed in claim 1, it is characterized in that, described first metal plug comprises: be positioned at the diffusion impervious layer of the first through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
10. the formation method of LDMOS device as claimed in claim 1, is characterized in that, also comprise: etch described first medium layer, form the second through hole in first medium layer, described second through hole exposes the surface in drain region.
The formation method of 11. LDMOS device as claimed in claim 10, is characterized in that, forms second metal plug of filling full second through hole; Form the metal interconnecting wires be electrically connected with the first metal plug and the second metal plug.
The formation method of 12. LDMOS device as claimed in claim 1, it is characterized in that, described ldmos transistor comprises: the well region being positioned at the second substrate; Be positioned at the grid structure on well region; Be positioned at the drift region of the well region of grid structure side, the doping type of described drift region is contrary with the doping type of well region; Be positioned at the drain region of drift region, the degree of depth in drain region is less than the degree of depth of drift region, and the doping type in drain region is identical with the doping type of drift region; Be positioned at the source region of the well region of grid structure opposite side, the degree of depth in source region is less than the degree of depth of well region, and the doping type in source region is contrary with the doping type of well region.
13. 1 kinds of LDMOS device, is characterized in that, comprising:
Silicon substrate in insulation, described silicon-on-insulator substrate comprises the first substrate, the second substrate and the buried layer between the first substrate and the second substrate;
Be positioned at the ldmos transistor on the second substrate, described ldmos transistor comprises: the well region being positioned at the second substrate, be positioned at source region and the drain region of well region, the degree of depth in source region and drain region is less than the degree of depth of well region, and the doping type in source region and drain region is contrary with the doping type of well region;
Cover the first medium layer of described ldmos transistor and the second substrate surface;
Be positioned at the first through hole of the second substrate of first medium layer and segment thickness, described first through hole runs through the thickness in first medium layer and source region, and exposes the well region bottom source region;
Be positioned at the first doped region of the well region bottom source region, the doping type of the first doped region is identical with the doping type of well region;
Fill the first metal plug of full first through hole, the first metal plug is electrically connected with source region and the first doped region.
14. LDMOS device as claimed in claim 13, is characterized in that, the doping type of described well region and the first doped region is P type, and the doping type in drift region, source region and drain region is N-type.
15. LDMOS device as claimed in claim 13, is characterized in that, the doping type of described well region and the first doped region is N-type, and the doping type in drift region, source region and drain region is P type.
16. LDMOS device as claimed in claim 13, is characterized in that, the degree of depth of described first through hole is greater than the degree of depth in source region, and the width of the first through hole is less than the width in source region.
17. LDMOS device as claimed in claim 13, is characterized in that, the degree of depth of described first doped region equals the thickness of the second substrate, and the width of the first doped region is greater than the width of the first through hole, the described bottom of the first doped region and the surface contact of buried layer.
18. LDMOS device as claimed in claim 13, it is characterized in that, described first metal plug comprises: be positioned at the diffusion impervious layer of the first through-hole side wall and bottom, be positioned at the metal level that full through hole is filled on diffusion impervious layer surface.
19. LDMOS device as claimed in claim 13, it is characterized in that, also comprise: the second metal plug being arranged in first medium layer, the second metal plug is electrically connected with drain region; Be positioned at the metal interconnecting wires that first medium layer is electrically connected with the first metal plug and the second metal plug on the surface.
20. LDMOS device as claimed in claim 13, it is characterized in that, described ldmos transistor comprises: the well region being positioned at the second substrate; Be positioned at the grid structure on well region; Be positioned at the drift region of the well region of grid structure side, the doping type of described drift region is contrary with the doping type of well region; Be positioned at the drain region of drift region, the degree of depth in drain region is less than the degree of depth of drift region, and the doping type in drain region is identical with the doping type of drift region; Be positioned at the source region of the well region of grid structure opposite side, the degree of depth in source region is less than the degree of depth of well region, and the doping type in source region is contrary with the doping type of well region.
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|---|---|---|---|
| CN201410381682.5A CN105405879B (en) | 2014-08-05 | LDMOS device and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410381682.5A CN105405879B (en) | 2014-08-05 | LDMOS device and forming method thereof |
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| CN105405879B CN105405879B (en) | 2018-06-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166820A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device and semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020053695A1 (en) * | 2000-11-07 | 2002-05-09 | Chorng-Wei Liaw | Split buried layer for high voltage LDMOS transistor |
| US20130134598A1 (en) * | 2008-05-15 | 2013-05-30 | Great Wall Semiconductor Corporation | Semiconductor Device and Method of Forming a Power MOSFET With Interconnect Structure to Achieve Lower RDSON |
| CN103545372A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | FinFET with trench field plate |
| CN103839999A (en) * | 2012-11-27 | 2014-06-04 | 深圳市力振半导体有限公司 | Structure and preparation method of power field effect transistor |
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020053695A1 (en) * | 2000-11-07 | 2002-05-09 | Chorng-Wei Liaw | Split buried layer for high voltage LDMOS transistor |
| US20130134598A1 (en) * | 2008-05-15 | 2013-05-30 | Great Wall Semiconductor Corporation | Semiconductor Device and Method of Forming a Power MOSFET With Interconnect Structure to Achieve Lower RDSON |
| CN103545372A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | FinFET with trench field plate |
| CN103839999A (en) * | 2012-11-27 | 2014-06-04 | 深圳市力振半导体有限公司 | Structure and preparation method of power field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166820A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device and semiconductor devices |
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