CN108269861B - MOS capacitor and forming method thereof - Google Patents
MOS capacitor and forming method thereof Download PDFInfo
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- CN108269861B CN108269861B CN201611264809.0A CN201611264809A CN108269861B CN 108269861 B CN108269861 B CN 108269861B CN 201611264809 A CN201611264809 A CN 201611264809A CN 108269861 B CN108269861 B CN 108269861B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 150000002500 ions Chemical class 0.000 claims description 57
- -1 phosphorus ions Chemical class 0.000 claims description 27
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
Abstract
The invention provides an MOS capacitor and a forming method thereof, wherein the MOS capacitor comprises: a substrate including a device region and a protection region adjacent to each other; a gate structure located on the device region substrate; source-drain doped regions in the device region substrate at two sides of the gate structure; a dummy gate structure on the protection region substrate; and the conductive structure is used for connecting the source drain doped region and the dummy gate structure. The MOS capacitor comprises a conductive structure which is connected with the pseudo grid structure and the source drain doped region, the potential on the pseudo grid structure is stable, when the external environment changes, the potential on the pseudo grid structure is not easy to change, and the voltage between the pseudo grid structure and the substrate is not easy to change, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the MOS capacitor performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a Metal Oxide Semiconductor (MOS) capacitor and a forming method thereof.
Background
With the development of mobile communication technology, the research on Radio Frequency (RF) circuits has attracted considerable attention. Implementing a Voltage Controlled Oscillator (VCO) using standard CMOS processes is key to implementing a radio frequency CMOS integrated transceiver. Most of the prior voltage-controlled oscillator circuits adopt a reverse-biased varactor diode as a voltage-controlled device, however, when the circuits are realized by using an actual process, the quality factor of the varactor diode is usually very small, which affects the performance of the circuits. Therefore, instead of the conventional varactor, other devices that can be implemented by CMOS process are tried, and MOS capacitors are produced accordingly.
Shorting the drain and source of the MOS transistor and shorting the source and drain to the substrate can be a simple MOS capacitor whose capacitance varies with the voltage between the gate and the substrate. In the PMOS capacitor, an inversion carrier channel is established when the voltage between the grid and the substrate is greater than a threshold voltage absolute value, and when the voltage between the grid and the substrate is far greater than the threshold voltage absolute value, the PMOS capacitor works in a strong inversion region. On the other hand, when the gate voltage is greater than the substrate voltage, the PMOS capacitor operates in the accumulation region, where the interface voltage between the gate oxide layer and the semiconductor is positive and electrons are allowed to move freely.
In order to reduce the influence of external environment change on the MOS capacitor, dummy gate structures are often formed on two sides of the MOS capacitor, so as to achieve isolation between the MOS capacitor and the external environment.
However, the conventional MOS capacitor is still susceptible to the external environment, which makes the performance of the MOS capacitor poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of an MOS capacitor.
To solve the above problems, the present invention provides a MOS capacitor, including: a substrate including a device region and a protection region adjacent to each other; a gate structure located on the device region substrate; source-drain doped regions in the device region substrate at two sides of the gate structure; a dummy gate structure on the protection region substrate; and the conductive structure is used for connecting the source drain doped region and the dummy gate structure.
Optionally, the device further includes a well region located in the device region substrate, and the gate structure is located on the well region; the well region is provided with trap ions, the source and drain doped region is provided with doped ions, and the conductive types of the doped ions and the trap ions are the same or different.
Optionally, the trap ions and the doped ions are phosphorus ions, arsenic ions, boron ions or BF 2-ions.
Optionally, the source and drain regions at two sides of the gate structure are electrically connected to each other.
Optionally, the conductive structure includes: the source-drain plug is connected with the source-drain doped region, the dummy gate plug is connected with the dummy gate structure, and the connecting line is connected with the dummy gate structure and the source-drain plug.
Optionally, the connecting wire is made of aluminum or copper-aluminum alloy.
Optionally, the dummy gate plug is made of copper or aluminum.
Optionally, the source-drain plugs respectively connected to the source-drain doped regions on both sides of the gate structure are electrically connected through the connecting line.
Optionally, the method further includes: and the grid plug is connected with the grid structure.
Correspondingly, the invention also provides a method for forming the MOS capacitor, which comprises the following steps: providing a substrate, wherein the substrate comprises a device region and a protection region which are adjacent to each other; forming a grid structure on the substrate of the device region; forming a pseudo gate structure on the protection region substrate; forming source and drain doped regions in the device region substrate on two sides of the grid structure; and forming a conductive structure for connecting the source drain doped region and the dummy gate structure.
Optionally, the conductive structure includes: the source-drain plug is connected with the source-drain doped region, the pseudo grid plug is connected with the pseudo grid structure, and the connecting line is connected with the pseudo grid structure and the source-drain plug; the step of forming the conductive structure comprises: forming dielectric layers on the device region substrate and the protection region substrate; forming contact holes in the device region and the protective region dielectric layer respectively, wherein the device region contact hole exposes the source-drain doped region, and the protective region contact hole exposes the top surface of the pseudo gate structure; forming source and drain plugs in the contact holes of the device region; forming a dummy gate plug in the protection region contact hole; and forming a connecting line on the dielectric layer, wherein the connecting line is connected with the source-drain doped plug and the dummy gate plug.
Optionally, the source-drain plugs respectively connected to the source-drain doped regions on both sides of the gate structure are electrically connected through the connecting line.
Optionally, the method further includes: and forming a gate plug connected with the gate structure.
Optionally, before forming the gate structure, the method further includes: and carrying out ion implantation on the device area substrate, and forming a well region in the device area substrate.
Optionally, the well region has trap ions therein, and the source-drain doped region has doping ions therein, where the doping ions and the trap ions have the same or different conductivity types.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the MOS capacitor provided by the technical scheme of the present invention, the MOS capacitor includes a conductive structure connecting the dummy gate structure and the source-drain doped region, and the dummy gate structure is electrically connected to the source-drain doped region. In the use process of the MOS capacitor, when a potential is applied to the source drain doped region, the same potential is also applied to the dummy gate structure, and the potential on the dummy gate structure is a stable potential. When the external environment changes, for example, when the resistance of the dummy gate structure changes due to changes in external humidity and temperature, or when the effect of an electric field formed by an external circuit on charges on the dummy gate structure changes, the potential on the dummy gate structure is not easily changed, and the voltage between the dummy gate structure and the substrate can be a constant value. Therefore, the potential of the substrate is not easy to change due to the change of the external environment, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor is improved.
In the method for forming the MOS capacitor provided by the technical scheme of the invention, the conductive structure for connecting the pseudo gate structure and the source-drain doped region is formed, so that the pseudo gate structure is electrically connected with the source-drain doped region. In the use process of the MOS capacitor, when a potential is applied to the source-drain doped region, the same potential is also applied to the dummy gate structure. And the potential on the dummy gate structure is a stable potential. When the external environment changes, for example, when the resistance of the dummy gate structure changes due to changes in external humidity and temperature, or when the effect of an electric field formed by an external circuit on charges on the dummy gate structure changes, the potential on the dummy gate structure is not easily changed, and the voltage between the dummy gate structure and the substrate can be a constant value. Therefore, the potential of the substrate is not easy to change due to the change of the external environment, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor is improved.
Drawings
FIGS. 1 and 2 are schematic structural diagrams of a MOS capacitor;
fig. 3 to fig. 10 are schematic structural diagrams of steps of a method for forming a MOS capacitor according to an embodiment of the invention.
Detailed Description
The conventional semiconductor structure has many problems, such as: MOS capacitors have poor performance.
The reason for the poor performance of the MOS capacitor is analyzed below with reference to the drawings.
Fig. 1 and 2 are schematic structural diagrams of a MOS capacitor.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view taken along a cutting line 11-12 in fig. 1, the MOS capacitor includes: the semiconductor device comprises a substrate 100, wherein the substrate 100 comprises a device region A and a protection region B which are adjacent to each other, and fins 101 are arranged on the device region A and the protection region B of the substrate 100; an isolation structure 102 on the substrate 100, wherein a surface of the isolation structure 102 is lower than a top surface of the fin 101; a gate structure 110 spanning the device region a fin 101, wherein the gate structure 110 covers part of the sidewall and the top surface of the device region a fin 101; the dummy gate structure 111 crosses the protection region B fin 101, and the dummy gate structure 111 covers part of the side wall and the top surface of the protection region B fin 101; a source region 121 and a drain region 122 respectively located in the fins 101 on both sides of the gate structure 110; a conductive structure 132 connecting the source region 121 and the drain region 122.
Before forming the conductive structure 132, a dielectric layer 140 (not shown in fig. 1) covering the source region 121, the drain region 122 and the gate structure 110 needs to be formed, and the dielectric layer 140 is planarized. In the planarization process, the dummy gate structure 110 can support the dielectric layer 140, so as to reduce the recess in the dielectric layer 140 and improve the insulation of the dielectric layer 140.
However, since the dummy gate structure 111 is floating, the potential generated on the dummy gate structure 111 is unstable. For example, the change of humidity, temperature, etc. of the external environment easily causes the change of resistance of the dummy gate structure 111, thereby causing the change of the potential on the dummy gate structure 111; alternatively, a change in the electric field formed by an external circuit easily causes a change in the amount of charge on the dummy gate structure, thereby causing a change in the potential on the dummy gate structure 111. The unstable potential on the dummy gate structure 111 easily affects the potential of the substrate 100, and thus affects the voltage between the substrate 100 and the gate structure 111, and further affects the capacitance between the gate structure 110 and the substrate 100.
In order to solve the technical problem, the present invention provides a MOS capacitor, including: a substrate including a device region and a protection region adjacent to each other; a gate structure located on the device region substrate; source-drain doped regions in the device region substrate at two sides of the gate structure; a dummy gate structure on the protection region substrate; and the conductive structure is used for connecting the source drain doped region and the dummy gate structure.
The MOS capacitor comprises a conductive structure which is connected with the dummy gate structure and the source-drain doped region, and the dummy gate structure is electrically connected with the source-drain doped region. In the use process of the MOS capacitor, when a potential is applied to the source drain doped region, the same potential is also applied to the dummy gate structure, and the potential on the dummy gate structure is a stable potential. When the external environment changes, for example, when the resistance of the dummy gate structure changes due to changes in external humidity and temperature, or when the effect of an electric field formed by an external circuit on charges on the dummy gate structure changes, the potential on the dummy gate structure is not easily changed, and the voltage between the dummy gate structure and the substrate can be a constant value. Therefore, the potential of the substrate is not easy to change due to the change of the external environment, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to fig. 10 are schematic structural diagrams of steps of a method for forming a MOS capacitor according to an embodiment of the invention.
Referring to fig. 3, a substrate is provided, the substrate including a device region I and a protection region II.
The device region I is used for forming a semiconductor device, and the protection region II is used for forming a pseudo gate structure subsequently.
In this embodiment, the substrate includes: a substrate 200 and a fin 201 on the substrate 200 in the device region I and the protection region II. In other embodiments, the substrate may also be a planar substrate.
In this embodiment, the protection region II is located on both sides of the device region I.
In this embodiment, the substrate 200 and the fin 201 are made of silicon. In other embodiments, the substrate and the fin portion are made of germanium or silicon germanium, and the substrate may also be a semiconductor substrate such as silicon-on-insulator or germanium-on-insulator.
In this embodiment, the forming method further includes: an isolation structure 202 is formed on the substrate 200, wherein the isolation structure 202 covers a portion of the sidewall of the fin 201, and the surface of the isolation structure 202 is lower than the top surface of the fin 202.
In this embodiment, the isolation structure 202 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
In this embodiment, after forming the isolation structure 202, the method further includes: well regions are formed in the device region I substrate, the well regions having well ions therein.
In this embodiment, the well region is further located in the protection region II substrate. Specifically, the well region is located in the device region I and the protection region II fin portion 201.
In this embodiment, the step of forming the well region includes: ion implantation is performed on the fin portion 201, and trap ions are implanted into the fin portion 201.
In this embodiment, the trap ions are N-type ions, such as phosphorous ions or arsenic ions. In other embodiments, the trap ions may also be P-type ions, such as boron ions or BF2-Ions.
Referring to fig. 4, a gate structure 210 is formed on the device region I substrate; and forming a dummy gate structure 211 on the protection region II substrate.
In this embodiment, the gate structure 210 crosses over the device region I fin 201, and the gate structure 210 is located on a portion of the sidewall and the top surface of the fin 201.
In this embodiment, the dummy gate structure 211 crosses over the protection region II fin 201, and the dummy gate structure 211 is located on a portion of the sidewall and the top surface of the fin 201.
In this embodiment, the step of forming the gate structure 210 and the dummy gate structure 211 includes: forming a gate dielectric layer covering the side walls and the top surfaces of the fin portions 201 in the device region I and the protection region II; forming a gate electrode layer on the gate dielectric layer; and patterning the gate dielectric layer and the gate electrode layer to form the gate structure 210 and the dummy gate structure 211.
In this embodiment, the gate dielectric layer is made of silicon oxide. In other embodiments, the material of the gate dielectric layer may also be a high-k (dielectric constant greater than 3.9) dielectric material.
In this embodiment, the gate is made of polysilicon. In other embodiments, the material of the gate may also be metal, for example: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
In this embodiment, the step of forming the gate structure 210 and the dummy gate structure 211 further includes: in the process of forming the gate layer, the gate layer is subjected to in-situ doping, and gate doping ions are doped into the gate layer.
Specifically, in this embodiment, the gate doping ions are N-type ions, such as phosphorus ions or arsenic ions, and in other embodiments, the gate doping ions are also P-type ions, which include: boron ions or BF2-Ions.
Referring to fig. 5, a source-drain doped region 220 is formed in the device region I substrate on both sides of the gate structure 210.
The source-drain doped regions 220 on both sides of the gate structure 210 are electrically connected to each other.
In this embodiment, the source-drain doped region 220 is located in the substrate between the gate structure 210 and the dummy gate structure 211.
In this embodiment, the source/drain doped region 220 is made of silicon germanium. In other embodiments, the source-drain doped region may also be made of silicon carbon or silicon.
In this embodiment, the process of forming the source/drain doped region 220 includes an epitaxial growth process.
In this embodiment, in the process of forming the source/drain doped region 220 through the epitaxial growth process, the source/drain doped region 220 is doped through an in-situ doping process, and doped ions are doped in the source/drain doped region 220.
In this embodiment, the conductivity type of the doped ions is the same as that of the trap ions. In other embodiments, the conductivity type of the dopant ions may also be different from the conductivity type of the trap ions.
In this embodiment, the doping ions are N-type ions, such as phosphorous ions or arsenic ions. In other embodiments, the source-drain doped region is made of silicon or carbon-silicon, and the dopant ions may also be P-type ions, such as boron ions or BF2-Ions.
And forming a conductive structure for connecting the source-drain doped region 220 and the dummy gate structure 211.
In this embodiment, the conductive structure includes: the source-drain plug is connected with the source-drain doped region 220, the dummy gate plug is connected with the dummy gate structure 211, and the dummy gate plug is connected with a connecting line of the source-drain plug. Specifically, the steps of forming the conductive structure are shown in fig. 6 to 10.
Referring to fig. 6, a dielectric layer 230 is formed on the device region I substrate and the protection region II substrate.
The dielectric layer 230 is used to achieve isolation between different conductive structures.
In this embodiment, the dielectric layer 230 is made of silicon oxide. In other embodiments, the material of the dielectric layer may also be silicon oxynitride or silicon nitride.
In this embodiment, the process of forming the dielectric layer 230 includes a fluid chemical vapor deposition process.
Referring to fig. 7, a source-drain contact hole 203 is formed in the device region I dielectric layer 230, the source-drain contact hole 203 exposes the source-drain doped region 220, a dummy gate contact hole 204 is formed in the protection region II dielectric layer 203, and the dummy gate contact hole 204 exposes the top surface of the dummy gate structure 211.
The source-drain contact hole 203 and the dummy gate contact hole 204 are used for respectively accommodating a source-drain plug and a dummy gate plug in a subsequent process.
In this embodiment, the process of forming the source-drain contact hole 203 and the dummy gate contact hole 204 includes a dry etching process.
In this embodiment, the method for forming the conductive structure further includes: a gate contact hole (not shown) is formed in the device region I dielectric layer 230.
Referring to fig. 8 and 9, fig. 9 is a cross-sectional view along the cutting line 23-24 in fig. 8, in which the dielectric layer 230 is omitted in fig. 8, and source drain plugs 231 are formed in the source drain contact holes 203; a dummy gate plug 232 is formed in the dummy gate contact hole 204.
The source-drain plug 231 is used for realizing the electrical connection between the source-drain doped region 220 and an external circuit; the dummy gate plug 232 is used to electrically connect the dummy gate structure 211 and the source/drain doped region 220.
In this embodiment, the source-drain plug 231 and the dummy gate plug 232 are made of tungsten. In other embodiments, the source-drain plug and the dummy gate plug may also be made of copper.
In this embodiment, the process of forming the source-drain plug 231 and the dummy gate plug 232 includes: chemical vapor deposition process, physical vapor deposition process or electrochemical plating process.
In this embodiment, the forming method further includes: forming a gate plug 233 connected to the gate structure 210, wherein the gate plug 233 penetrates through the dielectric layer 230.
The gate plug 233 is used to electrically connect the gate structure 210 to an external circuit.
In this embodiment, the gate plug 233 is made of tungsten. In other embodiments, the material of the gate plug may also be copper.
Referring to fig. 10, a connection line 240 is formed on the dielectric layer 230, and the connection line 240 connects the source-drain plug 231 and the dummy gate plug 232.
The connecting line 240 connects the source-drain plug 231 and the dummy gate plug 232, so that the dummy gate structure 211 is electrically connected to the source-drain doped region 220. In the use process of the MOS capacitor, when a potential is applied to the source-drain doped region 220, the same potential is also applied to the dummy gate structure 211, and the potential on the dummy gate plug 232 is a stable potential. When the external environment changes, for example, when the external humidity and temperature change to cause the resistance of the dummy gate structure 211 to change, or when the electric field formed by the external circuit changes the effect of the electric charge on the dummy gate structure, the potential on the dummy gate structure 211 is not easy to change, so that the voltage between the dummy gate structure 211 and the substrate is a constant value, therefore, the potential of the substrate is not easy to change due to the change of the external environment, the capacitance between the gate structure 210 and the substrate is not easy to be affected, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor can be improved.
In this embodiment, the source-drain plugs 231 respectively connected to the source-drain doped regions 220 on both sides of the gate structure 210 are electrically connected through the connection line 240.
In this embodiment, the connecting wire 240 is made of aluminum, and in other embodiments, the connecting wire may also be made of copper or copper-aluminum alloy.
In this embodiment, the process of forming the connection line 240 includes: chemical vapor deposition process. In other embodiments, the process of forming the connection line may further include a physical vapor deposition process or an electrochemical plating process.
In summary, in the method for forming the MOS capacitor according to the embodiment of the present invention, the MOS capacitor includes a conductive structure connecting the dummy gate structure and the source-drain doped region, and the dummy gate structure is electrically connected to the source-drain doped region. In the use process of the MOS capacitor, when a potential is applied to the source drain doped region, the same potential is also applied to the dummy gate structure, and the potential on the dummy gate structure is a stable potential. When the external environment changes, for example, when the resistance of the dummy gate structure changes due to changes in external humidity and temperature, or when the effect of an electric field formed by an external circuit on charges on the dummy gate structure changes, the potential on the dummy gate structure is not easily changed, and the voltage between the dummy gate structure and the substrate can be a constant value. Therefore, the potential of the substrate is not easy to change due to the change of the external environment, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor is improved.
With continued reference to fig. 10, an embodiment of the present invention further provides a MOS capacitor, including: the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a device region I and a protection region II which are adjacent to each other; a gate structure 210 located on the device region I substrate; a source-drain doped region 220 located in the device region I substrate at two sides of the gate structure 210; a dummy gate structure 211 on the protection region II substrate; and a conductive structure connecting the source-drain doped region 220 and the dummy gate structure 211.
The device region I is used to form a semiconductor device, and the protection region II is used to form a dummy gate structure 211.
In this embodiment, the substrate includes: a substrate 200 and a fin 201 on the substrate 200 in the device region I and the protection region II. In other embodiments, the substrate may also be a planar substrate.
In this embodiment, the protection region II is located on both sides of the device region I.
In this embodiment, the substrate 200 and the fin 201 are made of silicon. In other embodiments, the substrate and the fin portion are made of germanium or silicon germanium, and the substrate may also be a semiconductor substrate such as silicon-on-insulator or germanium-on-insulator.
In this embodiment, the MOS capacitor further includes: and an isolation structure 202 located on the substrate 200, wherein the isolation structure 202 covers a portion of the sidewall of the fin 201, and a surface of the isolation structure 202 is lower than a top surface of the fin 202.
In this embodiment, the isolation structure 202 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon nitride.
In this embodiment, the MOS capacitor further includes a well region located in the device region I substrate, and the well region has well ions therein.
In this embodiment, the well region is further located in the protection region II substrate. Specifically, the well region is located in the device region I and the protection region II fin portion 201.
In this embodiment, the trap ions are N-type ions, such as phosphorous ions or arsenic ions. In other embodiments, the trap ions may also be P-type ions, such as boron ions or BF2-Ions.
In this embodiment, the gate structure 210 crosses over the device region I fin 201, and the gate structure 210 is located on a portion of the sidewall and the top surface of the fin 201.
In this embodiment, the dummy gate structure 211 crosses over the protection region II fin 201, and the dummy gate structure 210 is located on a portion of the sidewall and the top surface of the fin 201.
Specifically, in this embodiment, the gate doping ions are N-type ions, such as phosphorus ions or arsenic ions, and in other embodiments, the gate doping ions are also P-type ions, which include: boron ions or BF2-Ions.
In this embodiment, the source-drain doped region 220 is located in the substrate between the gate structure 210 and the dummy gate structure 211.
In this embodiment, the source/drain doped region 220 is made of silicon germanium. In other embodiments, the source-drain doped region may also be made of silicon carbon or silicon.
In this embodiment, the source/drain doped region 220 has doped ions therein. The dopant ions are of the same conductivity type as the trap ions. In other embodiments, the conductivity type of the dopant ions may also be different from the conductivity type of the trap ions.
In this embodiment, the dopant ions are N-type ions, for examplePhosphorus ions or arsenic ions. In other embodiments, the source-drain doped region is made of silicon or carbon-silicon, and the dopant ions may also be P-type ions, such as boron ions or BF2-Ions.
In this embodiment, the conductive structure includes: the source-drain plug 231 connected with the source-drain doped region 220, the dummy gate plug 232 connected with the dummy gate structure 211, and a connection line connecting the dummy gate plug 232 and the source-drain plug 231.
In this embodiment, the semiconductor structure further includes: and a dielectric layer 230 positioned on the device region I substrate and the protection region II substrate.
In this embodiment, the MOS capacitor further includes: a gate plug (not shown) connected to the gate structure 210, wherein the gate plug 233 penetrates the dielectric layer 230.
The gate plug 233 is used to electrically connect the gate structure 210 to an external circuit.
The source-drain plug 231 and the dummy gate plug 232 are located in the dielectric layer 230, and the connection line 240 is located on the dielectric layer 230.
The source-drain plug 231 is used for realizing the electrical connection between the source-drain doped region 220 and an external circuit; the dummy gate plug 232 is used to electrically connect the dummy gate structure 211 and the source/drain doped region 220.
In this embodiment, the source-drain plug 231 and the dummy gate plug 232 are made of tungsten. In other embodiments, the source-drain plug and the dummy gate plug may also be made of copper.
The connecting line 240 connects the source-drain plug 231 and the dummy gate plug 232, so that the dummy gate structure 211 is electrically connected to the source-drain doped region 220. In the use process of the MOS capacitor, when a potential is applied to the source-drain doped region 220, the same potential is also applied to the dummy gate structure 211, and the potential on the dummy gate structure 211 is a stable potential. When the external environment changes, for example, when the external humidity and temperature change to cause the resistance of the dummy gate structure 211 to change, or when the electric field formed by the external circuit changes the effect of the electric charge on the dummy gate structure 211, the potential on the dummy gate structure 211 is not easy to change, so that the voltage between the dummy gate structure 211 and the substrate is a constant value, therefore, the potential of the substrate is not easy to change due to the change of the external environment, the capacitance between the gate structure 210 and the substrate is not easy to be affected, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor can be improved.
And the source and drain regions at two sides of the grid structure are mutually and electrically connected. In this embodiment, the source-drain plugs respectively connected to the source-drain doped regions on both sides of the gate structure are electrically connected through the connection line.
In this embodiment, the connecting wire 240 is made of aluminum, and in other embodiments, the connecting wire may also be made of copper or copper aluminum.
In summary, in the MOS capacitor provided in the embodiment of the present invention, a conductive structure is formed to connect the dummy gate structure and the source-drain doped region, and the dummy gate structure is electrically connected to the source-drain doped region. In the use process of the MOS capacitor, when a potential is applied to the source-drain doped region, the same potential is also applied to the dummy gate structure. And the potential on the dummy gate structure is a stable potential. When the external environment changes, for example, when the resistance of the dummy gate structure changes due to changes in external humidity and temperature, or when the effect of an electric field formed by an external circuit on charges on the dummy gate structure changes, the potential on the dummy gate structure is not easily changed, and the voltage between the dummy gate structure and the substrate can be a constant value. Therefore, the potential of the substrate is not easy to change due to the change of the external environment, so that the capacitance between the grid structure and the substrate is not easy to influence, the precision of the capacitance value of the MOS capacitor can be ensured, and the performance of the MOS capacitor is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A MOS capacitor, comprising:
a substrate including a device region and a protection region adjacent to each other;
a gate structure located on the device region substrate;
source-drain doped regions in the device region substrate at two sides of the gate structure;
a dummy gate structure on the protection region substrate; the dummy gate structure crosses the fin part of the protection region, and is positioned on the partial side wall and the top surface of the fin part;
the conductive structure is used for connecting the source drain doped region and the dummy gate structure;
applying a potential to the source-drain doped region, applying the same potential to the dummy gate structure, wherein the potential on the dummy gate structure is a stable potential, and further the voltage between the dummy gate structure and the substrate is a constant value;
the MOS capacitor further comprises: the grid plug is positioned in the well region in the substrate of the device region or connected with the grid structure; when the MOS capacitor comprises the well region, the gate structure is positioned on the well region;
the well region is provided with well ions, the source drain doped region is provided with doped ions, and the well ions and the doped ions are phosphorus ions, arsenic ions, boron ions or BF2-Ions.
2. The MOS capacitor of claim 1, wherein the source and drain regions on either side of the gate structure are electrically connected to each other.
3. The MOS capacitor of claim 1, wherein the conductive structure comprises: the source-drain plug is connected with the source-drain doped region, the dummy gate plug is connected with the dummy gate structure, and the connecting line is connected with the dummy gate structure and the source-drain plug.
4. The MOS capacitor as claimed in claim 3, wherein the material of the connecting line is aluminum or copper-aluminum alloy.
5. The MOS capacitor of claim 3, wherein the dummy gate plug is made of copper or aluminum.
6. The MOS capacitor according to claim 3, wherein the source-drain plugs respectively connected to the source-drain doped regions at both sides of the gate structure are electrically connected through the connection line.
7. A method for forming a MOS capacitor is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a device region and a protection region which are adjacent to each other;
forming a grid structure on the substrate of the device region;
forming a pseudo gate structure on the protection region substrate; the dummy gate structure crosses the fin part of the protection region, and is positioned on the partial side wall and the top surface of the fin part;
forming source and drain doped regions in the device region substrate on two sides of the grid structure;
forming a conductive structure connecting the source drain doped region and the dummy gate structure;
applying a potential to the source-drain doped region, applying the same potential to the dummy gate structure, wherein the potential on the dummy gate structure is a stable potential, and further the voltage between the dummy gate structure and the substrate is a constant value;
the method further comprises the following steps: forming a gate plug connected with the gate structure; alternatively, the method further comprises: before forming a grid structure, carrying out ion implantation on the device region substrate, and forming a well region in the device region substrate;
the well region is provided with well ions, the source drain doped region is provided with doped ions, and the well ions and the doped ions are phosphorus ions, arsenic ions, boron ions or BF2-Ions.
8. The method of claim 7, wherein the conductive structure comprises: the source-drain plug is connected with the source-drain doped region, the pseudo grid plug is connected with the pseudo grid structure, and the connecting line is connected with the pseudo grid structure and the source-drain plug;
the step of forming the conductive structure comprises: forming dielectric layers on the device region substrate and the protection region substrate; forming contact holes in the device region and the protective region dielectric layer respectively, wherein the device region contact hole exposes the source-drain doped region, and the protective region contact hole exposes the top surface of the pseudo gate structure; forming source and drain plugs in the contact holes of the device region; forming a dummy gate plug in the protection region contact hole; and forming a connecting line on the dielectric layer, wherein the connecting line is connected with the source-drain doped plug and the dummy gate plug.
9. The method for forming a MOS capacitor according to claim 8, wherein the source-drain plugs respectively connected to the source-drain doped regions on both sides of the gate structure are electrically connected through the connection line.
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