CN108269861A - Mos capacitance and forming method thereof - Google Patents
Mos capacitance and forming method thereof Download PDFInfo
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- CN108269861A CN108269861A CN201611264809.0A CN201611264809A CN108269861A CN 108269861 A CN108269861 A CN 108269861A CN 201611264809 A CN201611264809 A CN 201611264809A CN 108269861 A CN108269861 A CN 108269861A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 112
- 150000002500 ions Chemical class 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 37
- -1 phosphonium ion Chemical class 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000012071 phase Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003319 supportive effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of mos capacitance and forming method thereof, wherein, mos capacitance includes：Substrate, the substrate include the device region to adjoin each other and protection zone；Gate structure on the device region substrate；Source and drain doping area in the gate structure both sides device region substrate；Dummy gate structure on the protection zone substrate；Connect the conductive structure in the source and drain doping area and the dummy gate structure.The mos capacitance includes connecting the dummy gate structure and the conductive structure in the source and drain doping area, then the current potential in the dummy gate structure is stable potential, when external environment changes, current potential in dummy gate structure is less likely to occur to change, voltage between dummy gate structure and substrate is less likely to occur to change, so as to be not easy to influence the capacitance between gate structure and substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of mos capacitance and forming method thereof.
Background technology
With the development of mobile communication technology, the research of radio frequency (RF) circuit causes extensive attention.Using standard
CMOS technology realizes voltage controlled oscillator (VCO), is the key that realize that RF CMOS integrates transceiver.Passing voltage controlled oscillator electricity
Road uses the varactor of reverse biased as voltage-controlled device mostly, however when realizing circuit with actual process, it is found that
The quality factor of varactor usually all very little, this performance that will influence circuit.Then, people just attempt using it is other can
General varactor is replaced with the device realized with CMOS technology, mos capacitance just comes into being.
It can become a simple MOS electricity with substrate short circuit by the leakage of MOS transistor and source short circuit, and by source and leakage
Hold, capacitance changes with the voltage change between grid and substrate.In PMOS capacitances, inversion carriers raceway groove is in grid
Voltage between substrate is more than threshold voltage to the greatest extent to being established during value, when the voltage between grid and substrate is far longer than threshold value electricity
When pressure is to the greatest extent to value, PMOS capacitances are operated in strong inversion region.On the other hand, when grid voltage is more than underlayer voltage, PMOS electricity
Appearance is operated in accumulation area, and the phase boundary potential between gate oxide and semiconductor is just and can move freely electronics at this time.
Change influence to mos capacitance to reduce external environment, often form dummy gate structure in mos capacitance both sides,
Realize being isolated between mos capacitance and external environment.
However, existing mos capacitance is still easily influenced by external environment, make the poor-performing of mos capacitance.
Invention content
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, the property of mos capacitance can be improved
Energy.
To solve the above problems, the present invention provides a kind of mos capacitance, including：Substrate, the substrate include what is adjoined each other
Device region and protection zone；Gate structure on the device region substrate；Positioned at the gate structure both sides device region substrate
In source and drain doping area；Dummy gate structure on the protection zone substrate；Connect the source and drain doping area and the pseudo- grid
The conductive structure of pole structure.
Optionally, the well region in the device region substrate is further included, the gate structure is located on the well region；Institute
Stating has trap ion in well region, have Doped ions in the source and drain doping area, the Doped ions are led with the trap ion
Electric type is identical or differs.
Optionally, the trap ion and Doped ions are phosphonium ion, arsenic ion, boron ion or BF2- ions.
Optionally, the source-drain area of the gate structure both sides is electrically connected to each other.
Optionally, the conductive structure includes：The source and drain plug in the source and drain doping area is connected, connects the dummy grid knot
The dummy grid plug of structure connects the connecting line of the dummy gate structure and the source and drain plug.
Optionally, the material of the connecting line is aluminium or albronze.
Optionally, the material of the dummy grid plug is copper or aluminium.
Optionally, the source and drain plug for connecting the source and drain doping area of the gate structure both sides respectively passes through connecting line electricity
Connection.
Optionally, it further includes：Connect the gate plug of the gate structure.
Correspondingly, the present invention also provides a kind of forming method of mos capacitance, including：Substrate is provided, the substrate includes phase
Mutually adjacent device region and protection zone；Gate structure is formed on the device region substrate；It is formed on the protection zone substrate
Dummy gate structure；Source and drain doping area is formed in the device region substrate of the gate structure both sides；The connection source and drain is formed to mix
Miscellaneous area and the conductive structure of the dummy gate structure.
Optionally, the conductive structure includes：The source and drain plug in the source and drain doping area is connected, connects the dummy grid knot
The dummy grid plug of structure connects the connecting line of the dummy gate structure and the source and drain plug；Form the step of the conductive structure
Suddenly include：Dielectric layer is formed on the device region substrate and protection zone substrate；Respectively in the device region and protection zone medium
Contact hole is formed in layer, the device region contact holes exposing goes out the source and drain doping area, and the protection zone contact holes exposing goes out institute
State dummy gate structure top surface；Source and drain plug is formed in the device region contact hole；The shape in the protection zone contact hole
Into dummy grid plug；Connecting line is formed on the dielectric layer, the connecting line connects the source and drain and mixes plug and the pseudo- grid
Pole plug.
Optionally, the source and drain plug for connecting the source and drain doping area of the gate structure both sides respectively passes through connecting line electricity
Connection.
Optionally, it further includes：Form the gate plug for connecting the gate structure.
Optionally, it is formed before gate structure, further included：Ion implanting is carried out to the device region substrate, in the device
Well region is formed in part area substrate.
Optionally, in the well region there is trap ion, there are Doped ions, the Doped ions in the source and drain doping area
It is identical with the conduction type of the trap ion or differ.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the mos capacitance that technical solution of the present invention provides, the mos capacitance include connecting the dummy gate structure with it is described
The conductive structure in source and drain doping area is then electrically connected between the dummy gate structure and the source and drain doping area.The mos capacitance exists
During use, apply current potential in the source and drain doping area, be then also applied with identical current potential in the dummy gate structure,
And the current potential in the dummy gate structure is stable current potential.When external environment changes, such as when extraneous humidity, temperature hair
When changing causes the dummy gate structure resistance to change or electric field that external circuit is formed is to the charge in dummy gate structure
Effect when changing, the current potential in dummy gate structure is less likely to occur to change, and can make between dummy gate structure and substrate
Voltage be steady state value.Therefore, the variation of external environment is not easy to make the current potential of substrate to change, so as to be not easy to influence grid
Capacitance between pole structure and substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
In the forming method for the mos capacitance that technical solution of the present invention provides, formed connect the dummy gate structure with it is described
The conductive structure in source and drain doping area is then electrically connected between the dummy gate structure and the source and drain doping area.The mos capacitance exists
During use, apply current potential in the source and drain doping area, be then also applied with identical current potential in the dummy gate structure.
And the current potential in the dummy gate structure is stable current potential.When external environment changes, such as when extraneous humidity, temperature hair
When changing causes the dummy gate structure resistance to change or electric field that external circuit is formed is to the charge in dummy gate structure
Effect when changing, the current potential in dummy gate structure is less likely to occur to change, and can make between dummy gate structure and substrate
Voltage be steady state value.Therefore, the variation of external environment is not easy to make the current potential of substrate to change, so as to be not easy to influence grid
Capacitance between pole structure and substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
Description of the drawings
Fig. 1 and Fig. 2 is a kind of structure diagram of mos capacitance；
Fig. 3 to Figure 10 is the structure diagram of each step of one embodiment of forming method of mos capacitance of the present invention.
Specific embodiment
Existing semiconductor structure there are problems, such as：The poor-performing of mos capacitance.
The reason of poor-performing of the mos capacitance being analyzed below in conjunction with attached drawing.
Fig. 1 and Fig. 2 is a kind of structure diagram of mos capacitance.
It please refers to Fig.1 and Fig. 2, Fig. 2 is sectional views of the Fig. 1 along cutting line 11-12, the mos capacitance includes：Substrate 100,
The substrate 100 includes having fin on the device region A to adjoin each other and protection zone B, the substrate 100 device region A and protection zone B
Portion 101；Isolation structure 102 on the substrate 100,102 surface of isolation structure are less than the 101 top table of fin
Face；Across the gate structure 110 of the device region A fins 101, the gate structure 110 covers the device region A fins 101
Partial sidewall and top surface；Across the dummy gate structure 111 of the protection zone B fins 101, the dummy gate structure 111 is covered
Cover 101 partial sidewall of protection zone B fins and top surface；It is located in the 110 both sides fin 101 of gate structure respectively
Source region 121 and drain region 122；Connect the conductive structure 132 in the source region 121 and drain region 122.
Wherein, it before conductive structure 132 is formed, needs to form the covering source region 121, drain region 122 and gate structure
110 140 (not shown in figure 1) of dielectric layer, and planarization process is carried out to the dielectric layer 140.In the planarization process
In the process, the dummy gate structure 110 can play a supportive role to the medium 140, so as to reduce in the dielectric layer 140
Recess improves the insulating properties of the dielectric layer 140.
However, since the dummy gate structure 111 is hanging, the current potential generated in the dummy gate structure 111 is unstable.Example
Such as, the variation of the humidity of external environment, temperature etc. easily causes the variation of 111 resistance of dummy gate structure, so as to cause dummy grid
The variation of current potential in structure 111；Alternatively, the variation for the electric field that external circuit is formed, easily causes the quantity of electric charge in dummy gate structure
Variation, so as to cause the variation of current potential in dummy gate structure 111.Current potential is unstable easy in the dummy gate structure 111
The current potential of the substrate 100 is influenced, so as to influence the voltage between substrate 100 and gate structure 111, and then to gate structure
Capacitance between 110 and substrate 100 has an impact.
To solve the technical problem, the present invention provides a kind of mos capacitance, including：Substrate, the substrate include mutual
Adjacent device region and protection zone；Gate structure on the device region substrate；Positioned at gate structure both sides device
Source and drain doping area in area's substrate；Dummy gate structure on the protection zone substrate；Connect the source and drain doping area and institute
State the conductive structure of dummy gate structure.
Wherein, the mos capacitance includes connecting the dummy gate structure and the conductive structure in the source and drain doping area, then institute
It states and is electrically connected between dummy gate structure and the source and drain doping area.The mos capacitance is mixed during use in the source and drain
Apply current potential in miscellaneous area, then identical current potential, and the current potential in the dummy gate structure are also applied in the dummy gate structure
For stable current potential.When external environment changes, such as when extraneous humidity, temperature change and cause dummy gate structure resistance
When changing or when the electric field of external circuit formation changes to the effect of the charge in dummy gate structure, dummy grid
Current potential in structure is less likely to occur to change, and it is steady state value that can make the voltage between dummy gate structure and substrate.Therefore, it is extraneous
The variation of environment is not easy to make the current potential of substrate to change, so as to be not easy to influence the capacitance between gate structure and substrate,
And then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 10 is the structure diagram of each step of one embodiment of forming method of mos capacitance of the present invention.
It please refers to Fig.3, substrate is provided, the substrate includes device region I and protection zone II.
The device region I is used to form semiconductor devices, and the protection zone II is used to be subsequently formed dummy gate structure.
In the present embodiment, the substrate includes：Substrate 200 and on the device region I and protection zone II substrates 200
Fin 201.In other embodiments, the substrate can also be planar substrate.
In the present embodiment, the protection zone II is located at the device region I both sides.
In the present embodiment, the material of the substrate 200 and the fin 201 is silicon.In other embodiments, the substrate
Material with the fin is germanium or SiGe, and the substrate can also be the semiconductor bases such as silicon-on-insulator, germanium on insulator.
In the present embodiment, the forming method further includes：Isolation structure 202, the isolation are formed in the substrate 200
Structure 202 covers 201 partial sidewall of fin, and 202 surface of the isolation structure is less than 202 top surface of fin.
In the present embodiment, the material of the isolation structure 202 is silica.In other embodiments, the isolation structure
Material can also be silicon nitride or silicon oxynitride.
In the present embodiment, formed after the isolation structure 202, further included：Trap is formed in the device region I substrates
Area has trap ion in the well region.
In the present embodiment, the well region is also located in the protection zone II substrates.Specifically, the well region is located at the device
In part area I and protection zone II fins 201.
In the present embodiment, the step of forming the well region, includes：Ion implanting is carried out to the fin 201, in the fin
Trap ion is injected in portion 201.
In the present embodiment, the trap ion is N-type ion, such as phosphonium ion or arsenic ion.In other embodiments, it is described
Trap ion can also be p-type ion, such as boron ion or BF2-Ion.
It please refers to Fig.4, gate structure 210 is formed on the device region I substrates；It is formed on the protection zone II substrates
Dummy gate structure 211.
In the present embodiment, the gate structure 210 is across the device region I fins 201, and the gate structure 210
In 201 partial sidewall of fin and top surface.
In the present embodiment, the dummy gate structure 211 is across the protection zone II fins 201, and the dummy gate structure
211 are located at 201 partial sidewall of fin and top surface.
In the present embodiment, the step of forming the gate structure 210 and dummy gate structure 211, includes：It is formed described in covering
Device region I and the gate dielectric layer of 201 side wall of protection zone II fins and top surface；Grid layer is formed on the gate dielectric layer；
The gate dielectric layer and grid layer are patterned, form the gate structure 210 and dummy gate structure 211.
In the present embodiment, the material of the gate dielectric layer is silica.In other embodiments, the material of the gate dielectric layer
Material can also be high k (dielectric constant is more than 3.9) dielectric material.
In the present embodiment, the material of the grid is polysilicon.In other embodiments, the material of the grid can be with
For metal, such as：Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
In the present embodiment, the step of forming the gate structure 210 and dummy gate structure 211, further includes：Described in formation
During grid layer, doping in situ is carried out to the grid layer, grid doping ion is mixed in the grid layer.
Specifically, in the present embodiment, the grid doping ion is N-type ion, such as phosphonium ion or arsenic ion, at other
In embodiment, the grid doping ion is also p-type ion, including：Boron ion or BF2-Ion.
Fig. 5 is please referred to, source and drain doping area 220 is formed in the device region I substrates of 210 both sides of gate structure.
It is electrically connected to each other between the source and drain doping area 220 of 210 both sides of gate structure.
In the present embodiment, the source and drain doping area 220 be located at the gate structure 210 and the dummy gate structure 211 it
Between substrate in.
In the present embodiment, the material in the source and drain doping area 220 is SiGe.In other embodiments, the source and drain doping
The material in area can also be silicon-carbon or silicon.
In the present embodiment, the technique for forming source and drain doping area 220 includes epitaxial growth technology.
In the present embodiment, during source and drain doping area 220 is formed by the epitaxial growth technology, mixed by situ
General labourer's skill is doped the source and drain doping area 220, and Doped ions are mixed in the source and drain doping area 220.
In the present embodiment, the Doped ions are identical with the conduction type of the trap ion.In other embodiments, it is described
The conduction type of Doped ions and the trap ion can also differ.
In the present embodiment, the Doped ions are N-type ion, such as phosphonium ion or arsenic ion.In other embodiments, institute
The material in source and drain doping area is stated as silicon or carbon silicon, the Doped ions can also be p-type ion, such as boron ion or BF2-Ion.
It is subsequently formed and connects the source and drain doping area 220 and the conductive structure of the dummy gate structure 211.
In the present embodiment, the conductive structure includes：The source and drain plug in the source and drain doping area 220 is connected, described in connection
The dummy grid plug of dummy gate structure 211 connects the connecting line of the dummy grid plug and the source and drain plug.Specifically, shape
Into the step of the conductive structure as shown in Fig. 6 to 10.
Fig. 6 is please referred to, dielectric layer 230 is formed on the device region I substrates and protection zone II substrates.
The dielectric layer 230 is used to implement the isolation between different conductive structures.
In the present embodiment, the material of the dielectric layer 230 is silica.In other embodiments, the material of the dielectric layer
Material can also be silicon oxynitride or silicon nitride.
In the present embodiment, the technique for forming the dielectric layer 230 includes fluid chemistry gas-phase deposition.
Fig. 7 is please referred to, source and drain contact hole 203, the source and drain contact hole 203 are formed in the device region I dielectric layers 230
The source and drain doping area 220 is exposed, pseudo- grid contact hole 204 is formed in the protection zone II dielectric layers 203, the puppet grid connect
Contact hole 204 exposes 211 top surface of dummy gate structure.
The source and drain contact hole 203 and the pseudo- grid contact hole 204 accommodate source and drain plug and dummy grid respectively for follow-up
Plug.
In the present embodiment, the technique for forming the source and drain contact hole 203 and the pseudo- grid contact hole 204 includes dry etching
Technique.
It should be noted that in the present embodiment, the forming method of the conductive structure further includes：It is situated between in the device region I
Gate contact hole (not shown) is formed in matter layer 230.
Fig. 8 and Fig. 9 are please referred to, Fig. 9 is sectional views of the Fig. 8 along cutting line 23-24, and dielectric layer 230 is had ignored in Fig. 8,
Source and drain plug 231 is formed in the source and drain contact hole 203；Dummy grid plug 232 is formed in the pseudo- grid contact hole 204.
The source and drain plug 231 is used to implement being electrically connected for the source and drain doping area 220 and external circuit；The dummy grid
Plug 232 is used to implement being electrically connected for the dummy gate structure 211 and the source and drain doping area 220.
In the present embodiment, the material of the source and drain plug 231 and the dummy grid plug 232 is tungsten.In other embodiment
In, the material of the source and drain plug and the dummy grid plug can also be copper.
In the present embodiment, the technique for forming the source and drain plug 231 and the dummy grid plug 232 includes：Chemical gaseous phase
Depositing operation, physical gas-phase deposition or electrochemical plating membrane process.
In the present embodiment, the forming method further includes：Form the gate plug 233 for connecting the gate structure 210, institute
Gate plug 233 is stated through the dielectric layer 230.
The gate plug 233 is used to implement being electrically connected for gate structure 210 and external circuit.
In the present embodiment, the material of the gate plug 233 is tungsten.In other embodiments, the material of the gate plug
Material can also be copper.
0 is please referred to Fig.1, connecting line 240 is formed on the dielectric layer 230, the connecting line 240 connects the source and drain and inserts
Plug 231 and the dummy grid plug 232.
The connecting line 240 connects the source and drain plug 231 and the dummy grid plug 232, then the dummy gate structure
It is electrically connected between 211 and the source and drain doping area 220.The mos capacitance is during use, in the source and drain doping area
Apply current potential on 220, then identical current potential is also applied in the dummy gate structure 211, and on the dummy grid plug 232
Current potential is stable current potential.When external environment changes, such as when extraneous humidity, temperature change and cause dummy gate structure
When 211 resistance change or when the electric field of external circuit formation changes to the effect of the charge in dummy gate structure,
Current potential in dummy gate structure 211 is less likely to occur to change, so as to which the voltage between dummy gate structure 211 and substrate be made to be constant
Value, therefore, the variation of external environment is not easy to make the current potential of substrate to change, so as to be not easy influence gate structure 210 and
Capacitance between substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
In the present embodiment, the source and drain plug 231 for connecting the source and drain doping area 220 of 210 both sides of gate structure respectively is logical
The connecting line 240 is crossed to be electrically connected.
In the present embodiment, the material of the connecting line 240 is aluminium, and in other embodiments, the material of the connecting line is also
Can be copper or albronze.
In the present embodiment, the technique for forming the connecting line 240 includes：Chemical vapor deposition method.In other embodiment
In, physical gas-phase deposition or electrochemical plating membrane process can also be included by forming the technique of the connecting line.
To sum up, in the forming method of mos capacitance provided in an embodiment of the present invention, the mos capacitance includes connecting the puppet
Gate structure and the conductive structure in the source and drain doping area, then be electrically connected between the dummy gate structure and the source and drain doping area
It connects.The mos capacitance applies current potential during use in the source and drain doping area, then in the dummy gate structure
Identical current potential is applied with, and the current potential in the dummy gate structure is stable current potential.When external environment changes, such as when
The electric field pair that extraneous humidity, temperature change when causing the dummy gate structure resistance to change or external circuit is formed
When the effect of charge in dummy gate structure changes, the current potential in dummy gate structure is less likely to occur to change, and can make puppet
Voltage between gate structure and substrate is steady state value.Therefore, the variation of external environment is not easy to make the current potential of substrate to become
Change, so as to be not easy to influence the capacitance between gate structure and substrate, and then can ensure the precision of the capacitance of mos capacitance,
Improve mos capacitance performance.
With continued reference to Figure 10, the embodiment of the present invention additionally provides a kind of mos capacitance, including：Substrate, the substrate include phase
Mutually adjacent device region I and protection zone II；Gate structure 210 on the device region I substrates；Positioned at the gate structure
Source and drain doping area 220 in 210 both sides device region I substrates；Dummy gate structure 211 on the protection zone II substrates；Even
Connect the conductive structure in the source and drain doping area 220 and the dummy gate structure 211.
The device region I is used to form semiconductor devices, and the protection zone II is used to form dummy gate structure 211.
In the present embodiment, the substrate includes：Substrate 200 and on the device region I and protection zone II substrates 200
Fin 201.In other embodiments, the substrate can also be planar substrate.
In the present embodiment, the protection zone II is located at the device region I both sides.
In the present embodiment, the material of the substrate 200 and the fin 201 is silicon.In other embodiments, the substrate
Material with the fin is germanium or SiGe, and the substrate can also be the semiconductor bases such as silicon-on-insulator, germanium on insulator.
In the present embodiment, the mos capacitance further includes：Isolation structure 202 in the substrate 200, the isolation
Structure 202 covers 201 partial sidewall of fin, and 202 surface of the isolation structure is less than 202 top surface of fin.
In the present embodiment, the material of the isolation structure 202 is silica.In other embodiments, the isolation structure
Material can also be that silicon nitride or nitrogen are itched SiClx.
In the present embodiment, the mos capacitance further includes the well region in the device region I substrates, has in the well region
There is trap ion.
In the present embodiment, the well region is also located in the protection zone II substrates.Specifically, the well region is located at the device
In part area I and protection zone II fins 201.
In the present embodiment, the trap ion is N-type ion, such as phosphonium ion or arsenic ion.In other embodiments, it is described
Trap ion can also be p-type ion, such as boron ion or BF2-Ion.
In the present embodiment, the gate structure 210 is across the device region I fins 201, and the gate structure 210
In 201 partial sidewall of fin and top surface.
In the present embodiment, the dummy gate structure 211 is across the protection zone II fins 201, and the dummy gate structure
210 are located at 201 partial sidewall of fin and top surface.
Specifically, in the present embodiment, the grid doping ion is N-type ion, such as phosphonium ion or arsenic ion, at other
In embodiment, the grid doping ion is also p-type ion, including：Boron ion or BF2-Ion.
In the present embodiment, the source and drain doping area 220 be located at the gate structure 210 and the dummy gate structure 211 it
Between substrate in.
In the present embodiment, the material in the source and drain doping area 220 is SiGe.In other embodiments, the source and drain doping
The material in area can also be silicon-carbon or silicon.
In the present embodiment, there are Doped ions in the source and drain doping area 220.The Doped ions and the trap ion
Conduction type is identical.In other embodiments, the conduction type of the Doped ions and the trap ion can also differ.
In the present embodiment, the Doped ions are N-type ion, such as phosphonium ion or arsenic ion.In other embodiments, institute
The material in source and drain doping area is stated as silicon or carbon silicon, the Doped ions can also be p-type ion, such as boron ion or BF2-Ion.
In the present embodiment, the conductive structure includes：The source and drain plug 231 in the source and drain doping area 220 is connected, connects institute
The dummy grid plug 232 of dummy gate structure 211 is stated, connects the connection of the dummy grid plug 232 and the source and drain plug 231
Line.
In the present embodiment, the semiconductor structure further includes：On the device region I substrates and protection zone II substrates
Dielectric layer 230.
In the present embodiment, the mos capacitance further includes：The gate plug for connecting the gate structure 210 (is not shown in figure
Go out), the gate plug 233 runs through the dielectric layer 230.
The gate plug 233 is used to implement being electrically connected for gate structure 210 and external circuit.
The source and drain plug 231 and the dummy grid plug 232 are located in the dielectric layer 230, the connecting line 240
In on the dielectric layer 230.
The source and drain plug 231 is used to implement being electrically connected for the source and drain doping area 220 and external circuit；The dummy grid
Plug 232 is used to implement being electrically connected for the dummy gate structure 211 and the source and drain doping area 220.
In the present embodiment, the material of the source and drain plug 231 and the dummy grid plug 232 is tungsten.In other embodiment
In, the material of the source and drain plug and the dummy grid plug can also be copper.
The connecting line 240 connects the source and drain plug 231 and the dummy grid plug 232, then the dummy gate structure
It is electrically connected between 211 and the source and drain doping area 220.The mos capacitance is during use, in the source and drain doping area
Apply current potential on 220, be then also applied with identical current potential, and in the dummy gate structure 211 in the dummy gate structure 211
Current potential is stable current potential.When external environment changes, such as when extraneous humidity, temperature change and cause dummy gate structure
When 211 resistance change or the electric field of external circuit formation changes to the effect of the charge in dummy gate structure 211
When, the current potential in dummy gate structure 211 is less likely to occur to change, so as to which the voltage between dummy gate structure 211 and substrate be made to be
Steady state value, therefore, the variation of external environment are not easy to make the current potential of substrate to change, so as to be not easy to influence gate structure
Capacitance between 210 and substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
The source-drain area of the gate structure both sides is electrically connected to each other.In the present embodiment, the gate structure two is connected respectively
The source and drain plug in the source and drain doping area of side is electrically connected by the connecting line.
In the present embodiment, the material of the connecting line 240 is aluminium, and in other embodiments, the material of the connecting line is also
Can be copper or copper aluminium.
To sum up, it in mos capacitance provided in an embodiment of the present invention, is formed and connects the dummy gate structure and the source and drain doping
The conductive structure in area is then electrically connected between the dummy gate structure and the source and drain doping area.The mos capacitance is in the mistake used
Cheng Zhong applies current potential in the source and drain doping area, then is also applied with identical current potential in the dummy gate structure.And the puppet
Current potential on gate structure is stable current potential.When external environment changes, such as when extraneous humidity, temperature change and draw
The electric field that when dummy gate structure resistance changes or external circuit is formed is played to send out the effect of the charge in dummy gate structure
During changing, the current potential in dummy gate structure is less likely to occur to change, and can make the voltage between dummy gate structure and substrate be
Steady state value.Therefore, the variation of external environment is not easy to make the current potential of substrate to change, so as to be not easy influence gate structure with
Capacitance between substrate, and then can ensure the precision of the capacitance of mos capacitance, improve mos capacitance performance.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of mos capacitance, which is characterized in that including：
Substrate, the substrate include the device region to adjoin each other and protection zone；
Gate structure on the device region substrate；
Source and drain doping area in the gate structure both sides device region substrate；
Dummy gate structure on the protection zone substrate；
Connect the conductive structure in the source and drain doping area and the dummy gate structure.
2. mos capacitance as described in claim 1, which is characterized in that further include the well region in the device region substrate, institute
Gate structure is stated to be located on the well region；
In the well region there is trap ion, there are in the source and drain doping area Doped ions, the Doped ions and the trap from
The conduction type of son is identical or differs.
3. mos capacitance as claimed in claim 2, which is characterized in that the trap ion and Doped ions are phosphonium ion, arsenic from
Son, boron ion or BF2-Ion.
4. mos capacitance as described in claim 1, which is characterized in that the source-drain area of the gate structure both sides is electrically connected to each other.
5. mos capacitance as described in claim 1, which is characterized in that the conductive structure includes：Connect the source and drain doping area
Source and drain plug, connect the dummy grid plug of the dummy gate structure, connect the dummy gate structure and the source and drain plug
Connecting line.
6. mos capacitance as claimed in claim 5, which is characterized in that the material of the connecting line is aluminium or albronze.
7. mos capacitance as claimed in claim 5, which is characterized in that the material of the dummy grid plug is copper or aluminium.
8. mos capacitance as claimed in claim 5, which is characterized in that connect the source and drain doping of the gate structure both sides respectively
The source and drain plug in area is electrically connected by the connecting line.
9. mos capacitance as described in claim 1, which is characterized in that further include：Connect the gate plug of the gate structure.
10. a kind of forming method of mos capacitance, which is characterized in that including：
Substrate is provided, the substrate includes the device region to adjoin each other and protection zone；
Gate structure is formed on the device region substrate；
Dummy gate structure is formed on the protection zone substrate；
Source and drain doping area is formed in the device region substrate of the gate structure both sides；
It is formed and connects the source and drain doping area and the conductive structure of the dummy gate structure.
11. the forming method of mos capacitance as claimed in claim 10, which is characterized in that the conductive structure includes：Connection institute
The source and drain plug in source and drain doping area is stated, the dummy grid plug of the dummy gate structure is connected, connects the dummy gate structure and institute
State the connecting line of source and drain plug；
The step of forming the conductive structure includes：Dielectric layer is formed on the device region substrate and protection zone substrate；Respectively
Contact hole is formed in the device region and protection zone dielectric layer, the device region contact holes exposing goes out the source and drain doping area,
The protection zone contact holes exposing goes out the dummy gate structure top surface；Source and drain is formed in the device region contact hole to insert
Plug；Dummy grid plug is formed in the protection zone contact hole；Connecting line, the connecting line connection are formed on the dielectric layer
The source and drain mixes plug and the dummy grid plug.
12. the forming method of mos capacitance as claimed in claim 11, which is characterized in that connect the gate structure two respectively
The source and drain plug in the source and drain doping area of side is electrically connected by the connecting line.
13. the forming method of mos capacitance as claimed in claim 11, which is characterized in that further include：It is formed and connects the grid
The gate plug of structure.
14. the forming method of mos capacitance as claimed in claim 10, which is characterized in that formed before gate structure, also wrapped
It includes：Ion implanting is carried out to the device region substrate, well region is formed in the device region substrate.
15. the forming method of mos capacitance as claimed in claim 14, which is characterized in that there is trap ion, institute in the well region
Stating has Doped ions in source and drain doping area, the Doped ions are identical with the conduction type of the trap ion or differ.
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