CN109166820A - Manufacturing method of semiconductor device and semiconductor devices - Google Patents
Manufacturing method of semiconductor device and semiconductor devices Download PDFInfo
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- CN109166820A CN109166820A CN201810989689.3A CN201810989689A CN109166820A CN 109166820 A CN109166820 A CN 109166820A CN 201810989689 A CN201810989689 A CN 201810989689A CN 109166820 A CN109166820 A CN 109166820A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The present invention provides a kind of manufacturing method of semiconductor device and semiconductor devices, it first carries out photoetching and etching technics forms the first aperture of the second dielectric layer through the first substrate, first medium layer and segment thickness, photoetching is executed again and etching technics forms the second aperture of the first medium layer through first substrate and segment thickness, then execute without mask etching technique, with the part the first metal layer below the second metal layer and the second aperture below exposure first aperture, interconnection layer is eventually formed, realizes the metal interconnection between two wafers.The present invention only need to can form the first aperture and the second aperture using twice light shield, and realize the interconnection of the first metal layer and second metal layer, simplify technique, and reduce production cost.
Description
Technical field
The invention belongs to ic manufacturing technology fields, and in particular to manufacturing method of semiconductor device and semiconductor device
Part.
Background technique
Under the trend that the semiconductor of Highgrade integration develops, the integrated of chip with different function is semiconductor packages
The main direction of development of technology, crystal circular piled based on 3D-IC technology can be realized more inexpensive, more rapidly and more high density
Target.And after wafer bonding, how to realize that the metal interconnection between wafer is the important process in semiconductor technology.Hair
Bright people's discovery is usually to use third photo etching (need to use three light shields) and three times etching technics at present, and the process is more complicated, raw
Produce higher cost.
Summary of the invention
The purpose of the present invention is to provide a kind of manufacturing method of semiconductor device and semiconductor devices, to simplify technique,
Reduce production cost.
In order to solve the above technical problems, the present invention provides manufacturing method of semiconductor device.
There is provided bonding after the first wafer and the second wafer, first wafer include the first substrate, first medium layer and
The first metal layer, second wafer include the second substrate, second dielectric layer and second metal layer, the first medium level to
The second dielectric layer；
Photoetching and etching technics are executed, the first aperture is formed, first aperture runs through first substrate, first medium
The second dielectric layer of layer and segment thickness, first aperture are located above the second metal layer；
Photoetching and etching technics are executed, the second aperture is formed, second aperture is thick through first substrate and part
The first medium layer of degree, second aperture are located above the first metal layer of part, second aperture and described first
Aperture connection；
It executes without mask etching technique, below the second metal layer and the second aperture below exposure first aperture
The part the first metal layer；And
Form interconnection layer, the interconnection layer by first aperture and second aperture and the second metal layer and
The metal interconnection between two wafers is realized in the first metal layer electrical connection.
The present invention also provides a kind of semiconductor devices, comprising:
First wafer and the second wafer, first wafer include the first substrate, first medium layer and the first metal layer, institute
Stating the second wafer includes the second substrate, second dielectric layer and second metal layer, and the first medium level is to the second medium
Layer bonding；
First aperture and the second aperture, first aperture run through first substrate, first medium layer and segment thickness
Second dielectric layer, first aperture is located above the second metal layer, and second aperture runs through first substrate
With the first medium layer of segment thickness, second aperture is located above the first metal layer of part, second aperture with
The first aperture connection；And
Interconnection layer is formed in first aperture and second aperture, the interconnection layer and the first metal layer
It is electrically connected with the second metal layer.
The present invention provides a kind of manufacturing method of semiconductor device, first carries out photoetching and etching technics is formed through the first lining
Bottom, first medium layer and segment thickness second dielectric layer the first aperture, first aperture is located at the second metal layer
Top, then execute photoetching and etching technics and form second of first medium layer through first substrate and segment thickness and open
Hole, second aperture are located above the first metal layer of part and are connected to the first aperture, then execute without mask etching
Technique, with the part the first metal layer below the second metal layer and the second aperture below exposure first aperture, most
After form interconnection layer, realize the metal interconnection between two wafers.Compared with the prior art, it is only necessary to execute Twi-lithography and etching work
Skill and once without mask etching technique, need to can only form the first aperture and the second aperture using twice light shield and realize first
The interconnection of metal layer and second metal layer simplifies technique, and reduces production cost.
Detailed description of the invention
Fig. 1 is the flow diagram of the manufacturing method of semiconductor device of one embodiment of the invention；
Fig. 2 is schematic diagram after two wafer bondings of one embodiment of the invention；
Fig. 3 is the schematic diagram after first aperture of formation of one embodiment of the invention；
Fig. 4 is that the schematic diagram after filled layer is formed in first aperture of one embodiment of the invention；
Fig. 5 is the schematic diagram after second aperture of formation of one embodiment of the invention；
Fig. 6 is that the schematic diagram after filled layer is removed in first aperture of one embodiment of the invention；
Fig. 7 is the schematic diagram for exposing the first metal layer and second metal layer of one embodiment of the invention；
Fig. 8 is the schematic diagram filled after forming interconnection layer in the first aperture and the second aperture of one embodiment of the invention；
Wherein, appended drawing reference is as follows:
The first wafer of 10-；
The first substrate of 101-；102- first medium layer；103- the first metal layer；The first etching stop layer of 104-；
102a- first medium layer first part；102b- first medium layer second part；
The second wafer of 20-；
The second substrate of 201-；202- second dielectric layer；203- second metal layer；The second etching stop layer of 204-；
202a- second dielectric layer first part；202b- second dielectric layer second part；205- passivation layer；
31- bonded interface；
The first aperture of 41-；The second aperture of 42-；
50- filled layer；
60- interconnection layer.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to manufacturing method of semiconductor device proposed by the present invention and semiconductor device
Part is described in further detail.According to following explanation, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is equal
Using very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.
The embodiment of the present invention provides a kind of manufacturing method of semiconductor device, as shown in Figure 1, comprising:
There is provided bonding after the first wafer and the second wafer, first wafer include the first substrate, first medium layer and
The first metal layer, second wafer include the second substrate, second dielectric layer and second metal layer, the first medium level to
The second dielectric layer；
Photoetching and etching technics are executed, the first aperture is formed, first aperture runs through first substrate, first medium
The second dielectric layer of layer and segment thickness, first aperture are located above the second metal layer；
Photoetching and etching technics are executed, the second aperture is formed, second aperture is thick through first substrate and part
The first medium layer of degree, second aperture are located above the first metal layer of part, second aperture and described first
Aperture connection；
It executes without mask etching technique, below the second metal layer and the second aperture below exposure first aperture
The part the first metal layer；And
Form interconnection layer, the interconnection layer by first aperture and second aperture and the second metal layer and
The metal interconnection between two wafers is realized in the first metal layer electrical connection.
It should be noted that the present invention do not limit the first wafer and the second wafer which wafer have to be placed over/
Lower section, but the position of upper and lower wafer can be interchanged.Herein, simple, conveniently in order to describe, merely illustrate the two wafers
A kind of positional relationship, and those skilled in the art can understand, all technology contents being described herein are equally applicable
In the position of " the first wafer " and " the second wafer " is turned upside down the case where, the position of each layer of stacked semiconductor devices at this time
Relationship also correspondingly turns upside down.In some cases it may be preferred to ground, during carrying out bonding processing to two wafers, by wafer
The bigger wafer of curvature (bow) is placed on following.It but in this case, can also basis after wafer bonding
Actual demand decides whether to turn upside down, so that it is determined which final wafer is in which wafer above below.
It note that herein, the numbers such as " first ", " second ", " third ", " the 4th " are intended merely to mutually of the same name to having
The each different components or technique claimed are distinguished and are used, and are not meant to sequence or positional relationship etc..In addition, for phase
With each different components, such as " the first substrate " and " the second substrate ", " first medium layer " and " second dielectric layer " etc. of title
Deng being not meant to their structures all having the same or component.For example, although not shown in the drawings, still in most feelings
Under condition, the component formed in " the first substrate " and " the second substrate " is all different, and the structure of substrate may also be different.Some
In embodiment, substrate can be semiconductor substrate, by be suitable for semiconductor device any semiconductor material (such as Si,
SiC, SiGe etc.) it is made.In other embodiments, substrate may be silicon-on-insulator (SOI), silicon germanium on insulator etc.
Various compound substrates.Those skilled in the art understand that substrate is not any way limited, but can be carried out according to practical application
Selection.It could be formed with various devices (being not limited to semiconductor device) component (not shown) in substrate.Substrate can also be
It is formed with other layers or component, such as: gate structure, contact hole, dielectric layer, metal connecting line and through-hole etc..
Below in conjunction with Fig. 2 to the production method of Fig. 8 the present invention is described in detail embodiment.
As shown in Fig. 2, providing the first wafer 10 and the second wafer 20 after bonding, first wafer 10 includes the first lining
Bottom 101, first medium layer 102 and the first metal layer 103, second wafer 20 include the second substrate 201, second dielectric layer
202 and second metal layer 203, the first medium layer 102 utilize bonding medium bed boundary towards the second dielectric layer 202
Two wafers are bonded by the intermolecular chemical force of film, form bonded interface 31.
Wherein, the first medium layer 102 includes first medium layer first part 102a and first medium layer second part
102b, the first metal layer 103 are embedded at first medium layer first part 102a and first medium layer second part
Between 102b；The second dielectric layer 202 includes second dielectric layer first part 202a and second dielectric layer second part 202b,
The second metal layer 203 be embedded at the second dielectric layer first part 202a and second dielectric layer second part 202b it
Between.
Further, first wafer 10 further includes the first etching stop layer 104, first etching stop layer 104
Between the first metal layer 103 and the first medium layer second part 102b；Second wafer 20 further includes
Two etching stop layers 204, second etching stop layer 204 are located at the second metal layer 203 and the second dielectric layer the
Between two part 202b.Second wafer 20 further includes the passivation layer 205 positioned at the surface second dielectric layer second part 202b.
Preferably, after bonding, the first wafer 10 and/or the second wafer 20 are carried out it is thinned, to reduce the thickness of device,
On the one hand the first aperture 41 is easily formed after being thinned, the thickness on the other hand reducing wafer entirety after being bonded is conducive to the height of wafer
It is integrated.
As shown in figure 3, photoetching and etching technics the first aperture 41 of formation are executed, using first of light shield, described first
101 surface of substrate forms patterned photoresist layer one, and the photoresist for being located at 203 top of second metal layer is formed after exposure development
Opening, is performed etching with patterned photoresist layer one for exposure mask, and etching stopping forms first in the second etching stop layer 204
Aperture 41 then removes the photoresist layer one of 101 surface graphics of the first substrate.First aperture 41 is through first lining
Bottom 101, first medium layer 102 and second dielectric layer second part 202b, first aperture 41 are located at the second metal layer
203 tops.
As shown in figure 4, forming filled layer 50, filled layer described in the present embodiment uses the BARC (Bottom of good fluidity
Anti Reflective Coating, bottom antireflective coating), BARC fills up several first apertures 41, then to described
The filled layer 50 in one aperture 41 is etched, and remaining 50 top surface of the filled layer is made to be higher than the first metal layer
103 surface.
As shown in figure 5, photoetching and etching technics the second aperture 42 of formation are executed, using second light shield, described first
101 surface of substrate forms patterned photoresist layer two, is formed and is located at 103 top of part the first metal layer and the second metal of part
The photoresist opening of 203 top of layer, is performed etching for exposure mask with patterned photoresist layer two, forms the second aperture 42, with surplus
The remaining filled layer 50 is used as etching stop layer, makes the bottom surface of second aperture 42 and the top of the remaining filled layer 50
Face flushes.Second aperture 42 runs through the first medium layer 102 of first substrate 101 and segment thickness, and described second opens
Hole 42 is located at part 103 top of the first metal layer, and second aperture 42 is connected to first aperture 41.Also, institute
State the second aperture 42 cross-sectional width be greater than first aperture 41 cross-sectional width (cross section referred to herein refers to vertically
The section of cutting is carried out in the first wafer and the second wafer).
As shown in fig. 6, removing the remaining filled layer 50 in first aperture 41 using etch process.
As shown in fig. 7, executing without mask etching, the second etching stop layer 204 of 41 bottom of the first aperture is removed, and is removed
Second aperture, 42 bottom and the first medium layer first part 102a for being located at 103 surface of the first metal layer, expose the first aperture
The part the first metal layer 103 of 42 lower section of second metal layer 203 and the second aperture of 41 lower sections.This etching is without light
Cover directly carries out that the cost of one of light shield thus can be saved without mask etching.It should be noted that only being got rid of in Fig. 7
The first medium layer first part 102a on 103 surface of the first metal layer, but be can also have a degree of mistake in specific implementation
Etching, the first medium layer first part 102a of 103 side of the first metal layer can also be removed, this has no effect on device
The performance of part.
As shown in figure 8, forming interconnection layer 60, the interconnection layer 60 passes through first aperture 41 and second aperture 42
It is electrically connected with the second metal layer 203 and the first metal layer 103, realizes the metal interconnection between two wafers.
The interconnection layer 60 is conductive material, can be copper or copper alloy, electro-coppering mode can be used and fill the first aperture
41 and second aperture 42,101 surface of the first substrate is covered, and carry out chemical mechanical grinding planarization process, removes the first substrate
The interconnection layer on 101 surface.
The embodiment of the present invention also provides a kind of semiconductor devices, as shown in figs. 2,7 and 8, comprising:
First wafer 10 and the second wafer 20, first wafer 10 include the first substrate 101, are formed in the first substrate
First medium layer 102 on 101 and the first metal layer 103 being embedded in first medium layer 102, second wafer 20 include
Second substrate 201, second dielectric layer 202 and second metal layer 203, the first medium layer 102 is towards the second dielectric layer
202 bondings；
First aperture 41 and the second aperture 42, first aperture 41 run through first substrate 101, first medium layer
102 and segment thickness second dielectric layer 202, first aperture 41 is located at 203 top of the second metal layer, described second
Aperture 42 runs through the first medium layer 102 of first substrate 101 and segment thickness, and second aperture 42 is located at described in part
103 top of the first metal layer, second aperture 42 are connected to first aperture 41；And
Interconnection layer 60 is formed in first aperture 41 and second aperture 42, the interconnection layer 60 and described the
One metal layer 103 and the second metal layer 203 are electrically connected.
Further, first aperture 41 and second aperture 42 are perpendicular to first wafer 10 and described second
The shape in the section on 20 surface of wafer is inverted trapezoidal.
In conclusion first carrying out photoetching the present invention provides a kind of manufacturing method of semiconductor device and etching technics being formed
Through the first aperture of the second dielectric layer of the first substrate, first medium layer and segment thickness, first aperture is located at described
Above second metal layer, then photoetching and etching technics formation are executed through the first medium layer of first substrate and segment thickness
The second aperture, second aperture is located above the first metal layer of part and is connected to the first aperture, then executes nothing
Mask etching technique, with part first gold medal below the second metal layer and the second aperture below exposure first aperture
Belong to layer, eventually form interconnection layer, realizes the metal interconnection between two wafers.Compared with the prior art, it is only necessary to execute Twi-lithography
And etching technics and once without mask etching technique, only the first aperture and the second aperture can need to be formed simultaneously using twice light shield
The interconnection for realizing the first metal layer and second metal layer, simplifies technique, and reduce production cost.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (9)
1. a kind of manufacturing method of semiconductor device characterized by comprising
The first wafer and the second wafer after providing bonding, first wafer include the first substrate, first medium layer and first
Metal layer, second wafer include the second substrate, second dielectric layer and second metal layer, and the first medium level is to described
Second dielectric layer；
Execute photoetching and etching technics, form the first aperture, first aperture through first substrate, first medium layer and
The second dielectric layer of segment thickness, first aperture are located above the second metal layer；
Photoetching and etching technics are executed, forms the second aperture, second aperture is through first substrate and segment thickness
First medium layer, second aperture are located above the first metal layer of part, second aperture and first aperture
Connection；
It executes without mask etching technique, with the part below the second metal layer and the second aperture below exposure first aperture
The first metal layer；And
Interconnection layer is formed, the interconnection layer passes through first aperture and second aperture and the second metal layer and first
The metal interconnection between two wafers is realized in metal layer electrical connection.
2. manufacturing method of semiconductor device as described in claim 1, which is characterized in that formed after the first aperture, form the
Before two apertures, further includes:
Filled layer is formed, the filled layer fills first aperture and covers the surface of first substrate；And
Etch back process is executed, is removed described in the part in the filled layer and first aperture of first substrate surface
Filled layer makes the top surface of the remaining filled layer in first aperture be higher than the surface of the first metal layer.
3. manufacturing method of semiconductor device as claimed in claim 2, which is characterized in that during forming the second aperture, with
The remaining filled layer keeps the bottom surface of second aperture and the remaining filled layer top surface neat as etching stop layer
It is flat.
4. manufacturing method of semiconductor device as claimed in claim 3, which is characterized in that before executing without mask etching technique,
Further include:
Remove the remaining filled layer in first aperture.
5. manufacturing method of semiconductor device according to any one of claims 1 to 4, which is characterized in that form interconnection layer
Step includes:
It executes electroplating technology and forms interconnection layer, the interconnection layer is filled described in first aperture and second aperture and covering
The surface of first substrate；And
Chemical mechanical milling tech is executed, the interconnection layer on the surface of first substrate is removed and carries out surface planarisation processing.
6. manufacturing method of semiconductor device according to any one of claims 1 to 4, which is characterized in that the interconnection layer
Material is copper or copper alloy.
7. manufacturing method of semiconductor device according to any one of claims 1 to 4, which is characterized in that the first medium
Layer includes that first medium layer first part and first medium layer second part, the first metal layer are embedded at the first medium
Between layer first part and first medium layer second part；The second dielectric layer includes second dielectric layer first part and second
Dielectric layer second part, the second metal layer are embedded at the second dielectric layer first part and second dielectric layer second part
Between；First wafer further includes the first etching stop layer, first etching stop layer be located at the first metal layer with
Between the first medium layer second part；Second wafer further includes the second etching stop layer, second etching stopping
Layer is between the second metal layer and the second dielectric layer second part.
8. manufacturing method of semiconductor device according to any one of claims 1 to 4, which is characterized in that form the first aperture
Before, further includes:
The first wafer and/or the second wafer after para-linkage carry out thinned.
9. a kind of semiconductor devices characterized by comprising
First wafer and the second wafer, first wafer include the first substrate, first medium layer and the first metal layer, and described the
Two wafers include the second substrate, second dielectric layer and second metal layer, and the first medium level is to the second dielectric layer key
It closes；
First aperture and the second aperture, first aperture through first substrate, first medium layer and segment thickness the
Second medium layer, first aperture are located above the second metal layer, and second aperture runs through first substrate and portion
The first medium layer of point thickness, second aperture are located at the part the first metal layer top, second aperture with it is described
First aperture connection；And
Interconnection layer is formed in first aperture and second aperture, the interconnection layer and the first metal layer and institute
State second metal layer electrical connection.
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| CN201810989689.3A CN109166820B (en) | 2018-08-28 | 2018-08-28 | Semiconductor device manufacturing method and semiconductor device |
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| CN201810989689.3A CN109166820B (en) | 2018-08-28 | 2018-08-28 | Semiconductor device manufacturing method and semiconductor device |
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| CN112435977A (en) * | 2020-11-20 | 2021-03-02 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| WO2022104972A1 (en) * | 2020-11-20 | 2022-05-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method therefor |
| CN112435977B (en) * | 2020-11-20 | 2023-09-01 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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