CN109148360B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN109148360B CN109148360B CN201810988446.8A CN201810988446A CN109148360B CN 109148360 B CN109148360 B CN 109148360B CN 201810988446 A CN201810988446 A CN 201810988446A CN 109148360 B CN109148360 B CN 109148360B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The present invention provides manufacturing method of semiconductor device, first aperture and the second aperture are longitudinally separated, the first metal layer and the second metal layer electrical connection made by interconnection layer improves the flexibility of wafer design no longer by the restriction of TSV nesting hole transverse direction processing procedure.Patterned first photoresist layer filling the first aperture (first aperture is shallow bore hole) is used in the present invention, solves the problems, such as that difficulty is filled in deep hole and removed to filled layer in TSV nesting pore structure.Patterned first photoresist layer can be used as filled layer, be also used as exposure mask, eliminate to form filled layer and be etched back to two processing steps of filled layer, can simplify technique, shortens the production cycle, advantageously reduces production cost.Third dielectric layer of the present invention can be used to that the interconnection layer and first substrate is isolated, and can also form third aperture wherein, so as to realize the first metal layer and second metal layer interconnection by third aperture.
Description
Technical field
The invention belongs to ic manufacturing technology fields, and in particular to a kind of manufacturing method of semiconductor device.
Background technique
TSV (Through Silicon Via, through silicon via) technology is wafer and wafer by between chip and chip
Between manufacture vertical conducting, realize the new technology interconnected between chip, can to stack density in three-dimensional bigger.
In TSV technology, in a kind of manufacturing method of semiconductor device of TSV nesting pore structure, often tied by TSV nesting hole
Structure realizes the metal interconnection of upper wafer and lower wafer, and TSV nesting hole includes the upper aperture, middle aperture and lower aperture of vertical communication,
Wherein descending aperture is deep hole.This production method can largely solve the demand of the metal interconnection after bonding.But it sends out
Bright people's discovery, the limitation of this production method in practical applications also become increasingly conspicuous.This production method is communicated by longitudinal
TSV nesting hole connect the metal layer of wafer up and down, it is nested that the metal layer of upper and lower wafer is distributed the TSV longitudinally communicated when design
The metal layer lateral distance of the restriction of hole transverse direction processing procedure, such as upper and lower wafer must not be too far away, for aperture company if too far
It connects, the effective area of upper wafer is all wasted, therefore the flexibility of wafer design aspect is lower, while with the depth of lower aperture deep hole
For width than increasing, filling and removal of the filled layer in deep hole are also more difficult.
Summary of the invention
The purpose of the present invention is to provide manufacturing method of semiconductor device, to solve the half of existing TSV nesting pore structure
The flexibility of wafer design aspect is lower in conductor device production method, while leading to manufacturing process with the increase of the depth-to-width ratio of deep hole
The problem of difficulty increases.
In order to solve the above technical problems, the present invention provides manufacturing method of semiconductor device, comprising:
The first wafer and the second wafer after providing bonding, first wafer include the first substrate, are located at described first
The first medium layer of substrate face and the first metal layer being embedded in the first medium layer；Second wafer includes second
Substrate, the second dielectric layer on second substrate and the second metal layer being embedded in the second dielectric layer, it is described
First medium level is to the second dielectric layer；
Etching forms the first aperture, and first aperture runs through first substrate and part the first medium layer and position
Above the first metal layer；
Patterned first photoresist layer is formed, patterned first photoresist layer fills first aperture and covers institute
The first substrate back is stated, and patterned first photoresist layer has the photoresist window being located above the second metal layer；
The second aperture is formed by mask etching of patterned first photoresist layer, second aperture is through described the
One wafer and the part second dielectric layer and it is located above the second metal layer；
Form third dielectric layer, the third dielectric layer cover first substrate back, first open surface and
Second open surface；
Form third aperture, the third medium positioned at first substrate back of the third aperture through part thickness
Layer, the third aperture be located at the first metal layer and the second metal layer top and respectively with first aperture and institute
State the second aperture connection；
Execute dry etch process, with below exposure first aperture the first metal layer and second aperture below
The second metal layer；And
Interconnection layer is formed, the interconnection layer passes through the third aperture, first aperture and second aperture and institute
State the first metal layer and second metal layer electrical connection.
Manufacturing method of semiconductor device provided by the invention, the first aperture through the first substrate and part first medium layer and
Above the first metal layer, the second aperture is through the first wafer and part second dielectric layer and is located above second metal layer,
First aperture is not interconnected with the second aperture, i.e. it is finally by mutual that the first aperture and the second aperture, which are longitudinally separated,
The first metal layer and second metal layer electrical connection that even layer makes, i.e. lateral connection, are no longer limited by TSV nesting hole transverse direction processing procedure
Constraint improves the flexibility of wafer design.Also, the first aperture is filled using patterned first photoresist layer in the present invention,
First aperture solves filled layer in TSV nesting pore structure and fills out in deep hole through the first substrate (first aperture is shallow bore hole)
Fill and remove difficult problem.
Further, after the present invention forms the first aperture, patterned first photoresist layer of formation, described patterned first
Photoresist layer fills the first aperture and covers the first substrate back, and has the photoresist window being located above second metal layer, then
The second aperture is formed by mask etching of patterned first photoresist, it is seen then that patterned first photoresist layer can be used as filling
Object is also used as exposure mask, eliminates to form filled layer and be etched back to two processing steps of filled layer, can simplify technique, shortens
Production cycle advantageously reduces production cost.
In addition, the present invention also forms third dielectric layer, the third dielectric layer covers first substrate back, described the
One open surface and second open surface, the third aperture through part thickness are located at first substrate back
Third dielectric layer, it is seen then that the third dielectric layer can be used to that the interconnection layer and first substrate is isolated, can also be at it
The middle third aperture for forming connection the first aperture and the second aperture, so as to realize the first metal layer and described by third aperture
Second metal layer interconnection.
Detailed description of the invention
Fig. 1 is a kind of diagrammatic cross-section of the semiconductor devices of TSV nesting pore structure；
Fig. 2 is that a kind of TSV separates the upper wafer after being bonded in the manufacturing method of semiconductor device of pore structure and lower wafer
Diagrammatic cross-section；
Fig. 3 is that a kind of TSV separates the section etched after forming the first aperture in the manufacturing method of semiconductor device of pore structure
Schematic diagram；
Fig. 4 is that a kind of TSV separates the diagrammatic cross-section formed after filled layer in the manufacturing method of semiconductor device of pore structure；
Fig. 5 is etched back to the section signal after filled layer in the manufacturing method of semiconductor device for a kind of TSV separation pore structure
Figure；
Fig. 6 is that a kind of TSV is separated in the manufacturing method of semiconductor device of pore structure and formed cuing open after patterned photoresist layer
Face schematic diagram；
Fig. 7 forms the section signal after the second aperture in the manufacturing method of semiconductor device for a kind of TSV separation pore structure
Figure；
Fig. 8 is the manufacturing method of semiconductor device flow chart of the embodiment of the present invention；
Fig. 9 is that the first wafer and second wafer after being bonded in the manufacturing method of semiconductor device of the embodiment of the present invention cut open
Face schematic diagram；
Figure 10 is that etching forms the section signal after the first aperture in the manufacturing method of semiconductor device of the embodiment of the present invention
Figure；
Figure 11 be the embodiment of the present invention manufacturing method of semiconductor device in form cuing open after patterned first photoresist layer
Face schematic diagram；
Figure 12 be the embodiment of the present invention manufacturing method of semiconductor device in form the diagrammatic cross-section after the second aperture；
Figure 13 be the embodiment of the present invention manufacturing method of semiconductor device in remove cuing open after patterned first photoresist layer
Face schematic diagram；
Figure 14 is that the diagrammatic cross-section after third dielectric layer is formed in the manufacturing method of semiconductor device of the embodiment of the present invention；
Figure 15 be the embodiment of the present invention manufacturing method of semiconductor device in form the diagrammatic cross-section after the second photoresist layer；
Figure 16 be the embodiment of the present invention manufacturing method of semiconductor device in form cuing open after patterned second photoresist layer
Face schematic diagram；
Figure 17 is that the diagrammatic cross-section after third aperture is formed in the manufacturing method of semiconductor device of the embodiment of the present invention；
Figure 18 be the embodiment of the present invention manufacturing method of semiconductor device in remove cuing open after patterned second photoresist layer
Face schematic diagram；
Figure 19 is after exposing the first metal layer and second metal layer in the manufacturing method of semiconductor device of the embodiment of the present invention
Diagrammatic cross-section；
Figure 20 is that the diagrammatic cross-section after interconnection layer is formed in the manufacturing method of semiconductor device of the embodiment of the present invention.
Wherein, appended drawing reference is as follows:
The upper wafer of 10-；
The first substrate of 101-；102- first medium layer；103- the first metal layer；104- interconnection layer；
Wafer under 20-；
The second substrate of 201-；202- second dielectric layer；203- second metal layer；204- passivation layer；
A- bonded interface；
31-TSV nesting hole；The upper aperture of 31a-；Aperture in 31b-；Aperture under 31c-；
The upper wafer of 40-；
The first substrate of 401-；402- first medium layer；403- the first metal layer；The second passivation layer of 404-；405- first is blunt
Change layer；406- filled layer；407- photoresist layer；
Wafer under 50-；
The second substrate of 501-；502- second dielectric layer；503- second metal layer；
B- bonded interface；
The first aperture of 61-；The second aperture of 62-；
The first wafer of 70-；
The first substrate of 701-；702- first medium layer；702a- first medium layer first part；702b- first medium layer
Two parts；703- the first metal layer；The first etching stop layer of 704-；The second passivation layer of 705-；The first passivation layer of 706-；707-
One photoresist layer；708- third dielectric layer；The second photoresist layer of 709-；710- interconnection layer；
The second wafer of 80-；
The second substrate of 801-；802- second dielectric layer；803- second metal layer；The second etching stop layer of 804-；
C- bonded interface；
The first aperture of 91-；The second aperture of 92-；93- third aperture.
Specific embodiment
As described in background, a kind of manufacturing method of semiconductor device of current TSV nesting pore structure is deposited in practical applications
In limitation.This production method passes through the metal layer that the TSV nesting hole longitudinally communicated connects wafer up and down, the gold of upper and lower wafer
Belong to the restriction of the TSV nesting hole transverse direction processing procedure longitudinally communicated when layer distribution design, while with the deep wide of lower aperture deep hole
Than increasing, filling and removal of the filled layer in deep hole are also more difficult.
Specifically, a kind of semiconductor devices of TSV nesting pore structure, as shown in Figure 1, its production method, comprising:
The upper wafer 10 and lower wafer 20 of bonding are provided, the upper wafer 10 includes the first substrate 101, is located at the first substrate
First medium layer 102 on 101 fronts and the first metal layer 103 being embedded in first medium layer 102.Lower wafer 20 includes the
Two substrates 201, the second dielectric layer 202 on the second substrate 201, the second metal layer being embedded in second dielectric layer 202
203 and the passivation layer 204 in second dielectric layer 202, first medium layer 102 forms bonded interface A towards passivation layer 204.
TSV nesting hole 31 is formed, TSV nesting hole 31 includes upper aperture 31a, middle aperture 31b and lower aperture 31c.On
Aperture 31a is through the first substrate 101 and positioned at the top of the first metal layer 103 and second metal layer 203.Lower aperture 31c runs through
The second dielectric layer 202 of first wafer 10 and segment thickness simultaneously exposes second metal layer 203, and lower aperture 31c is deep hole.In open
Hole 31b is connected between upper aperture 31a and lower aperture 31c and with upper aperture 31a and lower aperture 31c, and middle aperture 31b exposes
The first metal layer 103.
Interconnection layer 104 is formed, the interconnection layer 104 passes through TSV nesting hole 31 and the first metal layer 103 and second metal layer
203 electrical connections.
Wherein, middle aperture 31b is formed by etching, is needed before aperture 31b in etching is formed first (deep in lower aperture 31c
Hole) in form filled layer to protect second metal layer 203, etching formed in remove in lower aperture 31c (deep hole) after aperture 31b
Filled layer.
Inventors have found that although the manufacturing method of semiconductor device of this TSV nesting pore structure, interconnection layer 104 pass through TSV
Nested hole 31 is electrically connected with the first metal layer 103 and second metal layer 203, and the interconnection of upper and lower wafer, still, first may be implemented
The restriction of the lateral processing procedure in the nested hole 31 the TSV that metal layer 103 is longitudinally communicated when being distributed and design with second metal layer 203,
If the first metal layer 103 and 203 lateral distance of second metal layer must not be too far away, for aperture connection, upper wafer if too far
10 effective area is all wasted.Increase simultaneously with the depth-to-width ratio of lower aperture 31c deep hole, filling of the filled layer in deep hole and goes
Except also more difficult.
Based on the studies above, a kind of manufacturing method of semiconductor device of TSV separation pore structure is proposed, wherein to realize
The interconnection of metal layer in upper and lower two wafer need to be respectively formed the first aperture for exposing the first chip metal layer and expose second
Second aperture of chip metal layer, the first aperture and the second aperture separation (being not communicated with).The preparation of first aperture and the second aperture
It is the committed step of metal interconnection, specifically, first etching forms the first aperture, the first aperture is filled using filled layer and covers the
One crystal column surface, then it is etched back to the filled layer of the first crystal column surface of removal, then in the first crystal column surface and filling layer surface shape
At patterned photoresist, etching forms the second aperture later, finally removes filled layer and patterned photoresist.
Further research, inventor have found that the manufacturing method of semiconductor device of this TSV separation pore structure includes multiple works
Sequence step, and the material category used is more, causes the technological parameter quantity of regulation big, there are complex process, production cycles to grow
Problem.
Specifically, introducing a kind of semiconductor devices production side of TSV separation pore structure below with reference to shown in Fig. 2 to Fig. 7
Method.
As shown in Fig. 2, provide bonding after upper wafer 40 and lower wafer 50, the upper wafer 40 include the first substrate 401,
First medium layer 402 on 401 front of the first substrate and the first metal layer 403 being embedded in first medium layer 402；Under
Wafer 50 includes the second substrate 501, the second dielectric layer 502 on the second substrate 501 and is embedded in second dielectric layer 502
Second metal layer 503.
Further, upper wafer 40 further includes the first passivation layer 405 positioned at 401 back side of the first substrate, is located at first and is situated between
Second passivation layer 404 on 402 surface of matter layer.Second passivation layer 404 forms bonded interface B towards second dielectric layer 502.
Then, as shown in figure 3, etching forms the first aperture 61, the first aperture 61 is served as a contrast through the first passivation layer 405, first
Bottom 401 and part the first medium layer 402 and it is located at the top of the first metal layer 403.
Then, as shown in figure 4, forming filled layer 406；The filled layer 406 fills first aperture 61 and covers institute
State 405 surface of the first passivation layer.
Then, as shown in figure 5, being etched back to the filled layer 406 on removal 406 surface of the first passivation layer, to guarantee that etching is clean
A degree of over etching is carried out, the filled layer 406 at such first aperture, 61 top is etched a little.
Then, as shown in fig. 6, forming patterned photoresist layer 407, patterned photoresist layer 407 covers the first passivation layer
405 surfaces and 406 surface of filled layer simultaneously have the photoresist window for being located at 403 top of second metal layer.
It then, is that mask etching forms the with the patterned photoresist layer 407 as shown in fig. 7, forming the second aperture 62
Two apertures 62, second aperture 62 is through upper wafer 40 and part second dielectric layer 502 and is located in second metal layer 503
Side.Finally, removal filled layer 406 and patterned photoresist layer 407.This preparation method includes multiple process, and is used
Material category it is more, cause the technological parameter quantity of regulation big, there is a problem of that complex process, production cycle are long.
Based on above-mentioned further investigation, the embodiment of the invention provides a kind of manufacturing method of semiconductor device, as shown in figure 8,
Include the following steps:
S1, the first wafer and the second wafer after bonding are provided, first wafer includes the first substrate, is located at described the
The first medium layer of one substrate face and the first metal layer being embedded in the first medium layer；Second wafer includes the
Two substrates, the second dielectric layer on second substrate and the second metal layer being embedded in the second dielectric layer, institute
First medium level is stated to the second dielectric layer；
S2, etching form the first aperture, and first aperture runs through first substrate and part the first medium layer
And it is located above the first metal layer；
S3, patterned first photoresist layer is formed, patterned first photoresist layer is filled first aperture and covered
First substrate back is covered, and patterned first photoresist layer has the photoresist window being located above the second metal layer
Mouthful；
S4, the second aperture is formed by mask etching of patterned first photoresist layer, second aperture runs through institute
It states the first wafer and the part second dielectric layer and is located above the second metal layer；
S5, third dielectric layer is formed, the third dielectric layer covers first substrate back, first open surface
With second open surface；
S6, third aperture, the third positioned at first substrate back of the third aperture through part thickness are formed
Dielectric layer, the third aperture be located above the first metal layer and the second metal layer and respectively with first aperture
It is connected to second aperture；
S7, execute dry etch process, with below exposure first aperture the first metal layer and second aperture
The second metal layer of lower section；And
S8, form interconnection layer, the interconnection layer by the third aperture, first aperture and second aperture and
The first metal layer and second metal layer electrical connection.
Below in conjunction with the drawings and specific embodiments, the present invention is described in more detail.It is of the invention according to following explanation
Advantages and features will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-accurate ratio, only
To convenient, the lucidly aid illustration embodiment of the present invention the purpose.
Below with reference to manufacturing method of semiconductor device provided in an embodiment of the present invention shown in Fig. 9 to Figure 20, is discussed in detail.
As shown in figure 9, providing the first wafer 70 and the second wafer 80 after bonding, first wafer 70 includes the first lining
Bottom 701, the first medium layer 702 on 701 front of the first substrate and the first metal layer being embedded in first medium layer 702
703；Second wafer 80 includes the second substrate 801, the second dielectric layer 802 on the second substrate 801 and is embedded at second Jie
Second metal layer 803 in matter layer 802, first medium layer 702 form bonded interface C towards second dielectric layer 802.
Further, the first wafer 70 further includes the first passivation layer 706 positioned at 701 back side of the first substrate, is located at first
Second passivation layer 705 on 702 surface of dielectric layer.
Further, first medium layer 702 includes first medium layer first part 702a and first medium layer second part
702b, the first metal layer 703 be embedded at first medium layer first part 702a and first medium layer second part 702b it
Between；Second dielectric layer 802 includes second dielectric layer first part 802a and second dielectric layer second part 802b, second metal layer
803 are embedded between second dielectric layer first part 802a and second dielectric layer second part 802b.
In preferred embodiment, the first wafer 70 further includes the first etching stop layer 704, and the first etching stop layer 704 is located at institute
It states between the first metal layer 703 and first medium layer first part 702a；Second wafer 80 further includes the second etching stop layer
804, the second etching stop layer 804 is located between second metal layer 803 and the second dielectric layer second part 802b.
Then, as shown in Figure 10, etching forms the first aperture 91, and etching stopping is opened in the first etching stop layer 704, first
Hole 91 is through the first passivation layer 706, the first substrate 701 and part the first medium layer 702 and is located on the first metal layer 703
Side.
Then, as shown in figure 11, patterned first photoresist layer 707 is formed, patterned first photoresist layer 707 is filled out
First aperture 91 is filled to cover 706 surface of the first passivation layer and there is the light for being located at 803 top of second metal layer
Hinder window.
Then, as shown in figure 12, the second aperture 92 is formed, is mask etching with patterned first photoresist layer 707
The second aperture 92 is formed, etching stopping runs through 70 He of the first wafer in the second etching stop layer 804, second aperture 92
The part second dielectric layer 802 and it is located at 803 top of the second metal layer.
Further, the section of the first aperture 91 and the second aperture 92 perpendicular to 80 surface of the first wafer 70 and the second wafer
Shape be inverted trapezoidal.
Then, as shown in figure 13, patterned first photoresist layer 707 is removed.
Then, as shown in figure 14, third dielectric layer 708 is formed, the third dielectric layer 708 covers first passivation layer
706 surfaces, 91 surface of the first aperture and 92 surface of the second aperture.
Then, as shown in figure 15, the second photoresist layer 709 is formed, second photoresist layer 709 covers the third dielectric layer
708 surfaces and the surface of the first aperture 91 and the second aperture 92, and the first aperture 91 and the second aperture of fill part depth
92。
Then, as shown in figure 16, exposure and imaging technique is executed, patterned second photoresist layer 709, the figure are formed
The second photoresist layer 709 changed has the photoresist window positioned at 803 top of the first metal layer 703 and the second metal layer,
Second photoresist layer 709 of 92 bottom of the first aperture 91 and the second aperture can be removed together.
It then, as shown in figure 17, is exposure mask with patterned second photoresist layer 709, etched portions thickness is located at first
The third dielectric layer 708 at 701 back side of substrate forms the third aperture 93.
Then, as shown in figure 18, patterned second photoresist layer 709 is removed.
Exposure and imaging technique is executed, is formed in patterned second photoresist layer, 709 step, the first aperture 91 and second is opened
Second photoresist layer 709 of 92 bottom of hole can also have some reservations, be formed after third aperture 93, remove third dielectric layer together
Remaining second photoresist layer 709 of second photoresist layer 709 on 708 surfaces and the first aperture 91 and 92 bottom of the second aperture.
Then, as shown in figure 19, dry etch process is executed, the third dielectric layer of 91 bottom of the first aperture is removed
708 and the first etching stop layer 704 below and 92 bottom of the second aperture third dielectric layer 708 and below
Two etching stop layers 804, the second metal layer of 92 lower section of the first metal layer 703 and the second aperture of 91 lower section of the first aperture of exposure
803。
Then, as shown in figure 20, interconnection layer 710 is formed, interconnection layer 710 fills third aperture 93, the first aperture 91 and the
Two apertures 92 simultaneously cover third dielectric layer 708；Chemical mechanical milling tech is executed, the interconnection on 708 surface of third dielectric layer is removed
Layer 710.Interconnection layer 710 passes through third aperture 93, the first aperture 91 and the second aperture 92 and the first metal layer 703 and the second metal
Layer 803 is electrically connected.The material of interconnection layer 710 is copper or copper alloy, and electroplating technology can be used and form interconnection layer 710.
Preferably, the material of third dielectric layer 708 includes silicon nitride, and silicon nitride compactness is good, can be not only used for isolated interconnection
The side wall of layer 710 (e.g. copper) and the first substrate 701, preventing copper to be diffused into the first substrate 701 influences the first wafer 70
Performance；Third aperture can also be formed, in third dielectric layer 708 so as to realize the first metal layer and institute by third aperture
State second metal layer interconnection.
In addition, the material of third dielectric layer 708 is not limited to silicon nitride, or other prevent copper from expanding with isolation features
It is scattered to the dielectric layer material of the first substrate.
It should be understood that herein, the numbers such as " first ", " second ", " third ", " the 4th " are intended merely to mutually of the same name to having
The each different components or technique claimed are distinguished and are used, and are not meant to sequence or positional relationship etc..In addition, for phase
With each different components, such as " the first substrate " and " the second substrate ", " first medium layer " and " second dielectric layer " etc. of title
Deng being not meant to their structures all having the same or component.For example, although not shown in the drawings, still in most feelings
Under condition, the component formed in " the first substrate " and " the second substrate " is all different, and the structure of substrate may also be different.Some
In embodiment, substrate can be semiconductor substrate, by be suitable for semiconductor device any semiconductor material (such as Si,
SiC, SiGe etc.) it is made.In other embodiments, substrate may be silicon-on-insulator (SOI), silicon germanium on insulator etc.
Various compound substrates.Those skilled in the art understand that substrate is not any way limited, but can be carried out according to practical application
Selection.It could be formed with various devices (being not limited to semiconductor device) component (not shown) in substrate.Substrate can also be
It is formed with other layers or component, such as: gate structure, contact hole, dielectric layer, metal connecting line and through-hole etc..
Manufacturing method of semiconductor device provided by the invention, the first aperture through the first substrate and part first medium layer and
Above the first metal layer, the second aperture is through the first wafer and part second dielectric layer and is located above second metal layer,
First aperture is not interconnected with the second aperture, i.e. it is finally by mutual that the first aperture and the second aperture, which are longitudinally separated,
The first metal layer and second metal layer electrical connection that even layer makes, i.e. lateral connection, are no longer limited by TSV nesting hole transverse direction processing procedure
Constraint improves the flexibility of wafer design.Also, the first aperture is filled using patterned first photoresist layer in the present invention,
First aperture solves filled layer in TSV nesting pore structure and fills out in deep hole through the first substrate (first aperture is shallow bore hole)
Fill and remove difficult problem.
Further, after the present invention forms the first aperture, patterned first photoresist layer of formation, described patterned first
Photoresist layer fills the first aperture and covers the first substrate back, and has the photoresist window being located above second metal layer, then
The second aperture is formed by mask etching of patterned first photoresist, it is seen then that patterned first photoresist layer can be used as filling
Object is also used as exposure mask, eliminates to form filled layer and be etched back to two processing steps of filled layer, can simplify technique, shortens
Production cycle advantageously reduces production cost.
In addition, the present invention also forms third dielectric layer, the third dielectric layer covers first substrate back, described the
One open surface and second open surface, the third aperture through part thickness are located at first substrate back
Third dielectric layer, it is seen then that the third dielectric layer can be used to that the interconnection layer and first substrate is isolated, can also be at it
The middle third aperture for forming connection the first aperture and the second aperture, so as to realize the first metal layer and described by third aperture
Second metal layer interconnection.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (9)
1. a kind of manufacturing method of semiconductor device characterized by comprising
The first wafer and the second wafer after providing bonding, first wafer include the first substrate, are located at first substrate
Positive first medium layer and the first metal layer being embedded in the first medium layer；Second wafer includes the second lining
Bottom, the second dielectric layer on second substrate and the second metal layer being embedded in the second dielectric layer, described
One dielectric layer is towards the second dielectric layer；
Etching forms the first aperture, and first aperture is through first substrate and part the first medium layer and is located at institute
It states above the first metal layer；
Form patterned first photoresist layer, patterned first photoresist layer fills first aperture and covers described the
One substrate back, and patterned first photoresist layer has the photoresist window being located above the second metal layer；
The second aperture is formed by mask etching of patterned first photoresist layer, second aperture is brilliant through described first
Circle is with the part second dielectric layer and above the second metal layer；
Form third dielectric layer, the third dielectric layer covers first substrate back, first open surface and described
Second open surface；
Formation third aperture, the third dielectric layer positioned at first substrate back of the third aperture through part thickness,
The third aperture be located above the first metal layer and the second metal layer and respectively with first aperture and described
Second aperture connection；
Dry etch process is executed, with the first metal layer below exposure first aperture and the institute below second aperture
State second metal layer；And
Interconnection layer is formed, the interconnection layer fills the third aperture, first aperture and second aperture, the interconnection
Layer passes through the third aperture, first aperture and second aperture and the first metal layer and the second metal layer
Electrical connection,
Wherein, the step of formation third aperture specifically includes:
Form the second photoresist layer in the third dielectric layer surface, second photoresist layer cover the third dielectric layer surface with
And the surface of first aperture and the second aperture, and first aperture and second aperture of fill part depth；
Exposure and imaging technique is executed, patterned second photoresist layer is formed, patterned second photoresist layer, which has, to be located at
Photoresist window above the first metal layer and the second metal layer；
Using patterned second photoresist layer as exposure mask, the third medium positioned at the first substrate back of etched portions thickness
Layer, forms the third aperture；And
Remove patterned second photoresist layer.
2. manufacturing method of semiconductor device as described in claim 1, which is characterized in that first substrate back is formed with
One passivation layer, first aperture and second aperture also extend through first passivation layer.
3. manufacturing method of semiconductor device as described in claim 1, which is characterized in that when executing dry etch process, removal
The third dielectric layer of first aperture bottom and second aperture bottom.
4. manufacturing method of semiconductor device as described in claim 1, which is characterized in that formed interconnection layer the step of include:
Interconnection layer is formed, the interconnection layer fills the third aperture, first aperture and second aperture and covers institute
State third dielectric layer；And
Chemical mechanical milling tech is executed, the interconnection layer of the third dielectric layer surface is removed.
5. manufacturing method of semiconductor device as claimed in claim 4, which is characterized in that the material of the interconnection layer is copper or copper
Alloy forms the interconnection layer using electroplating technology.
6. the manufacturing method of semiconductor device as described in any one of claims 1 to 5, which is characterized in that the third medium
The material of layer includes silicon nitride.
7. the manufacturing method of semiconductor device as described in any one of claims 1 to 5, which is characterized in that the first medium
Layer includes that first medium layer first part and first medium layer second part, the first metal layer are embedded at the first medium
Between layer first part and first medium layer second part；The second dielectric layer includes second dielectric layer first part and second
Dielectric layer second part, the second metal layer are embedded at the second dielectric layer first part and second dielectric layer second part
Between.
8. manufacturing method of semiconductor device as claimed in claim 7, which is characterized in that
First wafer further includes the first etching stop layer, and first etching stop layer is located at the first metal layer and institute
It states between first medium layer first part；Second wafer further includes the second etching stop layer, second etching stop layer
Between the second metal layer and the second dielectric layer second part；
When etching forms the first aperture, etching stopping is in first etching stop layer；
When etching forms the second aperture, etching stopping is in second etching stop layer；
When executing dry etch process, the first etching stop layer of removal first aperture bottom and second aperture bottom
The second etching stop layer.
9. the manufacturing method of semiconductor device as described in any one of claims 1 to 5, which is characterized in that first aperture
With second aperture perpendicular to the section of first wafer and the second crystal column surface shape be inverted trapezoidal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102751234A (en) * | 2011-04-19 | 2012-10-24 | 索尼公司 | Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus |
| CN104051422A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect structure and method of forming same |
| CN104952843A (en) * | 2015-07-01 | 2015-09-30 | 武汉新芯集成电路制造有限公司 | Chips of IoT (Internet of Things) system and preparation method of chips |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102751234A (en) * | 2011-04-19 | 2012-10-24 | 索尼公司 | Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus |
| CN104051422A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect structure and method of forming same |
| CN104952843A (en) * | 2015-07-01 | 2015-09-30 | 武汉新芯集成电路制造有限公司 | Chips of IoT (Internet of Things) system and preparation method of chips |
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