CN108122838A - Semiconductor device fabrication processes - Google Patents
Semiconductor device fabrication processes Download PDFInfo
- Publication number
- CN108122838A CN108122838A CN201711329358.9A CN201711329358A CN108122838A CN 108122838 A CN108122838 A CN 108122838A CN 201711329358 A CN201711329358 A CN 201711329358A CN 108122838 A CN108122838 A CN 108122838A
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- CN
- China
- Prior art keywords
- substrate
- semiconductor device
- fabrication processes
- device fabrication
- dielectric layer
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
The present invention provides a kind of semiconductor device fabrication processes, including：Semiconductor substrate is provided, the semiconductor substrate includes the substrate with device architecture and the interlayer dielectric layer on the substrate surface；Graphical photoresist is formed in the inter-level dielectric layer surface；Using the graphical photoresist as interlayer dielectric layer described in mask etching, the substrate is exposed；The substrate exposed is etched, forms groove；Substrate described in thinning back side forms multiple crystal grain.In the present invention, wafer can be completed to cut after the completion of wafer process, reduce the size of Cutting Road, form the crystal grain of more, reduce cost, improve efficiency.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology field more particularly to a kind of semiconductor device fabrication processes.
Background technology
In integrated circuit preparation process, device usually is prepared in wafer (wafer) first, wafer is cut afterwards
(Dicing) multiple crystal grain (Die) are formed, and CP tests are carried out to each crystal grain, lead packages then are carried out to crystal grain.In general,
Wafer techniques are completed by manufacturer (Foundry), other encapsulation are then transferred in Dicing techniques, CP tests, lead packages part
Manufacturer completes.During packaging and testing, encapsulation manufacturer cuts into wafer for example with the mode of machine cuts or laser cutting
Multiple crystal grain, then CP tests, encapsulation are carried out to crystal grain.However the preparation method of the device is less efficient, cost is higher, wafer is cut
During cutting larger silicon is caused to lose.
The content of the invention
It is an object of the invention to provide a kind of semiconductor device fabrication processes, solve prior art device preparation method
Efficiency reduces cost.
In order to solve the above technical problems, the present invention provides a kind of semiconductor device fabrication processes, including：
Semiconductor substrate is provided, the semiconductor substrate includes the substrate with device architecture and positioned at the substrate surface
On interlayer dielectric layer；
Graphical photoresist is formed in the inter-level dielectric layer surface；
Using the graphical photoresist as interlayer dielectric layer described in mask etching, the substrate is exposed；
The substrate exposed is etched, forms groove；
Substrate described in thinning back side forms multiple crystal grain.
Optionally, the characteristic size of the graphical photoresist is 3 microns~5 microns.
Optionally, the graphical photoresist exposes the Cutting Road of the semiconductor substrate.
Optionally, there is amplifier, D/A converter, analog processing circuit and/or digital processing electricity in the substrate
One or more device architectures in road, interface circuit.
Optionally, interconnection structure is formed in the interlayer dielectric layer, the interconnection structure and the device architecture are electrical
Connection.
Optionally, the substrate is silicon substrate, SOI substrate, silicon carbide substrates or germanium silicon substrate.
Optionally, the thickness of the substrate is 200 microns~250 microns.
Optionally, the material of the interlayer dielectric layer is silica or silicon nitride.
Optionally, the thickness of the interlayer dielectric layer is 2 microns~10 microns.
Optionally, using plasma etching technics etches the interlayer dielectric layer and the substrate.
Optionally, the depth of the groove is 150 microns~200 microns.
Compared with prior art, semiconductor device fabrication processes of the invention have the advantages that：
In the present invention, graphical photoresist is formed in the inter-level dielectric layer surface, is carved by mask of the graphical photoresist
The interlayer dielectric layer is lost, exposes the substrate, etches the substrate, groove, and substrate described in thinning back side is formed, is formed
Multiple crystal grain.In the present invention, wafer can be completed to cut after the completion of wafer process, reduce the size of Cutting Road, formed more
Multiple crystal grain reduces cost, improves efficiency.
Description of the drawings
Fig. 1 is the flow chart of the semiconductor device fabrication processes in one embodiment of the invention；
Fig. 2 is the schematic top plan view of semiconductor devices in one embodiment of the invention；
Fig. 3 is the diagrammatic cross-section of semiconductor devices in one embodiment of the invention.
Specific embodiment
The semiconductor device fabrication processes of the present invention are described in more detail below in conjunction with schematic diagram, wherein representing
The preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still real
The advantageous effects of the existing present invention.Therefore, description below is appreciated that for the widely known of those skilled in the art, and simultaneously
Not as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.It will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is, in the semiconductor device fabrication processes provided, including：Semiconductor substrate is provided,
The semiconductor substrate includes the substrate with device architecture and the interlayer dielectric layer on the substrate surface；In the layer
Between dielectric layer surface form graphical photoresist；Using the graphical photoresist as interlayer dielectric layer described in mask etching, institute is exposed
State substrate；The substrate exposed is etched, forms groove；Substrate described in thinning back side forms multiple crystal grain.In the present invention,
Wafer can be completed to cut after the completion of wafer process, can reduce the size of Cutting Road, the more crystal grain of forming quantity, from
And it reduces cost, improve efficiency.
The semiconductor device fabrication processes of the present invention are specifically described below in conjunction with attached drawing, Fig. 1 is preparation process's
Method flow diagram, Fig. 2 be semiconductor devices schematic top plan view, Fig. 3 be semiconductor devices diagrammatic cross-section, system of the invention
Standby technique includes the following steps：
First, execution step S1, it is shown referring to figs. 2 and 3, semiconductor substrate 10 is provided, the semiconductor substrate 10 wraps
Include the substrate 101 with device architecture (not shown) and the interlayer dielectric layer 102 on 101 surface of substrate.Its
In, the substrate is silicon (Si) substrate, and substrate described in certain the other embodiment of the present invention can also be SOI substrate, carbonization
Silicon (SiC) substrate, germanium silicon (GeSi) substrate or other substrate materials well known in the art not limit this in of the invention.This
In embodiment, the thickness of the substrate 101 is 200 microns~250 microns, such as 200 microns, 230 microns, 250 microns etc..Institute
Stating in substrate 101 has in amplifier, D/A converter, analog processing circuit and/or digital processing circuit, interface circuit
One or more device architectures may be employed CMOS technology and prepare the device architecture, this is known to those skilled in the art
, this will not be repeated here.The material of the interlayer dielectric layer 102 be silica or silicon nitride, the thickness of the interlayer dielectric layer 102
It spends for 2 microns~10 microns, interlayer dielectric layer is used to protect the device architecture in substrate, and in the interlayer dielectric layer 102
It is formed with interconnection structure (not shown), the interconnection structure is electrically connected with the device architecture, for by device architecture
Electrically pick out.
Step S2 is performed, graphical photoresist (Photo), the graphical light are formed on 102 surface of interlayer dielectric layer
Resistance exposes the Cutting Road (Scribe Line) 11 of the semiconductor substrate 10, and Cutting Road 11 is used for the semiconductor substrate
10 are separated into multiple crystal grain.The characteristic size (Critical Distance) of the graphical photoresist is 3 microns~5 microns, example
Such as, 4 microns, the thickness of graphical photoresist is 3 microns~5 microns, for example, 4 microns.The mode of laser cutting or machine cuts is cut
It cuts and forms crystal grain, the thickness for the photoresist used is at least 7 microns, and characteristic size is 7 microns.Therefore, it is graphical in the present invention
The thickness of photoresist and characteristic size smaller so that the Cutting Road of formation it is smaller.
Step S3 is performed, using the graphical photoresist as interlayer dielectric layer 102 described in mask etching, exposes the substrate
101, so as to which the Cutting Road of semiconductor substrate 10 be exposed.In the present embodiment, using plasma etching technics etching institute
State interlayer dielectric layer 102.Compared in the prior art using laser cutting or machine cuts semiconductor substrate by the way of, the present invention
The mode of middle using plasma etching, can reduce the size of Cutting Road, so as to reduce the loss of silicon substrate, increase crystal grain
Effective dimensions.
Step S4 is performed, etches the substrate 101 exposed, forms groove 13, in the present embodiment, using plasma
Etching technics etches the substrate 101, and the groove 13 is the position described in Cutting Road 11, and the depth of the groove 13 is 150
Micron~200 microns, for example, the depth of groove is 160 microns, 180 microns, 200 microns etc..Then, preparation work of the invention
The cleaning semiconductor substrate 10 is further included in skill, removes the graphical photoresist.
Perform step S5, substrate 101 described in thinning back side so that the semiconductor substrate 10 forms multiple crystal grain (Die)
11.In the present invention, the back side of the substrate 101 is thinned by the way of chemical mechanical grinding (CMP).In wafer wafer process
After finishing, wafer can be completed to cut in Fab, also, reduces the size of Cutting Road, the more crystal grain of forming quantity will
Cutting technique in encapsulation process is completed together with wafer process, so as to improve efficiency, reduce cost.
In conclusion in semiconductor device fabrication processes provided by the invention, including：Offer semiconductor substrate, described half
Conductor substrate includes the substrate with device architecture and the interlayer dielectric layer on the substrate surface；In the inter-level dielectric
Layer surface forms graphical photoresist；Using the graphical photoresist as interlayer dielectric layer described in mask etching, the substrate is exposed；
The substrate exposed is etched, forms groove；Substrate described in thinning back side forms multiple crystal grain.In the present invention, in wafer work
Wafer can be completed to cut in Fab after the completion of skill, can reduce the size of Cutting Road, the more crystal grain of forming quantity, from
And it reduces cost, improve efficiency.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
Claims (11)
1. a kind of semiconductor device fabrication processes, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes the substrate with device architecture and on the substrate surface
Interlayer dielectric layer；
Graphical photoresist is formed in the inter-level dielectric layer surface；
Using the graphical photoresist as interlayer dielectric layer described in mask etching, the substrate is exposed；
The substrate exposed is etched, forms groove；
Substrate described in thinning back side forms multiple crystal grain.
2. semiconductor device fabrication processes as described in claim 1, which is characterized in that the characteristic size of the graphical photoresist
For 3 microns~5 microns.
3. semiconductor device fabrication processes as described in claim 1, which is characterized in that the graphical photoresist exposes described
The Cutting Road of semiconductor substrate.
4. semiconductor device fabrication processes as described in claim 1, which is characterized in that in the substrate have amplifier, number/
One or more device architectures in mode converter, analog processing circuit and/or digital processing circuit, interface circuit.
5. semiconductor device fabrication processes as described in claim 1, which is characterized in that be formed in the interlayer dielectric layer mutually
Link structure, the interconnection structure is electrically connected with the device architecture.
6. semiconductor device fabrication processes as described in claim 1, which is characterized in that the substrate is silicon substrate, SOI is served as a contrast
Bottom, silicon carbide substrates or germanium silicon substrate.
7. semiconductor device fabrication processes as described in claim 1, which is characterized in that the thickness of the substrate is 200 microns
~250 microns.
8. semiconductor device fabrication processes as described in claim 1, which is characterized in that the material of the interlayer dielectric layer is oxygen
SiClx or silicon nitride.
9. semiconductor device fabrication processes as described in claim 1, which is characterized in that the thickness of the interlayer dielectric layer is 2
Micron~10 microns.
10. semiconductor device fabrication processes as described in claim 1, which is characterized in that using plasma etching technics is carved
Lose the interlayer dielectric layer and the substrate.
11. semiconductor device fabrication processes as described in claim 1, which is characterized in that the depth of the groove is 150 microns
~200 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711329358.9A CN108122838A (en) | 2017-12-13 | 2017-12-13 | Semiconductor device fabrication processes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711329358.9A CN108122838A (en) | 2017-12-13 | 2017-12-13 | Semiconductor device fabrication processes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108122838A true CN108122838A (en) | 2018-06-05 |
Family
ID=62229800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711329358.9A Pending CN108122838A (en) | 2017-12-13 | 2017-12-13 | Semiconductor device fabrication processes |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265475A (en) * | 2019-06-24 | 2019-09-20 | 长江存储科技有限责任公司 | A kind of wafer and its manufacturing method, wafer dividing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040080274A (en) * | 2003-03-11 | 2004-09-18 | 삼성전자주식회사 | Wafer dicing method using dry etching and back grinding |
| US20060088983A1 (en) * | 2004-10-21 | 2006-04-27 | Shinichi Fujisawa | Method of dividing wafer |
| CN103117250A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Methods for de-bonding carriers |
| CN105448826A (en) * | 2014-05-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Wafer cutting method |
-
2017
- 2017-12-13 CN CN201711329358.9A patent/CN108122838A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040080274A (en) * | 2003-03-11 | 2004-09-18 | 삼성전자주식회사 | Wafer dicing method using dry etching and back grinding |
| US20060088983A1 (en) * | 2004-10-21 | 2006-04-27 | Shinichi Fujisawa | Method of dividing wafer |
| CN103117250A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Methods for de-bonding carriers |
| CN105448826A (en) * | 2014-05-27 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Wafer cutting method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265475A (en) * | 2019-06-24 | 2019-09-20 | 长江存储科技有限责任公司 | A kind of wafer and its manufacturing method, wafer dividing method |
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Application publication date: 20180605 |