CN110265475A - A kind of wafer and its manufacturing method, wafer dividing method - Google Patents
A kind of wafer and its manufacturing method, wafer dividing method Download PDFInfo
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- CN110265475A CN110265475A CN201910549571.3A CN201910549571A CN110265475A CN 110265475 A CN110265475 A CN 110265475A CN 201910549571 A CN201910549571 A CN 201910549571A CN 110265475 A CN110265475 A CN 110265475A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention provides a kind of wafer and its manufacturing method, dividing method, pre-buried cutting groove is formd on the Cutting Road of wafer, the pre-buried cutting groove is penetrated through from the upper surface of wafer into the substrate of segment thickness, in this way, when carrying out wafer segmentation, it can be carried out from the back side of wafer thinned, and then realize the segmentation of bare die on wafer, without being cut or being reduced the intensity of cutting, it can realize the segmentation of bare die on wafer, cutting technique window is greatly promoted, production efficiency is improved.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of wafer and its manufacturing method, segmentation side
Method.
Background technique
In the wafer fabrication stage, based on substrate and it is formed on the chip of array arrangement, has been cut between these chips
It cuts, in the encapsulated phase of wafer, wafer segmentation will be independent chip along Cutting Road, it in turn, can be by independent core
Piece is encapsulated as packaging body.
Currently, mainly come the segmentation of realizing wafer, often being needed in cutting process by machine cuts or laser cutting
The multiple cutting of linear reciprocation is done along Cutting Road, divide low efficiency, and the chip generated will cause centainly in chip surface
The pollution of degree, and damage subtle on wafer can all lead to disintegrating tablet, sliver, the process window of cutting occur when cutting
It is small.
Summary of the invention
In view of this, improving cutter the purpose of the present invention is to provide a kind of wafer and its manufacturing method, dividing method
Skill window improves production efficiency.
To achieve the above object, the present invention has following technical solution:
A kind of wafer, comprising:
Substrate；
The bare die of array arrangement on substrate has Cutting Road between the bare die；
There is pre-buried cutting groove, the pre-buried cutting groove is penetrated through from the upper surface of wafer to segment thickness on the Cutting Road
Substrate in, and the pre-buried cutting groove extends to the two edges of wafer along the Cutting Road direction.
Optionally, the width of the pre-buried cutting groove is the 15-50% of the width of the cutting groove.
Optionally, the width of the pre-buried cutting groove is 10-30 μm.
Optionally, further includes: the test pads in the Cutting Road of the pre-buried cutting groove side.
Optionally, the height of pre-buried cutting groove bottom to the wafer lower surface is the 80- of the wafer thickness
90%.
A kind of manufacturing method of wafer, comprising:
Wafer is provided, the wafer includes the bare die of array arrangement on substrate and substrate, has between the bare die and cuts
It cuts；
Pre-buried cutting groove is formed in the Cutting Road, the pre-buried cutting groove penetrates through thick to part from the upper surface of wafer
In the substrate of degree, and the pre-buried cutting groove extends to the two edges of wafer along the Cutting Road direction.
It is optionally, described that pre-buried cutting groove is formed on the Cutting Road, comprising:
The Cutting Road is performed etching using etching technics, to form pre-buried cutting groove on the Cutting Road.
A kind of wafer dividing method, the dividing method include:
Wafer described in any of the above embodiments is provided, thinned protective film is pasted on the upper surface of the wafer；
It is carried out from the lower surface of wafer thinned, until the pre-buried cutting groove, wafer segmentation is independent bare die.
Optionally, the altitude range of pre-buried cutting groove is 50-200 μm in the wafer before being thinned, the crystalline substance after being thinned
Round thickness range is 30-180 μm.
Optionally, further includes:
It carries out the cold of cutting film and collapses technique, so that the spacing between individual die increases.
A kind of wafer dividing method, the dividing method include:
Wafer described in any of the above embodiments is provided；
The thickness that thinned and thinned thickness is less than pre-buried cutting groove bottom to wafer lower surface is carried out from the lower surface of wafer
Degree；
The substrate under pre-buried cutting groove is separated along the pre-buried cutting groove, wafer segmentation is independent bare die.
Optionally, the substrate under pre-buried cutting groove is separated along the pre-buried cutting groove, comprising:
Disintegrating tablet technique, machine cuts or laser cutting parameter are used in the segmentation.
Wafer provided in an embodiment of the present invention and its manufacturing method, dividing method, form pre- on the Cutting Road of wafer
Cutting groove is buried, which penetrates through from the upper surface of wafer into the substrate of segment thickness, in this way, carrying out wafer segmentation
When, segmentation that is thinned, and then realizing bare die on wafer can be carried out from the back side of wafer, without being cut or being reduced cutting
Intensity, it can the segmentation for realizing bare die on wafer greatly promotes cutting technique window, improves production efficiency.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the overlooking structure diagram of wafer according to an embodiment of the present invention；
Fig. 2 shows the local overlooking schematic diagrames of the regional area A1 in Fig. 1；
Fig. 2A show AA in Fig. 2 to diagrammatic cross-section；
The partial cutaway schematic of wafer during Fig. 3-4 is shown according to the application manufacturing method formation wafer；
Fig. 5-7 is shown be split according to the dividing method of the embodiment of the present application one during wafer part section
Schematic diagram；
Fig. 8-9 is shown be split according to the dividing method of the embodiment of the present application two during wafer part section
Schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, currently, mainly realizing wafer by machine cuts or laser cutting
Segmentation generally requires the multiple cutting that linear reciprocation is done along Cutting Road in cutting process, divides low efficiency, and the chip generated
It will cause a degree of pollution in chip surface, and damage subtle on wafer can all lead to disintegrating tablet, sliver occur when cutting
The problems such as, the process window of cutting is small.
For this purpose, being formd on the Cutting Road of wafer present applicant proposes a kind of wafer and its manufacturing method, dividing method
Pre-buried cutting groove, the pre-buried cutting groove are penetrated through from the upper surface of wafer into the substrate of segment thickness, in this way, carrying out wafer point
When cutting, segmentation that is thinned, and then realizing bare die on wafer can be carried out from the back side of wafer, is cut without being cut or being reduced
The intensity cut, it can the segmentation for realizing bare die on wafer greatly promotes cutting technique window, improves production efficiency.
This application provides a kind of wafers 10, with reference to shown in Fig. 1-Fig. 2A, comprising:
Substrate 12；
The bare die 100 of array arrangement on substrate 12 has Cutting Road 110 between the bare die 100；
There is pre-buried cutting groove 120, the pre-buried cutting groove 120 is passed through from the upper surface of wafer 10 on the Cutting Road 110
It passes in the substrate 12 of segment thickness, and the pre-buried cutting groove 120 extends to the two of wafer 10 along 110 direction of Cutting Road
Edge.
In the embodiment of the present application, wafer 10 has completed the processing technology of wafer stage, and wafer 10 includes 12 He of substrate
The bare die (DIE) 100 of array arrangement on substrate, bare die 100 be actual chip region, be formed with required device architecture with
And the interconnection structure of electrical connection structure.
Between bare die 100 be Cutting Road 110, Cutting Road 110 be in longitudinal and transverse arrangement, between the row of 100 array of bare die and
It is both provided with Cutting Road 110 between column, is not used to form actual device on Cutting Road 110, Cutting Road 110 is mainly used for naked
The segmentation of piece 100, in addition, can also form test structure and test pads 130 on Cutting Road 110, these structures are used for wafer
The monitoring of stage process technique.
In the embodiment of the present application, bare die 100 is arranged in array, it is to be understood that the array of bare die 100 is arranged in ranks
Cloth, but wafer 100 is generally circular, and therefore, the quantity for the bare die 100 arranged on every row or each column may be different.
With reference to shown in Fig. 2 and Fig. 2A, bare die 100 is actual chip region, is used to form device architecture and device architecture
Interconnection structure, device architecture may include active device and/or passive device, and active device may include MOS device, memory
Part or other semiconductor devices, memory device may include nonvolatile memory or random access memory etc., non-volatile memories
Device for example may include the floating gate fets such as NOR type flash memory, NAND-type flash memory or ferroelectric memory, phase transition storage
It may include resistance, inductively or capacitively etc. Deng, passive device, device architecture can be planar device or three-dimensional device, three-dimensional
Device for example can be FIN-FET (fin formula field effect transistor), three-dimensional storage etc..
Wherein, device architecture can be formed in first medium layer 20 and substrate 102, in one example, device junction
Structure includes MOS device, and device architecture includes in the gate dielectric layer on substrate, the grid on gate dielectric layer and grid two sides substrate
Source-drain area, grid and source-drain area cover by first medium layer 20, which can be interlayer dielectric layer, can have
Single or multi-layer structure, the material of dielectric layer may include silica, silicon nitride, silicon oxynitride or their combination.Mutually connection
Structure is used for the interconnection of device architecture, may include contact plug, via hole and interconnection layer, contact plug can be formed in first medium layer 20
In, for the extraction of grid and source-drain area, via hole and interconnection layer can be formed in second dielectric layer 30, the second dielectric layer
30 can be intermetallic dielectric layer, and according to the difference of the number of plies of interconnection layer, which can also have more accordingly
Layer structure, in specific application, interconnection layer may include one or more layers, and interconnection structure can be metal material, such as can be with
Including tungsten, aluminium, copper etc..It is understood that device architecture herein is merely illustrative, in different applications, device architecture can
With different structures.
Actual device architecture is not formed on Cutting Road 110, Cutting Road 110 is to be stacked with dielectric material on substrate 12
Region, which is to form the dielectric material deposited in device configuration process, with reference to shown in Fig. 2 and Fig. 2A, the medium
Material may include the second dielectric layer 30 on the first medium layer 20 and first medium layer 20 of covering device structure, and second
Dielectric layer 30 is used for the isolation of interconnection layer.
In addition, can also form test pads (Test Pad) 130 in Cutting Road 110, test pads 130 are mainly used for surveying
The measurement for trying structure, is monitored manufacturing process each in wafer manufacturing process by measurement result.In the embodiment of the present application,
Test pads 130 can be set in the Cutting Road 110 of pre-buried 120 side of cutting groove, in this way, pre-buried cutting groove can be avoided surveying
Cushion region is tried, and then pre-buried cutting groove can be formed by the etching technics in semiconductor fabrication process.
In the embodiment of the present application, pre-buried cutting groove 120 is also formed in Cutting Road 110, which is
Pre-buried structure in wafer cutting procedure, the pre-buried structure are used for the segmentation of bare die.The pre-buried cutting groove 120 and Cutting Road 110
Extending direction having the same extends to the two edges of wafer 10 along 110 direction of Cutting Road, where 10 surface of wafer
In plane, along 110 direction of Cutting Road in wafer 10, the present embodiment, pre-buried cutting groove 120 is also in longitudinal and transverse arrangement.
Perpendicular to the plane where 10 surface of wafer, which is penetrated through from the upper surface of wafer 10 to portion
Divide in the substrate 12 of thickness, and on the substrate 102 of Cutting Road 110 be dielectric material, can be the multilayered medium material of stacking, it should
Pre-buried cutting groove 120 is then for through the open slot of dielectric material 30,20 and the substrate 12 of segment thickness.Wherein, wafer 10
For upper surface finger-type at the surface of bare die 100, the surface opposite with the upper surface is then the lower surface of wafer 10, the following table of wafer 10
Face i.e. the back side of substrate 12.
In some embodiments of the application, the segmentation of bare die 100 is directly carried out by the pre-buried cutting groove 120, without
Mechanical or these external force of laser are cut to realize, therefore, smaller width can be arranged in Cutting Road 110, in this way, can save
The area of wafer arranges more bare dies 100, improves the integrated level of wafer.In some applications, the width model of Cutting Road 110
Enclosing for example to be 30 μm or so.
Compared to the processing dimension of device in bare die 100, the width of the width of cutting groove 110 and pre-buried cutting groove 120
All it is large scale, can use the etching technics in device fabrication and form the pre-buried cutting groove 120 in high quality, utilizes etching work
When skill forms large-sized pre-buried cutting groove, cell wall has straight and uniform pattern, while etch by-products are also easy to clear up,
Wafer will not be polluted.
In some embodiments of the application, the width of pre-buried cutting groove 120 can be the 15- of the width of cutting groove 110
50%, it can be 20%, 30%, 40% typically.In other embodiments of the application, the width of pre-buried cutting groove 120 can
Think 10-30 μm.
Furthermore, it is possible to which the depth that pre-buried cutting groove 120 is arranged according to specific application, in some embodiments, pre-buried
The height of 120 bottom surface of cutting groove to 10 lower surface of wafer can be the 80-90% of 10 thickness of wafer, typically, can for 82%,
85%, 88%, it can guarantee that substrate 12 still has certain support force under the thickness.In other embodiments of the application,
The height of the pre-buried cutting groove can be 50-200 μm, can when the range of the final goal thickness of wafer is 30-180 μm
Directly to carry out the segmentation of wafer using pre-buried cutting groove, required thickness when the final goal of the wafer is with a thickness of bare die encapsulation
Degree.Typically, the final goal thickness of wafer can for 90 μm, the height of pre-buried cutting groove can be 120 μm, wafer it is final
Target thickness can be able to be 50 μm for the height of 30 μm, pre-buried cutting groove.
The wafer of the embodiment of the present application is described in detail above, in addition, present invention also provides above-mentioned wafers
Manufacturing method, specific embodiment is described in detail below with reference to attached drawing.
In step S01, wafer 10 is provided, the wafer 10 includes the bare die of array arrangement on substrate 12 and substrate 12
100, there is Cutting Road 110, with reference to shown in Fig. 1 and Fig. 3 between the bare die 100.
In the embodiment of the present application, substrate 12 can be semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe
Substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elemental semiconductors or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other outer
Prolong structure, such as SGOI (silicon germanium on insulator) etc..
The wafer 10 has completed the device manufacturing process of wafer stage, and required device junction has been formed in bare die 100
Structure.
In step S02, pre-buried cutting groove 120 is formed in the Cutting Road 110, the pre-buried cutting groove 120 is from wafer
10 upper surface is penetrated through into the substrate 12 of segment thickness, and the pre-buried cutting groove 120 extends along 110 direction of Cutting Road
To the two edges of wafer 10, with reference to shown in Fig. 1 and Fig. 4.
In the embodiment of the present application, Cutting Road 12 can will be carved using the etching technics in semiconductor fabrication process
Erosion, thus, the pre-buried cutting groove 120 for being through to section substrate 12 is formed in Cutting Road 110, etching technics can be each for dry method
Anisotropy etching, such as can be plasma etching, reactive ion etching etc..
Specifically, refering to what is shown in Fig. 4, it is possible, firstly, to forming mask layer 40 on wafer 10, which can be light
Photoresist, or hard exposure mask, hard exposure mask can be for example silica, silicon nitride or silicon oxynitride or their lamination, this is covered
It is formed with the etched features of pre-buried cutting groove in film layer 40, can use photoetching technique for etched features and be transferred to photoresist layer
In, it can also be further by the pattern transfer in photoresist into hard exposure mask；In turn, it is masking with the mask layer 40, utilizes quarter
Etching technique carries out the etching of dielectric material 30,20 and substrate 12 in Cutting Road 110, and stops in substrate 12, retains part
The substrate 12 of thickness is not etched, thus, the pre-buried cutting groove 120 for being through to section substrate 12 is formed in Cutting Road 110；And
Afterwards, which is removed, with reference to shown in Fig. 2A, so far, forms the wafer of the embodiment of the present application.It is formed using etching technics
When large-sized pre-buried cutting groove, cell wall has straight and uniform pattern, while etch by-products are also easy to clear up, will not be right
Wafer pollutes.
In addition, present invention also provides may not need and cut in some embodiments using the dividing method of above-mentioned wafer
It cuts, the segmentation of bare die is directly realized using pre-buried cutting groove, specific embodiment is carried out below with reference to attached drawing 5-7 detailed
Description.
In step S101, wafer 10 is provided, cutting is pasted on the upper surface of the wafer 10, protective film 200, ginseng is thinned
It examines shown in Fig. 1 and Fig. 5.
Wafer 10 is the wafer of above-described embodiment description, is provided with pre-buried cutting groove 120 in the Cutting Road 110 of wafer 100,
This is thinned protective film 200 and is used to that the protection and fixation in cutting procedure to wafer and bare die 100 to be thinned, and protective film 200 is thinned in this
It can be the film with adhesive layer, such as can be glue film, the upper surface that protective film 200 is covered in whole wafer is thinned in this
On.
In step S102, carried out from the lower surface of wafer 10 it is thinned, until the pre-buried cutting groove 120, by wafer 10
Segmentation is independent bare die 100, with reference to shown in Fig. 1 and Fig. 6.
Being thinned for substrate 12 is carried out from the back side of the lower surface of wafer 10, that is, substrate 12, thinned thickness can wait
In or greater than pre-buried cutting groove 120 through the thickness of substrate 12, that is, pre-buried cutting groove 120 just it has been thinned to or has crossed pre-buried
Cutting groove 120, in this way, after thinning, the substrate 12 under pre-buried cutting groove 120 between bare die 100 is removed, pre- by this
It is just that bare die 100 is separated to bury cutting groove 120, becomes mutually independent bare die 100.
In some embodiments, the altitude range of pre-buried cutting groove can be 50-200 μm in the wafer before being thinned, and subtract
The thickness range of the wafer after thin can be 30-180 μm.
Specifically, being thinned for substrate 12 can be carried out using chemical mechanical grinding or acid system corrosion, it can also be using twice
Reduction process first uses chemical mechanical grinding be thinned for the first time, this time thinned with thinned rate then can faster
Be thinned for the second time to use acid system to corrode, this time thinned with slower rate, but thinned surface can be made to have
Better flatness.
Later, step S103 can also be carried out, cutting film 210 is pasted on the lower surface of wafer 10 after singulation, and go
Except the thinned protective film 200；It carries out the cold of cutting film 210 and collapses technique, so that the spacing 130 between individual die 100 increases, ginseng
It examines shown in Fig. 7.
Carrying out thinned and after being thinned to pre-buried cutting groove 120, bare die 100 becomes independent individual, after singulation
Cutting film 210 is pasted in the lower surface of wafer 10, which is fixed in cutting film 210, subsequent to pass through pickup (pick)
After bare die 100, it is further encapsulated as chip-packaging structure.The cutting film 210 is used for the fixation of bare die, can be for bonding
The film of layer.Due to spacing 130 of the region between bare die 100 of pre-buried cutting groove 120 former between these 100 individuals of bare die,
In some embodiments, the width of the pre-buried cutting groove 120 of the original is smaller, can be conducive to the effective area for saving wafer, improve
The integrated level of device is based on this, can further expand the spacing 130, it is thus possible to be conducive to subsequent bare die 100
Pickup.
Specifically, technique can be collapsed using cold, is collapsed in technique cold, wafer is placed in low temperature environment, the low temperature environment
Usually less than room temperature, and make cutting film 200 along wafer radius outwardly direction stress F, thus, so that cutting film 210 stretches
Deformation, so that the spacing 130 between individual die 100 increases, refering to what is shown in Fig. 7, in this way, without occupying Cutting Road, i.e. wafer
Effective area, and make spacing 130 between individual die 100 bigger, convenient for it is subsequent can accurately pick up bare die 100 carry out it is subsequent
Packaging technology.
In these embodiments, without cutting, the segmentation of bare die is directly realized using pre-buried cutting groove, external force is avoided to cut
Caused by wafer sliver the problems such as, greatly improve the process window of division process, also improve production efficiency, also avoid simultaneously
To the pollution of wafer in cutting process.
In further embodiments, it can use the segmentation that pre-buried cutting groove realizes bare die by part cutting, below will
Specific embodiment is described in detail in conjunction with attached drawing 8-9.
In step S201, wafer 10 is provided, with reference to shown in Fig. 1 and Fig. 8.
Wafer 10 is the wafer of above-described embodiment description, is provided with pre-buried cutting groove 120 in the Cutting Road 110 of wafer 100,
Protective layer 210 is also provided on the upper surface of the wafer 10, the protective layer 210 is for avoiding crystalline substance in subsequent reduction process
The upper surface of circle 10 is damaged, which can be the film with adhesive layer, such as can be glue film, the protection
Layer 210 is covered on the upper surface of whole wafer.
In step S202, carried out from the lower surface of wafer 10 thinned, and thinned thickness is less than pre-buried 120 bottom surface of cutting groove
To the thickness of 10 lower surface of wafer, with reference to shown in Fig. 8.
Being thinned for substrate 12 is carried out from the back side of the lower surface of wafer 10, that is, substrate 12, thinned thickness is smaller than
Pre-buried cutting groove 120 does not run through the thickness of substrate 12, in this way, after thinning, also remaining with the pre-buried cutting between bare die 100
The substrate 12 of segment thickness under slot 120 facilitates in this way, just reducing the thickness of the subsequent substrate for needing further exist for cutting
Divide the raising of efficiency.
Same above-described embodiment, specifically, being thinned for substrate 12 can be carried out using chemical mechanical grinding or acid system corrosion, or
The method that both persons combine carries out being thinned for substrate 12.
In step S203, the segmentation of wafer 10 is independent bare die 100 along the pre-buried cutting groove 120, with reference to Fig. 9 institute
Show.
Since reduction process has been carried out, so that the thickness of the substrate 12 under pre-buried cutting groove 120 substantially reduces, and
Afterwards, the substrate under pre-buried cutting groove need to only be separated using pre-buried cutting groove 120, it can realize the segmentation of wafer 10, this
Sample, it is possible to reduce the intensity of segmentation effectively improves cutting technique window, and improves production efficiency, simultaneously as the intensity of segmentation
The substrate portions for reducing and only not removed with segmentation, effectively reduce the pollution caused by wafer in division process.
In specific application, in division process, it is possible, firstly, to paste cutting film on the lower surface of wafer 10, (figure is not
It shows) for the cutting film for the fixation in cutting procedure to wafer and bare die 100, which can be for adhesive layer
Film, such as can be glue film, which is covered on the lower surface of whole wafer.It then, can be by table on wafer 10
Protective layer 210 on face removes, and using the segmentation of pre-buried cutting groove 120 progress wafer 10, when segmentation, can use disintegrating tablet work
Skill, machine cuts or laser cutting parameter.Wherein, disintegrating tablet technique is the crystal orientation sliver using substrate and the segmentation carried out, will not
Generate any cutting pollution, meanwhile, notch is more neat, division process it is more efficient.
In addition, can also carry out the cold of cutting film with the step S103 of above-described embodiment and collapse technique, so that between individual die
Spacing increase.
In the present embodiment, substrate is thinned from the back side of wafer, it, can be with when being split using pre-buried cutting groove
The intensity for effectively reducing segmentation effectively improves cutting technique window, and improves production efficiency, meanwhile, effectively reduce division process
In polluted caused by wafer.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and the highlights of each of the examples are differences from other embodiments.Especially for manufacturer
For method embodiment, since it has part similar with crystal circle structure embodiment, so describe fairly simple, related place
Illustrate referring to the part of embodiment of the method.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (12)
1. a kind of wafer characterized by comprising
Substrate；
The bare die of array arrangement on substrate has Cutting Road between the bare die；
There is pre-buried cutting groove, the pre-buried cutting groove is penetrated through from the upper surface of wafer to the lining of segment thickness on the Cutting Road
In bottom, and the pre-buried cutting groove extends to the two edges of wafer along the Cutting Road direction.
2. wafer according to claim 1, which is characterized in that the width of the pre-buried cutting groove is the width of the cutting groove
The 15-50% of degree.
3. wafer according to claim 1, which is characterized in that the width of the pre-buried cutting groove is 10-30 μm.
4. wafer according to claim 1, which is characterized in that further include: the Cutting Road in the pre-buried cutting groove side
In test pads.
5. wafer described in any one of -4 according to claim 1, which is characterized in that the pre-buried cutting groove bottom to the crystalline substance
The height of circle lower surface is the 80-90% of the wafer thickness.
6. a kind of manufacturing method of wafer characterized by comprising
Wafer is provided, the wafer includes the bare die of array arrangement on substrate and substrate, has Cutting Road between the bare die；
Pre-buried cutting groove is formed in the Cutting Road, the pre-buried cutting groove is penetrated through from the upper surface of wafer to segment thickness
In substrate, and the pre-buried cutting groove extends to the two edges of wafer along the Cutting Road direction.
7. manufacturing method according to claim 6, which is characterized in that described to form pre-buried cutting on the Cutting Road
Slot, comprising:
The Cutting Road is performed etching using etching technics, to form pre-buried cutting groove on the Cutting Road.
8. a kind of wafer dividing method, which is characterized in that the dividing method includes:
Wafer according to any one of claims 1 to 5 is provided, thinned protective film is pasted on the upper surface of the wafer；
It is carried out from the lower surface of wafer thinned, until the pre-buried cutting groove, wafer segmentation is independent bare die.
9. dividing method according to claim 8, which is characterized in that the height of pre-buried cutting groove in the preceding wafer is thinned
Range is 50-200 μm, and the thickness range of the wafer after being thinned is 30-180 μm.
10. dividing method according to claim 8, which is characterized in that further include:
It carries out the cold of cutting film and collapses technique, so that the spacing between individual die increases.
11. a kind of wafer dividing method, which is characterized in that the dividing method includes:
Such as wafer of any of claims 1-6 is provided；
The thickness that thinned and thinned thickness is less than pre-buried cutting groove bottom to wafer lower surface is carried out from the lower surface of wafer；
The substrate under pre-buried cutting groove is separated along the pre-buried cutting groove, wafer segmentation is independent bare die.
12. dividing method according to claim 11, which is characterized in that will be under pre-buried cutting groove along the pre-buried cutting groove
Substrate separate, comprising:
Disintegrating tablet technique, machine cuts or laser cutting parameter are used in the segmentation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111226313A (en) * | 2020-01-07 | 2020-06-02 | 长江存储科技有限责任公司 | Method for stacking and cutting polycrystalline circles |
| CN112885923A (en) * | 2020-08-12 | 2021-06-01 | 北京绿波静心新能源科技有限公司 | Silicon solar cell preparation method, silicon wafer and silicon solar cell |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120020944A (en) * | 2010-08-31 | 2012-03-08 | 오름반도체 주식회사 | Dicing method of semiconductor device |
| CN104979187A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for dividing wafer |
| CN107546175A (en) * | 2016-06-28 | 2018-01-05 | 台湾积体电路制造股份有限公司 | Split the method for wafer |
| CN108122838A (en) * | 2017-12-13 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | Semiconductor device fabrication processes |
-
2019
- 2019-06-24 CN CN201910549571.3A patent/CN110265475A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120020944A (en) * | 2010-08-31 | 2012-03-08 | 오름반도체 주식회사 | Dicing method of semiconductor device |
| CN104979187A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for dividing wafer |
| CN107546175A (en) * | 2016-06-28 | 2018-01-05 | 台湾积体电路制造股份有限公司 | Split the method for wafer |
| CN108122838A (en) * | 2017-12-13 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | Semiconductor device fabrication processes |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111226313A (en) * | 2020-01-07 | 2020-06-02 | 长江存储科技有限责任公司 | Method for stacking and cutting polycrystalline circles |
| US11710717B2 (en) | 2020-01-07 | 2023-07-25 | Yangtze Memory Technologies Co., Ltd. | Methods for multi-wafer stacking and dicing |
| CN112885923A (en) * | 2020-08-12 | 2021-06-01 | 北京绿波静心新能源科技有限公司 | Silicon solar cell preparation method, silicon wafer and silicon solar cell |
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Application publication date: 20190920 |