CN113437075B

CN113437075B - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN113437075B
Application number: CN202110687113.3A
Authority: CN
Inventors: 张坤; 周文犀; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2022-07-29
Anticipated expiration: 2041-06-21
Also published as: CN113437075A

Abstract

The application provides a three-dimensional memory and a manufacturing method thereof. The method comprises the following steps: providing a first substrate; sequentially forming a sacrificial layer and a laminated structure on the first substrate; forming a channel structure extending through the stacked structure and into the sacrificial layer, the channel structure including a memory film and a channel layer; etching to remove the first substrate, the sacrificial layer and part of the storage film so as to expose part of the channel layer; forming a doped semiconductor layer and a buffer layer in sequence, wherein the doped semiconductor layer is in contact with the channel layer; carrying out planarization treatment on the buffer layer; a source contact is formed through the buffer layer and extending into the doped semiconductor layer. The three-dimensional memory of the present application has high integration and enhanced reliability.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor manufacturing technologies, and in particular, to a three-dimensional memory and a method for manufacturing the same.

Background

With the rapid development of the electronics industry, there is an increasing demand for high-performance low-cost semiconductor devices. The degree of integration of a conventional two-dimensional or planar memory is mainly determined by the area occupied by a unit memory cell. Therefore, the degree of integration of the conventional two-dimensional memory is greatly affected by the fine pattern forming technology. However, increasing the fineness of the pattern requires relatively expensive process equipment, which poses a great limitation in increasing the integration of the two-dimensional memory.

To overcome such limitations, three-dimensional memories have been developed that can increase the reliability of memory devices while significantly improving the integration of the memory devices.

Disclosure of Invention

In view of the above, it is a primary object of the present application to provide a three-dimensional memory with enhanced reliability and a method for fabricating the same.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

a first aspect of the present application provides a method of manufacturing a three-dimensional memory, the method comprising:

providing a first substrate;

sequentially forming a sacrificial layer and a laminated structure on the first substrate;

forming a channel structure extending through the stacked structure and into the sacrificial layer, the channel structure including a memory film and a channel layer;

etching to remove the first substrate, the sacrificial layer and part of the storage film so as to expose part of the channel layer;

forming a doped semiconductor layer and a buffer layer in sequence, wherein the doped semiconductor layer is in contact with the channel layer;

carrying out planarization treatment on the buffer layer;

a source contact is formed through the buffer layer and extending into the doped semiconductor layer.

According to one embodiment of the present application, the source contact is in contact with the channel layer.

According to an embodiment of the present application, the forming a source contact through the buffer layer and extending into the doped semiconductor layer includes:

etching the buffer layer and the doped semiconductor layer to form a source contact opening;

and filling a conductive material in the source contact opening to form a source contact.

According to one embodiment of the present application, a depth of a portion of a bottom surface of the source contact opening overlapping a region where the channel layer is located is smaller than a depth of a portion not overlapping the region where the channel layer is located.

According to one embodiment of the present application, the sequentially forming a doped semiconductor layer and a buffer layer includes:

forming a doped semiconductor layer by an in-situ growth process;

depositing a buffer layer on the doped semiconductor layer;

the doped semiconductor layer includes a flat portion and a protruding portion extending into the buffer layer.

According to an embodiment of the present application, before forming the doped semiconductor layer, the method further comprises:

and carrying out ion implantation on the exposed part of the channel layer to form a doped channel layer.

In accordance with an embodiment of the present application, prior to forming the buffer layer, the method further comprises:

And activating the doped channel layer and the doped semiconductor layer to enable the doping concentration of the doped channel layer and the doping concentration of the doped semiconductor layer to be the same.

According to an embodiment of the present application, before the etching removes the first substrate and the sacrificial layer and a part of the storage film, the method further includes:

providing a second substrate, wherein a peripheral circuit and a second bonding layer formed on the peripheral circuit are formed on the second substrate;

a first bonding layer is formed on the laminated structure;

bonding the first bonding layer and the second bonding layer.

According to an embodiment of the present application, etching the buffer layer and the doped semiconductor layer to form a source contact opening includes:

etching the buffer layer and the doped semiconductor layer to form a source contact opening and simultaneously forming a contact opening;

the contact opening penetrates through the buffer layer and the doped semiconductor layer.

According to an embodiment of the present application, filling a conductive material in the source contact opening to form a source contact includes:

filling conductive material in the contact opening and the source contact opening to form a contact and a source contact;

The contact contacts an end of the peripheral contact.

A second aspect of the present application provides a three-dimensional memory comprising:

the buffer layer, the doped semiconductor layer and the laminated structure are arranged in sequence;

a channel structure extending through the stack structure and into the doped semiconductor layer; the channel structure comprises a storage film and a channel layer;

a source contact extending through the buffer layer and into the doped semiconductor layer.

According to one embodiment of the present application, a depth of a portion of the source contact overlapping a region of the channel layer is smaller than a depth of a portion of the source contact not overlapping the region of the channel layer.

According to an embodiment of the present application, the three-dimensional memory further comprises:

a second substrate having a peripheral circuit formed thereon.

According to one embodiment of the present application, the channel layer includes a doped channel layer including a portion in the doped semiconductor layer and a portion in the stacked structure.

According to one embodiment of the present application, the doping concentrations of the doped channel layer and the doped semiconductor layer are the same.

According to an embodiment of the present application, further comprising: a contact extending through the buffer layer and the doped semiconductor layer, wherein the contact is in contact with an end of a peripheral contact.

According to one embodiment of the present application, the doped semiconductor layer includes a flat portion and a protruding portion extending into the buffer layer.

A third aspect of the present application provides a three-dimensional memory comprising:

the buffer layer, the doped semiconductor layer, the laminated structure and the first bonding layer are arranged in sequence;

a source contact extending through the buffer layer and into the doped semiconductor layer;

a second substrate on which a peripheral circuit is formed and on which a second bonding layer is formed;

and the first bonding layer and the second bonding layer are in bonding connection.

Compared with the prior art, the three-dimensional memory has the advantages of high integration level and enhanced reliability.

Drawings

Fig. 1-12 are fabrication processes for forming a three-dimensional memory according to some embodiments of the present application;

FIG. 13 is a side view in cross-section of an exemplary three-dimensional memory according to one embodiment of the present application;

FIG. 14 is a flow chart of a method of fabricating an exemplary three-dimensional memory according to some embodiments of the present application;

the figure includes: 100-a first semiconductor structure; 101-a first substrate; 102-a first bonding layer; 103-a sacrificial layer; 104 a laminated structure; 105-a conductive layer; 106-an insulating layer; 107-peripheral contacts; 108-a contact; 109-a virtual channel structure; 110-channel structure; 111-a channel layer; 112-a tunneling layer; 113-a storage layer; 114-a barrier layer; 115-doped semiconductor layer; 116-a contact; 117-source contact; 118-a buffer layer; 119-a third interconnect layer; 120-a first bonding contact; 121-interlayer sacrificial layer; 122-a gap; 123-contact opening; 124-source contact opening; 200-a second semiconductor structure; 201-a second substrate; 202-a second bonding layer; 203-second bonding contact.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the embodiments of the present invention and the accompanying drawings, and obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

The term "substrate" herein refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added to the substrate may be patterned or may remain unpatterned.

The term "layer" herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Further, a layer may be a region of a continuous structure, homogenous or non-homogenous, having a thickness less than the continuous structure.

The term "three-dimensional memory" herein refers to a semiconductor device having a vertically oriented memory cell transistor string on a substrate that is laterally oriented such that the memory string extends in a vertical direction relative to the substrate.

The term "interconnect layer" herein may include any suitable type of interconnect, which may be exemplified by intermediate-process (MEOL) interconnects, and back-end-of-line (BEOL) interconnects. The "interconnect layer" may include a plurality of interconnects, including lateral interconnect lines and vertical interconnect contacts. That is, the interconnect layer may include interconnect lines and interconnect contacts in the plurality of layers of dielectric material. The interconnect lines and interconnect contacts in the interconnect layer may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The dielectric material layer in the interconnect layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Fig. 1-12 are fabrication processes for forming a three-dimensional memory according to some embodiments of the present application. FIG. 14 illustrates a flow chart of a method of fabricating an exemplary three-dimensional memory according to some embodiments of the present disclosure. As shown in fig. 14, in step 1401, a first substrate is provided; in step 1402, a sacrificial layer and a stack structure are sequentially formed on the first substrate.

As shown in fig. 1, a sacrificial layer 103 is formed on a first substrate 101, and insulating layers 106 and interlayer sacrificial layers 121 alternately stacked are formed on the sacrificial layer 103. The alternately stacked insulating layers and interlayer sacrificial layers are referred to herein as a stacked structure.

The first substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like, among others. It should be appreciated that the first substrate may be part of a pseudo wafer (e.g., a carrier substrate) composed of any suitable material to reduce the cost of the first substrate, such as glass, sapphire, plastic, silicon, to name a few, as the first substrate is to be removed from the final product.

Wherein the sacrificial layer will be removed in a subsequent process step, the sacrificial layer here may comprise any suitable sacrificial material. In some embodiments, the sacrificial layer may comprise an insulating material, such as silicon oxide or silicon nitride. According to some embodiments, to form the sacrificial layer, one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, may be used to deposit silicon oxide or silicon nitride on the first substrate.

In some embodiments, the interlayer sacrificial layers and the insulating layers are alternately deposited on the sacrificial layers, and the alternately stacked interlayer sacrificial layers and insulating layers may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Referring to fig. 2, a stepped structure may be formed on edges of the alternately stacked interlayer sacrificial layers 121 and insulating layers 106. The stepped structure may be formed by performing a "trim-etch" cycle on the plurality of insulating layers 106 and the interlayer sacrificial layer 121 toward the first substrate 101.

As shown in fig. 14, in step 1403, a channel structure is formed through the stacked structure and extending into the sacrificial layer, the channel structure including a memory film and a channel layer. As shown in fig. 2, a channel structure 110 vertically extending through the alternately stacked interlayer sacrificial layer 121 and insulating layer 106 and sacrificial layer 103 is formed. In some embodiments, to form the channel structure 110, the channel structure 110 vertically extending through the alternately stacked interlayer sacrificial layers 121 and insulating layers 106, stopping within the sacrificial layer 103, is etched, and the memory film and the channel layer 111 are sequentially deposited along the sidewalls of the channel structure 110.

In some embodiments, the fabrication process for the formed channel structure includes wet etching and/or dry etching. The sacrificial layer may act as an etch stop layer for controlling the variation of the trenching between different channel structures. For example, the etching of the channel structure may be stopped by the sacrificial layer without extending further into the first substrate. That is, according to some embodiments, the lower end of each channel structure is between the top and bottom surfaces of the sacrificial layer.

Still referring to fig. 2, on the sidewall and bottom surface of the channel structure 110, a blocking layer 114, a memory layer 113, a tunneling layer 112, and a channel layer 111 may be sequentially deposited in order. In some embodiments, a barrier layer, a memory layer, and a tunneling layer may be sequentially deposited on the sidewalls and bottom surface of the channel structure using one or more thin film deposition processes, such as PVD, CVD, ALD, any other suitable process, or combinations thereof, to form a memory film. In one example, the channel structure may be cylindrical. The storage film includes a blocking layer, a storage layer, and a tunneling layer radially inward of the channel structure. Then, deposition of, for example, polysilicon may continue on the tunneling layer to form the channel layer using one or more thin film deposition processes, such as PVD, CVD, ALD, any other suitable process, or combinations thereof. In some embodiments, the remaining space of the channel structure may be partially or completely filled with a capping layer comprising an insulating material and/or an air gap.

Wherein the barrier layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. In one example, the memory film may include a silicon oxide/silicon oxynitride/silicon oxide (ONO) composite layer. The channel layer may include, for example, amorphous silicon, polycrystalline silicon, or single crystal silicon, among others.

With further reference to fig. 2, the three-dimensional memory is further provided with a dummy channel structure 109, and the dummy channel structure 109 and the channel structure 110 may be formed simultaneously to improve the etching morphology of the channel structure 110. The material of the dummy channel structure may be the same as or different from the material of the channel structure. Here, the material of the dummy channel structure is different from that of the channel structure, and the dummy channel structure is filled with an insulating material. The dummy channel structure can also play a role in supporting, and the collapse of the laminated structure is avoided. In one example, the dummy channel structure may be cylindrical.

As shown in fig. 3, the slit 122 is an opening vertically extending through the alternately stacked interlayer sacrificial layers and insulating layers 106. In some embodiments, wet etching and/or dry etching may be used to form the gap. In some embodiments, the gap is formed for the purpose of performing a "gate replacement" process, by injecting an etchant, e.g., an etching gas and/or liquid, into the gap to remove the stacked interlayer sacrificial layers such that lateral grooves are formed alternating between the insulating layers. Wherein the etchant may be any appropriate etchant as long as the etchant can remove the interlayer sacrificial layer without etching the insulating layer.

Still referring to fig. 3, a conductive layer 105 is deposited into the lateral grooves through the gap 122. In some embodiments, the conductive layer may be deposited using one or more thin film deposition processes, such as PVD, CVD, ALD, any other suitable process, or combinations thereof. In one example, the conductive layer may be a metal layer, such as tungsten. Here, a stacked structure in which conductive layers and insulating layers are alternately stacked is formed, that is, the conductive layers 105 and the insulating layers 106 in the stacked structure 104 may alternate in the vertical direction. That is, each conductive layer may be adjacent to two insulating layers on both sides, and each insulating layer may be adjacent to two conductive layers on both sides, except for the layer located at the bottom or top of the stacked structure. The alternately stacked insulating layers and conductive layers are also referred to herein as a stacked structure.

With further reference to fig. 3, after the formation of the stacked structure 104, an insulating material may be deposited inside the gap 122 to fill the opening. In some embodiments, one or more insulating materials may be filled into the gaps to form insulating structures using one or more thin film deposition processes, such as PVD, CVD, ALD, any other suitable process, or a combination thereof. In one example, the insulating structure may have an air gap.

As shown in fig. 3 and 4, the stacked structure 104 may include a step region and a core region. In the step region, a plurality of insulating layers and a plurality of conductive layers are alternately stacked to form a plurality of steps. The channel structure is located in the core region. The three-dimensional memory may also form a peripheral contact 107, the peripheral contact 107 may extend vertically into the sacrificial layer 103, and the depth of the peripheral contact 107 may be greater than the thickness of the stacked structure. Further, the three-dimensional memory may also form a contact 108, and one end of the contact 108 is in contact with the conductive layer 105 at the step of the step region of the stacked-layer structure 104.

As shown in fig. 5, the first substrate 101, the sacrificial layer 103, and the stacked structure, which are stacked, and the channel structure 110 which penetrates through the stacked structure and extends into the sacrificial layer 103, are the first semiconductor structure 100. The three-dimensional memory of the present application may include a first semiconductor structure 100 and a second semiconductor structure 200 bonded to each other. The first semiconductor structure 100 and the second semiconductor structure 200 may be bonded in a "face-to-face" fashion, i.e., the first substrate 101 is at the top of the three-dimensional memory and the second substrate 201 is at the bottom of the three-dimensional memory.

Specifically, the second semiconductor structure 200 includes a second substrate 201, and peripheral circuits formed on the second substrate 201. The second substrate may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

Wherein the peripheral circuit is used for controlling and sensing the three-dimensional memory. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for facilitating operation of the three-dimensional memory, including but not limited to page buffers, decoders, sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive component of the circuitry. The peripheral circuit may include a transistor formed over the second substrate, where the transistor may be formed in whole or in part over the second substrate.

In some embodiments, the second semiconductor structure of the three-dimensional memory further includes a second interconnect layer (not shown in fig. 5) located above the peripheral circuit, the second interconnect layer being used to pass electrical signals of the peripheral circuit, i.e., to input the electrical signals to the peripheral circuit or to output the electrical signals of the peripheral circuit. The second interconnect layer may include one or more interlayer insulating layers in which both interconnect lines and contacts may be formed, i.e., the second interconnect layer may include a plurality of interconnect lines and contacts in the interlayer insulating layers. In particular, both the interconnect lines and the contacts in the interconnect layer may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlayer insulating layer may include an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in fig. 5, the second semiconductor structure 200 further includes a second bonding layer 202, the second bonding layer 202 being above the second interconnect layer and the peripheral circuitry. The second bonding layer 202 may include a plurality of second bonding contacts 203 and an insulating material electrically isolating the second bonding contacts 203. The second bonding contact may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the second bonding contacts may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

With further reference to fig. 5, the first semiconductor structure 100 further includes a first bonding layer 102, the first bonding layer 102 being above a second bonding layer 202 of the second semiconductor structure 200. The first bonding layer may also include a plurality of first bonding contacts 120 and an insulating material that electrically isolates the first bonding contacts 120. The first bonding contact may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the first bonding contact may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Similarly, first semiconductor structure 100 further includes a first interconnect layer (not shown in fig. 5) located above first bonding layer 102, which may be used to pass electrical signals. The first interconnection layer may include one or more interlayer insulating layers in which both interconnection lines and contacts may be formed, i.e., the second interconnection layer may include a plurality of interconnection lines and contacts in the interlayer insulating layers. In particular, both the interconnect lines and the contacts in the interconnect layer may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlayer insulating layer may include an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, the first semiconductor structure and the second semiconductor structure may be bonded by metal fusion bonding. Of course, in some embodiments, the first semiconductor structure and the second semiconductor structure may be bonded by non-metal bonding, including but not limited to using an adhesive or the like. In some embodiments, a bonding layer may also be formed between the first semiconductor structure and the second semiconductor structure by hybrid bonding, i.e., metal/non-metal hybrid bonding. That is, a metal bond is formed between the first bonding contact and the second bonding contact, a non-metal bond is formed between the insulating materials for electrically isolating the first/second bonding contacts, a bonding layer having a certain thickness is formed between the first semiconductor structure and the second semiconductor structure without using an adhesive, and the metal-metal bond and the non-metal-non-metal bond can be simultaneously obtained.

With further reference to fig. 5, after the first and

second semiconductor structures

100 and 200 are bonded to each other, the peripheral contact 107 may also be electrically connected to peripheral circuitry of the second semiconductor structure 200 through a bonding layer (including the first and second bonding layers). The contacts 108 have one ends respectively contacting the conductive layers at the steps of the step regions of the stacked structure, and the other ends electrically connected to the peripheral circuits of the second semiconductor structure 200 through bonding layers (including a first bonding layer and a second bonding layer).

As shown in fig. 14, in step 1404, the first substrate and the sacrificial layer and a portion of the storage film are etched away to expose a portion of the channel layer. As shown in fig. 5 and 6, an operation of removing the first substrate 101 and the sacrifice layer 103 is performed from the back surface of the first substrate 101. A sacrificial layer and a stacked structure are formed on the front surface of the first substrate. And respectively removing the first substrate and the sacrificial layer through a wet etching process to expose the part of the channel structure corresponding to the sacrificial layer. Due to the selectivity of the wet etching process, only the first substrate and the sacrificial layer can be etched and removed, and the virtual channel structure cannot be etched. That is, the top surface of the three-dimensional memory at this time exhibits an uneven shape. In some embodiments, the first substrate may be removed by peeling the first substrate. The sacrificial layer may then be selectively removed by wet etching with an appropriate etchant (e.g., hydrofluoric acid) without etching the underlying stack. As described above, since the channel structure does not extend beyond the sacrificial layer into the first substrate, removal of the first substrate does not affect the channel structure. The removal of the sacrificial layer may expose a portion of the channel structure corresponding to the sacrificial layer. In some embodiments where the channel structure extends into the sacrificial layer, the selective etching of the sacrificial layer comprising silicon oxide also removes portions of the barrier layer comprising silicon oxide above the top surface of the stack structure, but the memory layer comprising silicon nitride and other layers (e.g., tunneling layers) surrounded by the memory layer remain intact.

Further, since a portion of the channel structure corresponding to the sacrificial layer is exposed at this time, the exposed memory film of the channel structure may be removed by a wet etching process, thereby exposing a portion of the channel layer of the channel structure corresponding to the sacrificial layer. As described above, the channel structure includes the blocking layer, the storage layer, the tunneling layer, and the channel layer in order from outside to inside along the radial direction of the cylinder. In some embodiments, the blocking layer, the memory layer, and the tunneling layer of the portion of the channel hole corresponding to the sacrificial layer may be selectively removed by a wet etching process without etching the channel layer. The etching of the memory film may also be controlled by controlling the etching time and/or the etching rate such that the etching does not continue to affect the remaining portion of the memory film surrounded by the stack structure. In some embodiments, the memory layer comprising silicon nitride is selectively removed using a wet etch with a suitable etchant such as phosphoric acid, without etching the tunneling layer and the channel layer. And removing the tunneling layer surrounding the channel layer of the part of the channel structure corresponding to the sacrificial layer. In some embodiments, the tunneling layer comprising silicon oxide is selectively removed using a wet etch with a suitable etchant such as hydrofluoric acid, without etching the channel layer comprising polysilicon.

As shown in fig. 7, in some embodiments, the channel layer 111 within the channel structure may be ion implanted to form a doped channel layer (as shown by the dashed box in fig. 7). The doped channel layer is partially located in the stack structure. In the ion implantation process, dopant ions are implanted into the channel layer in the form of ion beams, and the energetic ions lose energy due to collisions with electrons and atomic nuclei in the channel layer and finally stop at a certain depth within the crystal lattice. The dashed box in fig. 7 represents the depth of the doped channel layer. It should be noted that, in the present application, the channel layer is doped by using an ion implantation process, and the doping depth is the ion implantation depth. Different doping depths, doping concentrations or doping impurity profiles can be set according to the actual requirements of the three-dimensional memory. The doping depth can be controlled by adjusting the acceleration energy of the ion beam, and the doping concentration, i.e., the impurity dose, can be controlled by monitoring the ion current during implantation. Therefore, the doping is carried out by adopting the ion implantation process, the doping concentration, the doping depth and the doping impurity distribution can be more accurately controlled, and the repeatability is realized.

The channel layer includes a doped channel layer and an undoped channel layer, wherein a portion of the doped channel layer is located in the stacked structure and the undoped channel layer is entirely located in the stacked structure. In some embodiments, a length of a portion of the doped channel layer in the stacked structure is less than a thickness of the stacked structure.

The doped channel layer may be an N-type doped channel layer. In particular, the N-type doped channel layer may include, for example, polysilicon, monocrystalline silicon, or amorphous silicon. The N-type doped channel layer may include a channel doped with a pentavalent impurity element such As phosphorus (P), arsenic (As), or antimony (Tb) As an N-type dopant. Only four valence electrons in the pentavalent impurity atom can form covalent bonds with valence electrons in four surrounding semiconductor atoms, and the redundant one valence electron is easy to form free electrons because of no covalent bond constraint. Thus, the N-type doped channel layer is capable of providing free electrons. In some embodiments, an ion implantation process is employed to dope the channel layer with any appropriate N-type dopant to a desired doping depth and doping concentration.

As shown in fig. 14, in step 1405, a doped semiconductor layer and a buffer layer are sequentially formed, the doped semiconductor layer being in contact with the channel layer. Still referring to fig. 7, a doped semiconductor layer 115 is formed on top of the three-dimensional memory, the doped semiconductor layer 115 covering a portion of the channel layer of the channel structure 110 corresponding to the sacrificial layer and the stacked-layer structure. In the etching process steps, the portion of the channel structure corresponding to the sacrificial layer protrudes from the stacked structure (the portion of the dummy channel structure corresponding to the sacrificial layer also protrudes from the stacked structure), so that the top surface of the three-dimensional memory has an uneven shape, and the surface of the doped semiconductor layer has an uneven shape. So that the interface between the doped semiconductor layer and the buffer layer is not flat. The doped semiconductor layer can be an N-type doped semiconductor layer. Specifically, the N-type doped semiconductor layer may include, for example, polycrystalline silicon, monocrystalline silicon, or amorphous silicon. In some embodiments, the polysilicon covering the portion of the channel structure corresponding to the sacrificial layer and the stack structure may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with N-type dopants using an ion implantation process. In a more preferred embodiment, an in-situ growth process may be used to form the doped semiconductor layer.

Specifically, the doped channel layer includes a portion located in the doped semiconductor layer, and a portion located in the stacked structure. Still referring to fig. 7, as previously described, the exposed portion of the channel structure corresponding to the sacrificial layer of the memory film (including the barrier layer, the memory layer and the tunneling layer radially inward) has been removed by a wet etch process, at which point the portion of the channel structure in the doped semiconductor layer includes only the doped channel layer. If the doping concentrations in the doped channel layer and the doped semiconductor layer are different, this is likely to result in different magnitudes of GIDL current for different memory cells on a memory string even if the different memory cells on the same channel (i.e., memory string) have the same drain-gate voltage (i.e., GIDL voltage). In some embodiments, to ensure that substantially the same magnitude of GIDL current is achieved for each memory cell on a memory string, it may be necessary to intentionally form GIDL voltages of different magnitudes to compensate for the difference in doping concentration across the memory string.

In a more preferred embodiment, as shown in fig. 8, the doped channel layer and the doped semiconductor layer are subjected to an activation process such that the doping concentrations of the doped channel layer and the doped semiconductor layer are the same. An electron current path is formed between the N-type doped semiconductor layer and the channel hole when an erase operation is performed, and electrons are supplied to the memory string when the erase operation is performed. Under the condition that the doping concentrations of the doped channel layer and the doped semiconductor layer are the same, the same GIDL voltage is applied to different memory cells on the memory string, and the GIDL current with basically the same magnitude can be realized. This may improve erase speed, reduce current consumption, and/or reduce power consumption.

The activation process may include a thermal annealing process (thermal active) or a laser activation process (laser active). It should be noted that the temperature of laser activation is lower than the temperature of high-temperature annealing activation, and in practical application, the activation treatment process can be selected according to practical requirements, so as to prevent the temperature of activation treatment from affecting the subsequent processes.

In some embodiments, after the activation process, the surface of the doped semiconductor layer still exhibits an uneven shape, but the surface of the doped semiconductor layer has a more gradual shape.

With further reference to fig. 9, a buffer layer 118 is deposited on the doped semiconductor layer 115. The buffer layer 118 may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, to cover the portion of the channel structure corresponding to the sacrificial layer and the stacked structure. Since the surface of the doped semiconductor layer described above exhibits an uneven shape, the surface of the buffer layer also exhibits an uneven shape at this time. In some embodiments, the interface between the doped semiconductor layer and the buffer layer is not planar. That is, the doped semiconductor layer includes a flat portion and a protruding portion extending into the buffer layer. In some embodiments, the buffer layer may be an oxide, for example, silicon oxide.

As shown in fig. 14, in step 1406, the buffer layer is planarized. As shown in fig. 10, the buffer layer 118 is planarized, which may be performed using, for example, a chemical mechanical polishing process to ensure a smooth surface of the buffer layer.

As shown in fig. 14, in step 1407, a source contact is formed through the buffer layer and extending into the doped semiconductor layer. Further, as shown in fig. 11 and 12, the buffer layer 118 and the doped semiconductor layer 115 are etched to form a source contact opening 124; the source contact opening 124 is filled with a conductive material to form a source contact 117. In some embodiments, the buffer layer 118 and the doped semiconductor layer 115 may also be etched while forming the source contact to form a contact opening 123 through the buffer layer 118 and the doped semiconductor layer 115; filling the contact opening 123 with a conductive material to form the contact 116; where contact 116 makes contact with the end of peripheral contact 107 and source contact 117 makes contact with channel layer 111. As shown in fig. 8, after the doped semiconductor layer 115 is formed, the surface of the doped semiconductor layer 115 presents an uneven shape, and the uneven surface of the doped semiconductor layer 115 affects the formation of subsequent contacts and source contacts, so that the doped semiconductor layer 115 usually needs to be planarized, but since the planarization process of the doped semiconductor layer 115 is difficult and time-consuming, in the embodiment of the present invention, the buffer layer 118 is formed on the doped semiconductor layer 115 instead of planarizing the doped semiconductor layer 115, as shown in fig. 9, although the surface of the buffer layer 118 also presents an uneven shape. However, since the material of the buffer layer 118 is oxide, the planarization process is simple and fast, and the planarization effect is good. Therefore, in the embodiment of the present application, the non-planarized doped semiconductor layer and the planarized buffer layer are used as the substrate to form the source contact. In addition, when forming the source contact, in order to make the contact surface between the source contact and the doped semiconductor layer as large as possible, in the embodiment of the present application, a source contact opening is selected to be formed at the top end of the portion where the channel structure protrudes (the portion where the channel structure corresponds to the sacrificial layer), and in order to ensure that the source contact opening is as deep as possible, the depth of the source contact opening is deepened by aligning the source contact opening with the top end portion of the portion where the channel structure protrudes. As such, the depth of the portion of the bottom surface of the source contact opening in contact with the channel structure is less than the depth of the portion not in contact with the channel structure. In other words, the depth of the portion of the bottom surface of the source contact opening that overlaps the region where the channel layer is located is less than the depth of the portion that does not overlap the region where the channel layer is located.

Therefore, in the embodiment of the present application, not only the depth of the source contact opening is formed to be deeper, but also the contact surface between the source contact and the doped semiconductor layer is larger.

With further reference to fig. 11, in some embodiments, a contact opening 123 extending through the buffer layer 118 and the doped semiconductor layer 115 may be formed using a wet/dry etch process. In some embodiments, photolithography is used to pattern the contact openings in alignment with the peripheral contacts. The etching of the contact opening may stop at an upper end of the peripheral contact.

In some embodiments, the source contact opening may extend into a top portion of the doped semiconductor layer, i.e., after passing through the buffer layer by the etching process, the etching of the portion of the doped semiconductor layer may be continued. In some embodiments, the source contact opening is formed using a wet/dry etch process. In some embodiments, etching through the buffer layer and etching the doped semiconductor layer may employ different etching processes.

Still referring to fig. 12, a source contact 117 is formed by filling a conductive material in the source contact opening 124 at the back side of the doped semiconductor layer 115. In particular, one or more conductive materials may be deposited into the source contact openings using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof, to fill the source contact openings with the adhesive and the conductive layer. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may then be performed to remove the excess conductive material so that the top surface of the source contact is flush with the top surface of the buffer layer.

In some embodiments, the contact is connected to a peripheral contact, which may enable transmission of electrical signals with peripheral circuitry of the second semiconductor structure; the source contact may be directly electrically connected to the channel layer, but of course, the source contact may also be electrically connected to the channel layer through the doped semiconductor layer.

With further reference to fig. 11, the three-dimensional memory of the present application sequentially forms a doped semiconductor layer 115 and a buffer layer 118, the doped semiconductor layer 115 covers the end of the channel structure and the stacked structure; after the buffer layer 118 is planarized; the buffer layer 118 and the doped semiconductor layer 115 are etched to form source contact openings 123. If the buffer layer is not formed, the doped semiconductor layer is directly etched to form the source contact opening, so that the etching depth is small, the difficulty of the etching process is very high, and the formed source contact is not stable. Therefore, after the buffer layer is formed, the buffer layer and the doped semiconductor layer are etched, the etching depth of the source contact opening is large, and the etching process is easier to operate. In some embodiments, the source contact opening is partially located on top of the channel layer, and the etching of the opening on top of the channel layer stops at the channel layer at the end of the channel structure.

In a more preferred embodiment, the depth of the portion of the bottom surface of the source contact opening in contact with the channel layer is less than the depth of the portion not in contact with the channel layer. As shown in fig. 11, a portion of the source contact opening is located above the channel layer, which is etched through the buffer layer and extends the etched portion of the doped semiconductor layer; another portion of the source contact opening is not located above the channel layer, which portion etches through the buffer layer and extends to etch a greater depth of the doped semiconductor layer. In some embodiments, the bottom surface of the source contact opening has at least two levels of different heights. By increasing the etching depth, the stability and the conductivity of the formed source contact can be effectively improved.

As shown in fig. 12, the three-dimensional memory of the present application may further include a third interconnect layer 119 located above the source contact 117 and electrically connected to the source contact 117 to enable pad extraction. For example, electrical signals are communicated between the first semiconductor structure and the second semiconductor structure.

FIG. 13 is a side view in cross-section of an exemplary three-dimensional memory according to one embodiment of the present application. The three-dimensional memory of the present application may be a bonded chip including the second semiconductor structure 200 and the first semiconductor structure 100 bonded to each other. The first semiconductor structure 100 and the second semiconductor structure 200 may be bonded in a "face-to-face" fashion, i.e., the first substrate is at the top of the three-dimensional memory and the second substrate 201 is at the bottom of the three-dimensional memory.

Specifically, the first semiconductor structure 100 includes a buffer layer 118, a doped semiconductor layer 115, and a stacked structure disposed in a stack, and a channel structure 110 extending through the stacked structure and into the doped semiconductor layer 115. Wherein the stacked structure includes conductive layers and insulating layers alternately stacked in a vertical direction. The stacked structure may include a step region and a core region. In the step region, a plurality of insulating layers and a plurality of conductive layers are alternately stacked to form a plurality of steps. The channel structure 110 is located in the core region, vertically extending through the alternately stacked conductive and insulating layers. Radially inward of the channel structure 110, a memory film comprising, in order radially inward, a blocking layer, a memory layer, and a tunneling layer, and a channel layer. Wherein the barrier layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. In one example, the memory film may include a silicon oxide/silicon oxynitride/silicon oxide (ONO) composite layer. The channel layer may include, for example, amorphous silicon, polycrystalline silicon, or single crystal silicon, among others.

Since the surface of the doped semiconductor layer 115 is formed in an uneven shape as described above, the surface of the buffer layer 118 is also formed in an uneven shape. In some embodiments, the interface between the doped semiconductor layer 115 and the buffer layer 118 is not planar.

In one example, the channel layer may also include a doped channel layer and an undoped channel layer, the doped channel layer including a portion located in the doped semiconductor layer, and a portion located in the stacked-layer structure; the undoped channel layer is entirely located in the stacked structure. The portion of the channel structure 110 in the stacked structure further includes a storage film surrounding the channel layer; the storage film includes a barrier layer, a storage layer, and a tunneling layer radially inward of the channel hole.

In a more preferred embodiment, the doping concentration of the doped channel layer and said doped semiconductor layer is the same. By ensuring that the doping concentrations of the doped channel layer and the doped semiconductor layer are the same, the same GIDL voltage is applied to different memory cells on the memory string, and GIDL currents with substantially the same magnitude can be achieved. This may improve erase speed, reduce current consumption, and/or reduce power consumption.

Still referring to fig. 13, the three-dimensional memory is further provided with a dummy channel structure 109, where a material of the dummy channel structure 109 is different from a material of the channel structure 110, and the dummy channel structure 109 is filled with an insulating material. The virtual channel structure can also play a role in supporting, and collapse of the laminated structure is avoided. In one example, the dummy channel structure may be cylindrical.

With further reference to fig. 13, the three-dimensional memory is further provided with a slit 122, and the inside of the slit 122 may be filled with an insulating material. In one example, the insulating structure may have an air gap. Here, the slits may be gate slits.

The three-dimensional memory may also form a peripheral contact 107, the peripheral contact 107 may extend vertically into the sacrificial layer, and a depth of the peripheral contact 107 may be greater than a thickness of the stacked structure. Further, the three-dimensional memory may also form a contact 108, and one end of the contact 108 is in contact with the conductive layer at the step of the step region of the stacked structure.

The peripheral circuit may include a transistor formed over the second substrate, where the transistor may be formed in whole or in part over the second substrate.

In some embodiments, the second semiconductor structure of the three-dimensional memory further includes a second interconnect layer (not shown in fig. 13) located above the peripheral circuit, the second interconnect layer being used to pass electrical signals of the peripheral circuit, i.e., to input the electrical signals to the peripheral circuit or to output the electrical signals of the peripheral circuit. The second interconnect layer may include one or more interlayer insulating layers in which both interconnect lines and contacts may be formed, i.e., the second interconnect layer may include a plurality of interconnect lines and contacts in the interlayer insulating layers. In particular, both the interconnect lines and the contacts in the interconnect layer may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlayer insulating layer may include an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in fig. 13, the second semiconductor structure 200 further includes a second bonding layer 202, and the second bonding layer 202 is located above the second interconnect layer and the peripheral circuits. The second bonding layer 202 may include a plurality of second bonding contacts 203 and an insulating material electrically isolating the second bonding contacts 203. The second bonding contact may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the second bonding contacts may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

With further reference to fig. 13, the first semiconductor structure 100 further includes a first bonding layer 102, the first bonding layer 102 being above a second bonding layer 202 of the second semiconductor structure 200. The first bonding layer 102 may also include a plurality of first bonding contacts 120 and an insulating material that electrically isolates the first bonding contacts 120. The first bonding contact may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the first bonding contact may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Similarly, first semiconductor structure 100 further includes a first interconnect layer (not shown in fig. 13) located above first bonding layer 102, which may be used to pass electrical signals. The first interconnection layer may include one or more interlayer insulating layers in which both interconnection lines and contacts may be formed, i.e., the second interconnection layer may include a plurality of interconnection lines and contacts in the interlayer insulating layers. In particular, both the interconnect lines and the contacts in the interconnect layer may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlayer insulating layer may include an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Still referring to fig. 13, the three-dimensional memory further includes a source contact 117 extending through the buffer layer 118 and into the doped semiconductor layer 115, the source contact 117 partially contacting the channel structure 110; further, the source contact 117 partially contacts the channel layer to enable transmission of an electrical signal. In a more preferred embodiment, the thickness of the portion of source contact 117 not in contact with the channel layer is greater than the thickness of the portion in contact with the channel layer. The source contact 117 provided in the embodiment of the present application not only has a relatively thick thickness, but also has a relatively large contact area with the doped semiconductor layer 115, so that the source contact 117 has good stability and conductivity. In the embodiment of the present invention, even if the doped semiconductor layer 115 is not planarized, the formed source contact has better stability and conductivity. In the embodiment of the present invention, a buffer layer is formed on the doped semiconductor layer 115, and a source contact is formed in the buffer layer and the doped semiconductor layer after the buffer layer is planarized.

With further reference to fig. 13, the three-dimensional memory further includes a contact 116 extending through the buffer layer 118 and the doped semiconductor layer 115, wherein the contact 116 contacts an end of the peripheral contact 107.

The three-dimensional memory of the present application may further include a third interconnect layer 119 located above the source contact 117 and electrically connected to the source contact 117 to enable pad extraction. For example, electrical signals are communicated between the first semiconductor structure and the second semiconductor structure.

With continuing reference to fig. 13, an embodiment of the present application further provides a three-dimensional memory, where the three-dimensional memory includes:

a buffer layer 118, a doped semiconductor layer 115, a stacked structure, and a first bonding layer 102, which are sequentially disposed;

a channel structure 110, the channel structure 110 extending through the stack and into the doped semiconductor layer 115; the channel structure 110 includes a memory film and a channel layer;

a source contact 117 extending through the buffer layer 118 and into the doped semiconductor layer 115;

a second substrate 201, a peripheral circuit formed on the second substrate 201 and a second bonding layer 202 formed on the peripheral circuit;

the first bonding layer 102 and the second bonding layer 202 are bonded to each other.

According to some embodiments of the present application, source contact 117 is in contact with the channel layer.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application, and all modifications, equivalents, and direct/indirect applications in other related technical fields within the spirit of the present application are included in the scope of the present application.

Claims

1. A method of fabricating a three-dimensional memory, the method comprising:

providing a first substrate;

forming a doped semiconductor layer and a buffer layer in sequence, wherein the doped semiconductor layer is in contact with the channel layer; an interface between the doped semiconductor layer and the buffer layer is not flat;

carrying out planarization treatment on the buffer layer;

2. The method of fabricating a three-dimensional memory of claim 1, wherein the source contact is in contact with the channel layer.

3. The method of claim 2, wherein forming a source contact extending through the buffer layer and into the doped semiconductor layer comprises:

4. The method of manufacturing a three-dimensional memory according to claim 3, wherein a depth of a portion where a bottom surface of the source contact opening overlaps with a region where the channel layer is located is smaller than a depth of a portion where the bottom surface of the source contact opening does not overlap with the region where the channel layer is located.

5. The method of claim 1, wherein the sequentially forming a doped semiconductor layer and a buffer layer comprises:

forming a doped semiconductor layer by an in-situ growth process;

depositing a buffer layer on the doped semiconductor layer;

6. The method of fabricating a three-dimensional memory of claim 5, wherein prior to forming the doped semiconductor layer, the method further comprises:

7. The method of fabricating a three-dimensional memory of claim 6, wherein prior to forming the buffer layer, the method further comprises:

and performing activation treatment on the doped channel layer and the doped semiconductor layer to enable the doping concentration of the doped channel layer and the doped semiconductor layer to be the same.

8. The method of fabricating a three-dimensional memory as claimed in claim 1, wherein before etching away the first substrate and the sacrificial layer and a portion of the memory film, the method further comprises:

a first bonding layer is formed on the laminated structure;

bonding the first bonding layer and the second bonding layer.

9. The method of claim 3, wherein etching the buffer layer and the doped semiconductor layer to form a source contact opening comprises:

10. The method of claim 9, wherein filling the source contact opening with a conductive material to form a source contact comprises:

The contact is in contact with an end of the peripheral contact.

11. A three-dimensional memory, comprising:

the buffer layer, the doped semiconductor layer and the laminated structure are arranged in sequence; an interface between the doped semiconductor layer and the buffer layer is not flat;

a source contact extending through the buffer layer and into the doped semiconductor layer; the depth of the overlapped part of the source contact and the area where the channel layer is located is smaller than that of the part which is not overlapped with the area where the channel layer is located.

12. The three-dimensional memory of claim 11, wherein the source contact is in contact with the channel layer.

13. The three-dimensional memory according to claim 11, wherein the three-dimensional memory further comprises:

a second substrate having a peripheral circuit formed thereon.

14. The three-dimensional memory according to claim 11,

the channel layer includes a doped channel layer including a portion in the doped semiconductor layer and a portion in the stacked structure.

15. The three-dimensional memory of claim 14, wherein the doped channel layer and the doped semiconductor layer have the same doping concentration.

16. The three-dimensional memory according to claim 11, further comprising: a contact extending through the buffer layer and the doped semiconductor layer, wherein the contact is in contact with an end of a peripheral contact.

17. The three-dimensional memory of claim 11, wherein the doped semiconductor layer comprises a flat portion and a protruding portion extending into the buffer layer.

18. A three-dimensional memory, the three-dimensional memory comprising:

the buffer layer, the doped semiconductor layer, the laminated structure and the first bonding layer are arranged in sequence; an interface between the doped semiconductor layer and the buffer layer is not flat;

a source contact extending through the buffer layer and into the doped semiconductor layer; the depth of the overlapped part of the source contact and the area of the channel layer is smaller than that of the part which is not overlapped with the area of the channel layer;

19. The three-dimensional memory of claim 18, wherein the source contact is in contact with the channel layer.