CN114759037A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of fabricating the same. The method comprises the following steps: forming a first semiconductor structure comprising a core region, the core region comprising a semiconductor layer, a stacked structure located on the semiconductor layer, and a channel structure extending through the stacked structure and into the semiconductor layer; removing the semiconductor layer at the end of the channel structure to expose the end of the channel structure; forming a conductive layer of the channel layer overlying an end of the channel structure, the conductive layer in electrical contact with the channel layer.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The embodiment of the disclosure relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background

With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, with integration density being increased by three-dimensionally arranging memory cells over a substrate. The technical development of such a three-dimensional memory device is one of the mainstream of international development.

However, in the manufacturing process of the three-dimensional memory device, a back source contact is generally formed on the channel structure to electrically lead out the channel structure, but there is a risk of damaging the channel structure when forming the back source contact.

Disclosure of Invention

In view of the above, the embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same to solve at least one problem in the prior art.

In order to achieve the above purpose, the technical solution of the embodiment of the present disclosure is implemented as follows:

a first aspect of the present disclosure provides a method of manufacturing a semiconductor device, the method including:

forming a first semiconductor structure comprising a core region, the core region comprising a semiconductor layer, a stacked structure located on the semiconductor layer, and a channel structure extending through the stacked structure and into the semiconductor layer; removing the semiconductor layer at the tail end of the channel structure to expose the tail end of the channel structure; forming a conductive layer of a channel layer overlying an end of the channel structure, the conductive layer in electrical contact with the channel layer.

According to one embodiment of the present disclosure, the first semiconductor structure further comprises a peripheral region comprising a peripheral contact structure extending into the semiconductor layer; the thickness of the conductive layer is less than the thickness of the semiconductor layer.

According to one embodiment of the present disclosure, the channel structure includes a memory film and the channel layer; the storage film comprises a blocking layer, a storage layer and a tunneling layer along the radial direction of the channel structure; the removing the semiconductor layer at the end of the channel structure to expose the end of the channel structure includes: removing the semiconductor layer at the tail end of the channel structure; removing the memory film surrounding the channel layer at the end of the channel structure to expose the end of the channel structure.

According to an embodiment of the present disclosure, prior to the forming the conductive layer of the channel layer overlying the channel structure end, the method further comprises: carrying out an ion implantation process on the channel layer at the tail end of the channel structure to form a doped channel layer; and carrying out activation treatment on the doped channel layer.

According to one embodiment of the present disclosure, the semiconductor layer is a doped semiconductor layer; the doped semiconductor layer and the doped channel layer have the same doping type.

According to an embodiment of the present disclosure, the method further comprises: forming a dielectric layer, wherein the dielectric layer covers the conducting layer and the semiconductor layer; carrying out planarization treatment on the dielectric layer so that the upper surfaces of the dielectric layers of the peripheral area and the core area are flush; forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

According to an embodiment of the present disclosure, the forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure includes: forming a peripheral contact opening by etching through a first mask plate, wherein the peripheral contact opening penetrates through the dielectric layer, the conducting layer and the semiconductor layer and exposes the peripheral contact structure; and etching through a second mask plate to form a source contact opening, wherein the source contact opening penetrates through the dielectric layer and exposes the conducting layer.

According to an embodiment of the present disclosure, the forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure further comprises: forming a peripheral contact in electrical contact with the peripheral contact structure within the peripheral contact opening; a source contact is formed within the source contact opening in electrical contact with the conductive layer.

According to an embodiment of the present disclosure, the method further comprises: forming a dielectric layer, wherein the dielectric layer covers the conducting layer and the semiconductor layer; carrying out planarization treatment on the dielectric layer so that the dielectric layer in the core region is flush with the upper surface of the semiconductor layer in the peripheral region; forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

According to an embodiment of the present disclosure, the forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure includes: forming a source contact opening and a peripheral contact opening by etching through a third mask plate, wherein the source contact opening exposes the conductive layer, and the peripheral contact opening exposes the peripheral contact structure; filling the source contact opening and the peripheral contact opening to form a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

According to an embodiment of the present disclosure, the forming of the source contact opening and the peripheral contact opening by etching through the third mask includes: forming a patterned mask layer through a third mask plate, wherein the patterned mask layer is provided with a first opening positioned in the peripheral area and a second opening positioned in the core area; the first opening exposes the semiconductor layer, and the second opening exposes the dielectric layer; and etching through the patterned mask layer to form the source contact opening in the dielectric layer and the peripheral contact opening in the semiconductor layer, wherein the etching of the source contact opening is stopped at the conductive layer.

According to an embodiment of the present disclosure, the method further comprises: and forming a buffer layer, wherein the buffer layer covers the dielectric layer in the core area and the semiconductor layer in the peripheral area.

According to an embodiment of the present disclosure, prior to forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure, the method further comprises: providing a second semiconductor structure, wherein the second semiconductor structure comprises a substrate and peripheral circuits formed on the substrate; bonding the first semiconductor structure and the second semiconductor structure.

A second aspect of the present disclosure provides a semiconductor device including: a first semiconductor structure comprising a core region; the core region comprises a stacking structure and a channel structure penetrating through the stacking structure; the core region further includes a conductive layer overlying and in electrical contact with the channel layer at the end of the channel structure.

According to one embodiment of the present disclosure, the first semiconductor structure further comprises a peripheral region comprising a semiconductor layer and a peripheral contact structure extending into the semiconductor layer; the conductive layer covers the semiconductor layer, and a height difference is provided between the conductive layer of the core region and the conductive layer of the peripheral region.

According to an embodiment of the present disclosure, the core region further includes a semiconductor layer, the conductive layer covers the semiconductor layer, and a thickness of the conductive layer is smaller than a thickness of the semiconductor layer.

According to one embodiment of the present disclosure, the channel layer is a doped channel layer, and the semiconductor layer is a doped semiconductor layer; the doped semiconductor layer and the doped channel layer have the same doping type.

According to an embodiment of the present disclosure, the first semiconductor structure further includes a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

According to an embodiment of the present disclosure, the semiconductor device further includes: a second semiconductor structure in bonding connection with the first semiconductor structure; the second semiconductor structure includes a substrate and peripheral circuitry located on the substrate.

The embodiment of the disclosure discloses a semiconductor device and a manufacturing method thereof, wherein the method comprises the following steps: forming a first semiconductor structure comprising a core region, the core region comprising a semiconductor layer, a stacked structure located on the semiconductor layer, and a channel structure extending through the stacked structure and into the semiconductor layer; removing the semiconductor layer at the tail end of the channel structure to expose the tail end of the channel structure; forming a conductive layer of a channel layer overlying an end of the channel structure, the conductive layer in electrical contact with the channel layer. The embodiment discloses a manufacturing method of a semiconductor device, which comprises the steps of forming a conducting layer covering a channel layer at the tail end of a channel structure after removing a semiconductor layer at the tail end of the channel structure, electrically contacting the conducting layer with the channel layer of the channel structure, and simultaneously using the conducting layer as an etching stop layer of a subsequently formed source contact, so that the condition that the etching of the formed source contact influences a planing window of the channel structure can be avoided, and the planing window of the channel structure can be enlarged; further, the present disclosure uses the conductive layer as an etch stop layer for forming the source contact, expanding the etch window of the source contact compared to forming the source contact in the semiconductor layer.

Drawings

Fig. 1 is a schematic diagram of a semiconductor device provided by an embodiment of the present disclosure;

fig. 2 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 3a to fig. 3j are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 4a to fig. 4e are schematic structural diagrams of another method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a schematic diagram of a semiconductor device provided in an embodiment of the present disclosure, and as shown in fig. 1, the semiconductor device includes a first semiconductor structure 100, and the first semiconductor structure 100 includes a first semiconductor layer 11 and a second semiconductor layer 12. The second semiconductor layer 12 covers the first semiconductor layer 11 and the channel layer 141 at the end of the channel structure 140, and the channel structure 140 is located in the core array region 111, wherein the second semiconductor layer 12 is formed after removing the first semiconductor layer of the core array region 111. Since the channel structure 140 needs to extend into the first semiconductor layer during formation, which does not have an etch stop capability, the etching needs to be controlled during the fabrication of the channel structure 140 to avoid etching through the first semiconductor layer. This etching control process is also called "gouging". During the subsequent source contact formation process, the source contact etching may affect the gouging window 13 of the channel structure 140, thereby making the gouging process of the channel structure 140 more difficult to control; secondly, since the channel structure 140 extends into the first semiconductor layer to a deeper depth, after the first semiconductor layer on the core array region 111 is removed, a thicker second semiconductor layer needs to be formed on the core array region 111 to cover the channel layer 141 at the end of the channel structure 140, but the thicker second semiconductor layer increases the difficulty of the process of performing the activation treatment on the channel layer 141 of the channel structure 140; in addition, during the activation process, since the first semiconductor layer 11 and the second semiconductor layer 12 are formed in different processes, and the crystal grains and lattice orientations of the two layers may be different, and a large number of voids may be generated at the interface 14 between the first semiconductor layer 11 and the second semiconductor layer 12, it is necessary to remove the second semiconductor layer on the core transition region 112, the step region 113, and the peripheral region 120, but it is difficult to maintain the thicker second semiconductor layer on the core array region 111 while removing the second semiconductor layer on the core transition region 112, the step region 113, and the peripheral region 120.

Therefore, the following technical scheme of the embodiment of the disclosure is provided.

The embodiment of the present disclosure provides a method for manufacturing a semiconductor device, and fig. 2 is a schematic flow chart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure, as shown in fig. 2, the method includes:

step 201, forming a first semiconductor structure including a core region, the core region including a semiconductor layer, a stacked structure on the semiconductor layer, and a channel structure penetrating through the stacked structure and extending into the semiconductor layer.

Fig. 3a to fig. 3j are schematic structural diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, and a process for forming the semiconductor device according to the embodiment will be described below with reference to fig. 3a to fig. 3 j.

As shown in fig. 3a, a stacked structure 130 is formed on the semiconductor layer 101. The stack structure is formed by alternately stacking the gate layers 131 and the insulating layers 132. Here, the gate layer 131 and the insulating layer 132 may have the same thickness as each other or different thicknesses from each other. Each gate layer 131 may be adjoined by two insulating layers 132 on both sides, and each insulating layer 132 may be adjoined by two gate layers 131 on both sides. The gate layer 131 may extend laterally (in a direction parallel to the semiconductor layers) as a word line, terminating at one or more steps of the stack structure 130. In some embodiments, prior to forming the stack structure 130, the semiconductor layer 101 is doped using an ion implantation process to form a doped semiconductor layer. In some embodiments, the doped semiconductor layer may be an N-type doped semiconductor layer. The N-type doped semiconductor layer may comprise a semiconductor material, such as silicon. In some embodiments, the N-type doped semiconductor layer comprises polysilicon formed by a deposition process. The N-type doped semiconductor layer may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer may be a polysilicon layer doped with an N-type dopant (e.g., P, Ar or Sb). In some embodiments, the material of the gate layer 131 includes, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof, and the insulating layer 132 includes an insulating material such as silicon oxide. In practical applications, the stacked structure 130 may be formed by a Deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering, Metal-Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD). The first semiconductor structure 100 includes a core region 110 and a mesa region 113, the mesa region 113 includes a plurality of mesas, and the gate layer is exposed on top of each mesa. The step region 113 may be formed by performing a plurality of so-called "trim-etch" cycles on the stacked structure 130 toward the semiconductor layer 101.

In some embodiments, the stack structure 130 is formed on a substrate, and the substrate on which the stack structure 130 is formed may be removed from the rear surface to expose the channel structure 140. After removing the substrate, a doped semiconductor layer may be deposited from the backside to electrically connect the sources of the plurality of channel structures 140, thereby increasing the conductance of the Array Common Source (ACS) of channel structures 140. In some embodiments, the backside thinning process is automatically stopped using one or more stop layers 103 so that the substrate can be completely removed to avoid wafer thickness uniformity control issues and reduce the manufacturing complexity of the backside process. Here, the substrate may be a simple substance semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, or the like), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, or the like), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. The material of the substrate may also be part of a dummy wafer (e.g., a carrier substrate) made of any suitable material to reduce the manufacturing cost of the semiconductor device, such as glass, sapphire, plastic, silicon, to name a few, since the substrate may be removed in a subsequent step.

In some embodiments, at least one stop layer 103 may also be formed between the semiconductor layer 101 and the stack structure 130. The material of the stop layer includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. In a preferred embodiment, the material of the stop layer and the material of the semiconductor layer are the same.

A channel structure 140 is formed through the stacked structure 130 and extending into the semiconductor layer 101. The core region 110 includes a core array region 111 and a core transition region 112, and the channel structure 140 is formed in the core array region 111. The channel structure 140 includes a channel layer 141 and a memory film. The memory film includes a blocking layer, a memory layer, and a tunneling layer radially inward of the channel structure. In some embodiments, to form the channel structure 140, a channel hole, which may be cylindrical, is formed through the stack structure 130 and extends into the semiconductor layer 101, and then a barrier layer, a memory layer, a tunneling layer, and a channel layer are sequentially formed in the channel hole. The manufacturing process for forming the channel hole includes wet etching and/or dry etching. In some embodiments, the blocking layer and the tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof, the storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof, and the channel layer 141 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The memory film and the channel layer may be formed using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the remaining space of the trench hole may be partially or completely filled with a capping layer comprising an insulating material and/or an air gap. In one example, the memory film may include a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).

A plurality of first dummy channel structures 161 and second dummy channel structures 162 may also be disposed in the stack structure 130. A first dummy channel structure 161 and a second dummy channel structure 162 are formed in the core transition region 112. The first dummy channel structure 161 and the channel structure 140 have the same internal structure and filling material, and the second dummy channel structure 162 is filled with insulating material, so as to support the first dummy channel structure and prevent the collapse of the stacked structure 130. In order to form the first dummy channel structure 161 and the second dummy channel structure 162, a dummy channel hole may be formed first, and the dummy channel hole and the channel hole may be formed in the same step. In some embodiments, the dummy channel hole may be cylindrical. It should be noted that as the number of stacked layers of the semiconductor device increases, the etching depth of the channel hole (trench) also increases, so that the plurality of first dummy channel structures 161, second dummy channel structures 162 and channel structures 140 may extend into the semiconductor layer 101 to different depths. The dummy channel hole and the channel hole may be formed in different steps.

The stacked structure 130 may further include a gate line slit (gate line slit), and the gate layer 131 in the stacked structure 130 may be formed through the gate line slit, which includes the following specific processes: an initial stack structure is formed, the initial stack structure being formed of alternately stacked insulating layers and sacrificial layers. The initial stacked structure is etched to form a gate line gap, the sacrificial layer in the initial stacked structure is removed through the gate line gap to form a lateral recess, and then a gate material is filled in the lateral recess to form the gate layer 131. The gate material includes, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In a subsequent step, an insulating material may be filled in the gate line gap to form the gate line isolation structure 150. The gate line isolation structure 150 may divide the plurality of memory strings into different memory blocks. One or more insulating materials (e.g., silicon oxide) may be deposited into the gate line gaps using one or more thin film deposition processes, such as ALD, CVD, PVD, and any other suitable process or any combination thereof, to completely or partially fill the gate line gaps, thereby forming the gate line isolation structures 150.

After the gate line isolation structure 150 is formed, a step contact 171, a peripheral contact structure 172 located outside the stacked structure 130 and extending into the semiconductor layer 101, and a channel contact 173 are formed. Wherein a step contact 171 is formed in the step region 113 and a channel contact 173 is formed in the core region 110. The first semiconductor structure 100 further includes a peripheral region 120, and a peripheral contact structure 172 is formed in the peripheral region 120. The step contact 171 is in conductive contact with the gate layer exposed by the corresponding step top surface. A mask layer may be formed on the stack structure 130 by depositing a mask material (e.g., silicon oxide or silicon nitride) on top of the stack structure 130 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The contact openings through the mask layer may be etched using a wet etch and/or a dry etch (e.g., Reactive Ion Etching (RIE)) followed by filling the contact openings with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form a step contact 171, a peripheral contact structure 172 outside the stacked structure 130 and extending into the semiconductor layer 101, and a channel contact 173.

A first bonding layer 102 is formed. First bonding layer 102 includes a plurality of first bonding contacts electrically connected to step contact 171, peripheral contact structure 172, and channel contact 173. The first bonding layer 102 may also include an insulating material that electrically isolates the first bonding contacts. The material of the first bonding contact includes, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used for electrically isolating the first bonding contacts may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

And bonding the first semiconductor structure and the second semiconductor structure. As shown in fig. 3b, the first semiconductor structure 100 in fig. 3a is rotated 180 ° in fig. 3b and then bonded to the second semiconductor structure 200. The second semiconductor structure 200 includes a substrate 201 and peripheral circuits formed on the substrate 201. The substrate 201 may include silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The peripheral circuits may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for operation of the semiconductor device, including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). The second semiconductor structure 200 further includes a second bonding layer 202, and the second bonding layer 202 may include a plurality of second bonding contacts and an insulating material electrically isolating the second bonding contacts. The material of the second bonding contact includes, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The insulating material used to electrically isolate the second bonding contact may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, first bonding layer 102 facing down first semiconductor structure 100 is bonded in a face-to-face manner with second bonding layer 202 facing up second semiconductor structure 200. In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 may be bonded by metal fusion bonding. Of course, in some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 may be bonded by non-metal bonding, including but not limited to using an adhesive or the like. In some embodiments, a bonding layer may also be formed between the first semiconductor structure 100 and the second semiconductor structure 200 by hybrid bonding, i.e., metal/nonmetal hybrid bonding.

In some embodiments, the first semiconductor structure 100 further includes a first interconnect layer 190 located above the first bonding layer 102, the first interconnect layer 190 being operable to pass electrical signals. The first interconnect layer 190 may include an interconnect line (metal)191, a contact (via)192, and an interlayer dielectric layer in which both the interconnect line 191 and the contact 192 may be formed, i.e., the first interconnect layer 190 may include a plurality of interconnect lines 191 and contacts 192 in the interlayer dielectric layer. The step contact 171, the peripheral contact structure 172, and the channel contact 173 are connected with corresponding interconnect lines in the first interconnect layer 190. In particular, the materials of the interconnect lines and contacts in the interconnect layer may each include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlevel dielectric layer may comprise an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. As an example, the interlayer dielectric layer includes a first silicon nitride layer 193 and a silicon oxide material filled in a gap between the interconnection line 191 and the contact 192.

Likewise, the second semiconductor structure 200 further includes a second interconnect layer (not shown) above the peripheral circuits, the second interconnect layer being used for passing electrical signals of the peripheral circuits, including inputting electrical signals to the peripheral circuits and outputting electrical signals of the peripheral circuits. The second interconnect layer may include a peripheral interconnect line, a peripheral contact, and a peripheral interlevel dielectric layer, in which both the peripheral interconnect line and the peripheral contact may be formed, i.e., the second interconnect layer may include a plurality of peripheral interconnect lines and peripheral contacts in the peripheral interlevel dielectric layer. In particular, the materials of the peripheral interconnect lines and the peripheral contacts in the second interconnect layer may each include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The peripheral circuit interlayer dielectric layer may comprise an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. As an example, the peripheral circuit interlayer dielectric layer includes a second silicon nitride layer 203 and a silicon oxide material filled in the peripheral interconnection line and the peripheral contact gap.

In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and/or a thermal treatment, may be applied to the surfaces of first bonding layer 102 and second bonding layer 202 prior to bonding. After bonding, the first bonding contact in the first bonding layer 102 and the second bonding contact in the second bonding layer 202 are aligned and brought into contact with each other, so that the stacked structure 130 and the channel structure 140 formed therethrough in the first semiconductor structure 100 can be electrically connected to the peripheral circuit in the second semiconductor structure 200.

In step 202, the semiconductor layer at the end of the channel structure 140 is removed to expose the end of the channel structure 140. As shown in fig. 3c, the semiconductor layer of the core array region 111 is etched and removed from the back surface of the semiconductor layer 101 to expose the end of the channel structure 140. The backside of the semiconductor layer 101 refers to a side of the semiconductor layer 101 away from the stacked structure 130. The semiconductor layer of the core array region 111 is removed by a wet etching process to expose the end of the channel structure 140. Since the wet etching process is selective, only the semiconductor layer of the core array region 111 may be etched and removed, and the structure below the semiconductor layer, that is, the channel layer 141 and the storage film of the channel structure 140, may not be etched and remain intact.

In some embodiments, after removing the substrate in the first semiconductor structure, the semiconductor layer 101 may be selectively deposited only on the peripheral region 120, the step region 113 and the core transition region 112 to form the semiconductor structure as shown in fig. 3 c. Note that, when the semiconductor layer of the core array region 111 is etched and removed from the back surface of the semiconductor layer 101 by the wet etching process, not only the end of the channel structure 140 is exposed, but also the end of the gate line isolation structure 150 is exposed.

Further, since the end of the channel structure 140 is exposed at this time, the memory film surrounding the channel layer 141 at the end of the channel structure 140 may be removed by a wet etching process to expose the channel layer 141 at the end of the channel structure 140. As described previously, the channel structure 140 includes the channel layer 141 and a memory film, which includes a blocking layer, a memory layer, and a tunneling layer in this order along a radial direction of the channel structure 140. In some embodiments, the blocking layer, the memory layer, and the tunneling layer at the ends of the channel structure may be selectively removed by a wet etching process without etching the channel layer. The etching of the memory film may also be controlled by controlling the etching time and/or etching rate such that the etching does not continue to affect the rest of the memory film surrounded by stack structure 130. In one example, the memory film is a composite layer including silicon oxide/silicon nitride/silicon oxide (ONO), and the barrier layer, the memory layer and the tunneling layer may be sequentially removed by selecting an appropriate etchant according to an etching selection ratio of silicon oxide and silicon nitride, and the memory film surrounding the channel layer 141 may be simultaneously removed by using an etchant capable of simultaneously removing silicon oxide and silicon nitride. When etching is performed using the etching selectivity of silicon oxide and silicon nitride, silicon oxide may be selectively removed using, for example, hydrofluoric acid as an etchant, and silicon nitride may be selectively removed using, for example, phosphoric acid as an etchant. In some embodiments, the gate line isolation structure 150 includes an electrical shield layer 151 and a capping layer surrounding the electrical shield layer 151. Wherein, the material of the electric shielding layer 151 may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the cap layer may be formed of an insulating material, which may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Here, the material of the cap layer may be the same as that of the memory film, so that when the memory film surrounding the channel layer 141 at the end of the channel structure 140 is removed, the cap layer surrounding the electrical shielding layer 151 at the end of the gate line isolation structure 150 is also removed to expose the electrical shielding layer 151 at the end of the gate line isolation structure 150.

An ion implantation process is performed on the channel layer 141 at the end of the channel structure 140 to form a doped channel layer at the end of the channel structure 140. In the ion implantation process, the implantation depth of the dopant ions can be controlled by controlling the ion implantation energy. Here, there is an overlap of the doped channel layer and the stack structure 130 in an extension direction of the channel structure 140.

After ion implantation into the channel layer at the end of the channel structure 140, the channel layer of the channel structure 140 includes two portions: a doped channel layer and an undoped channel layer, the undoped channel layer being located on a side of the doped channel layer proximate to the second semiconductor structure 200. In other embodiments, different doping depths, doping concentrations or doping impurity profiles (doping profiles) may be set according to the actual requirements of the semiconductor device. Wherein, the doping depth can be controlled by adjusting the acceleration energy of the ion beam; the doping concentration, i.e. the impurity dose, can then be controlled by monitoring the ion current during implantation; the doping impurity profile can be controlled by simultaneously adjusting the ion implantation energy and the ion implantation dose. Therefore, the doping is carried out by adopting the ion implantation process, the doping concentration, the doping depth and the doping impurity distribution can be more accurately controlled, and the repeatability is realized.

In some embodiments, the doped channel layer may be an N-type doped channel layer, thereby enabling Gate Induced Drain Leakage (GIDL) erase. In particular, the N-type doped channel layer may include, for example, polycrystalline silicon, monocrystalline silicon, or amorphous silicon. The N-type doped channel layer may include a dopant doped with a pentavalent impurity element, such as P, Ar or Sb, as an N-type dopant. Only four valence electrons in the pentavalent impurity atom can form a covalent bond with valence electrons in four surrounding semiconductor atoms, and the redundant one valence electron is easy to form a free electron due to no covalent bond constraint. Thus, the N-type doped channel layer is capable of providing free electrons. In some embodiments, an ion implantation process is employed to dope the ends of the channel layer with any appropriate N-type dopant to a desired doping depth and doping concentration.

In some embodiments, after completely removing the semiconductor layer and forming the doped channel layer, the semiconductor layer 101 is formed and the semiconductor layer 101 is doped to form a doped semiconductor layer. Wherein, the doping type of the doped semiconductor layer is the same as that of the doped channel layer. In some embodiments, the doped semiconductor layer may be an N-type doped semiconductor layer. In some embodiments, the semiconductor layer 101 is doped with N-type dopants using an ion implantation process.

And carrying out activation treatment on the doped channel layer. The activation process may include a high temperature annealing activation process (thermal active) or a laser activation process (laser active). It should be noted that the temperature for laser activation is lower than the temperature for high-temperature annealing activation, and in practical application, the activation treatment process may be selected according to practical requirements, so as to prevent the temperature for activation treatment from affecting the subsequent processes.

The present disclosure directly performs activation processing on the channel layer 141 at the end of the channel structure 140 after removing the semiconductor layer at the end of the channel structure 140 and the memory film surrounding the channel layer 141, and thus requires less energy to complete the activation processing of the channel layer 141.

In step 203, a conductive layer 181 is formed overlying the channel layer 141 at the end of the channel structure 140, the conductive layer 181 being in electrical contact with the channel layer 141. As shown in fig. 3d, the conductive layer 181 covers the channel layer 141 exposed at the end of the channel structure 140, the electrical shield layer 151 exposed at the end of the gate line isolation structure 150, and the semiconductor layer 101 of the peripheral region 120, the stepped region 113, and the core transition region 112. The material of the conductive layer 181 includes titanium or titanium nitride. Illustratively, the conductive layer 181 of the semiconductor layer 101 covering the exposed channel layer 141 at the end of the channel structure 140, the exposed electrical shield layer 151 at the end of the gate line isolation structure 150, and the peripheral region 120, the stepped region 113, and the core transition region 112 may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The thickness of the conductive layer 181 is smaller than that of the semiconductor layer 101.

In the present disclosure, the conductive layer 181 replaces a semiconductor layer to make electrical contact with the channel layer 141 of the channel structure 140, and there is no need to form an additional semiconductor layer on the first semiconductor structure 100, and there is no need to remove the semiconductor layer on the core transition region 112, the step region 113, and the peripheral region 120 and to keep a thicker semiconductor layer on the core array region 111, so that the process difficulty and cost can be reduced.

As shown in fig. 3e, a dielectric layer 182 is formed, and the dielectric layer 182 is deposited to a thickness greater than or equal to the thickness of the semiconductor layer 101. The dielectric layer 182 covers the conductive layer 181 and the semiconductor layer 101, and since the surface of the conductive layer 181 is uneven, the dielectric layer 182 formed thereon also exhibits an uneven surface. The material of dielectric layer 182 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. Illustratively, the dielectric layer 182 may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As shown in fig. 3f, dielectric layer 182 is planarized such that the top surfaces of dielectric layer 182 in peripheral region 120 and core region 110 are flush. By making the upper surfaces of the dielectric layer 182 of the peripheral region 120 and the core region 110 flush, the etching depths of the source contact opening and the peripheral contact opening during the subsequent etching can be substantially the same, so that the source contact opening and the peripheral contact opening can be formed simultaneously in one etching process. In some embodiments, the excess dielectric layer on the peripheral region 120 and/or the core region 110 is removed by a Chemical Mechanical Polishing (CMP) process to make the upper surfaces of the dielectric layers 182 of the peripheral region 120 and the core region 110 flush after planarization.

As shown in fig. 3g, a peripheral contact opening 183 is formed by etching through the first mask, and the peripheral contact opening 183 penetrates through the dielectric layer 182, the conductive layer 181 and the semiconductor layer 101, and exposes the peripheral contact structure 172. The etching of peripheral contact opening 183 stops at peripheral contact structure 172. First, a first mask (not shown) having a plurality of openings in the peripheral region 120 is formed. The plurality of openings expose the dielectric layer 182. Etching is performed through the first mask to form peripheral contact openings 183. Here, the locations of the plurality of openings in peripheral region 120 correspond to the locations of peripheral contact structures 172 such that peripheral contact openings 183 subsequently formed through the openings can expose peripheral contact structures 172. In some embodiments, the peripheral contact opening 183 is formed using a dry etch process. In other embodiments, isolation openings 184 may also be formed in the stepped region 113, as shown in FIG. 3 g. The isolation opening 184 may be filled with an insulating material to form an isolation structure, and the isolation structure is used to divide the semiconductor layer into different portions to facilitate subsequent electrical extraction. The isolation opening 184 may be formed in the same step as the peripheral contact opening 183 to simplify the process and reduce the cost.

In some embodiments, after forming the peripheral contact opening 183, an isolation layer 185 is formed on the sidewalls of the peripheral contact opening 183. As shown in fig. 3h, an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, is deposited on the first semiconductor structure 100. The isolation layer may be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof. In some embodiments, the isolation opening 184 may also be filled with an insulating material to form an isolation structure, and this filling step may be performed in the same step as the deposition of the insulating material described above. The insulating material at the bottom of the peripheral contact opening 183 is etched away to form an isolation layer 185 on the sidewalls of the peripheral contact opening 183. Specifically, the insulating material is anisotropically processed to cause the etching selectivity of the insulating material at the sidewall of the peripheral contact opening 183 to be different from the etching selectivity of the insulating material at the bottom of the peripheral contact opening 183, so that the insulating material at the bottom of the peripheral contact opening 183 can be etched away to obtain the isolation layer 185 at the sidewall of the peripheral contact opening 183, as shown in fig. 3 h.

As shown in fig. 3i, a source contact opening 186 is formed by second masking etch, the source contact opening 186 penetrates through the dielectric layer 182 and exposes the conductive layer 181. The etching of source contact opening 186 stops at conductive layer 181, in other words, conductive layer 181 acts as an etch stop for source contact opening 186. First, a second mask (not shown) having a plurality of openings in the core array region 111 is formed. The plurality of openings expose the conductive layer 181. Etching is performed through the second mask to form source contact openings 186. In some embodiments, source contact opening 186 is formed using a dry etch process. It should be noted that the number of peripheral contact openings 183 and source contact openings 186 in the figures is only used for describing the embodiments of the present disclosure, and is not used for limiting the number of openings, and the number of peripheral contact openings 183 and source contact openings 186 may be set according to actual requirements.

As shown in fig. 3j, peripheral contact opening 183 and source contact opening 186 are filled with a conductive material to form peripheral contact 187 and source contact 188. Wherein peripheral contact 187 is in electrical contact with peripheral contact structure 172 and source contact 188 is in electrical contact with conductive layer 181. The isolation layer 185 on the sidewalls of the peripheral contact opening 183 serves to electrically isolate the peripheral contact 187 from the semiconductor layer 101. In some embodiments, the peripheral contact 187 is formed prior to the source contact 188. In other embodiments, the source contact 188 is formed prior to the peripheral contact 187. In some embodiments, the conductive material is tungsten. In particular, one or more conductive materials may be deposited into peripheral contact openings 183 and source contact openings 186 using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof, to fill peripheral contact openings 183 and source contact openings 186 with an adhesive and a conductive material. A planarization process, such as a chemical mechanical polishing process (CMP), may then be performed to remove excess conductive material so that the top surfaces of the peripheral contact 187 and the source contact 188 are flush with the top surface of the isolation layer 185. In some embodiments, the source contact 188 is electrically connected to the channel layer 141 through the conductive layer 181. The source contact 188 may or may not be directly over the channel structure 140, as long as the source contact 188 is electrically connectable to the channel layer 141 through the conductive layer 181.

According to the method, after the semiconductor layer at the tail end of the channel structure 140 is removed, the conducting layer 181 covering the channel layer 141 at the tail end of the channel structure 140 is formed, the conducting layer 181 is in electrical contact with the channel layer 141 of the channel structure 140, and meanwhile, the conducting layer 141 is used as an etching stop layer of the source contact 188 formed subsequently, so that the condition that the etching for forming the source contact 188 influences the planing window of the channel structure 140 can be avoided, and the planing window of the channel structure 140 can be enlarged; further, the present disclosure uses the conductive layer 181 as an etch stop layer for forming the source contact 188, enlarging the etch window for the source contact 188 as compared to forming the source contact 188 in a semiconductor layer.

In some embodiments, after forming peripheral contact 187 and source contact 188, the method further comprises forming a routing layer (not shown) on peripheral contact 187 and source contact 188, the routing layer electrically connecting peripheral contact 187 and source contact 188 for pad extraction. For example, electrical signals are transferred between the first semiconductor structure 100 and the second semiconductor structure 200.

Fig. 4a to fig. 4e are schematic structural diagrams of another method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The embodiment shown in fig. 4 a-4 e is similar to the embodiment shown in fig. 3 a-3 j, it being understood that the same steps in both the embodiment shown in fig. 4 a-4 e and the embodiment shown in fig. 3 a-3 j are not repeated for ease of description.

The semiconductor device shown in fig. 3e is obtained by the manufacturing method of the embodiment shown in fig. 3 a-3 e. Further, as shown in fig. 4a, the dielectric layer 182 is planarized such that the dielectric layer 182 of the core region 110 is flush with the upper surface of the semiconductor layer 101 of the periphery region 120. By making the dielectric layer 182 of the core region 110 flush with the upper surface of the semiconductor layer 101 of the peripheral region 120, the etching depths of the source contact opening and the peripheral contact opening during the subsequent etching can be substantially the same, so that the source contact opening and the peripheral contact opening can be formed simultaneously in one etching process. In some embodiments, the excess dielectric layer on the core region 110 and the excess dielectric layer and the conductive layer on the peripheral region 120 are removed by a Chemical Mechanical Polishing (CMP) process, so that the dielectric layer 182 of the core region 110 is flush with the upper surface of the semiconductor layer 101 of the peripheral region 120 after the planarization process.

As shown in fig. 4b, a buffer layer 189 is formed, and the buffer layer 189 covers the dielectric layer 182 of the core region 110 and the semiconductor layer 101 of the peripheral region 120. The material of the buffer layer 189 may be the same as the material of the dielectric layer 182. In other embodiments, the material of the buffer layer 189 may be different from the material of the dielectric layer 182, and the material of the buffer layer 189 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. Illustratively, the buffer layer 189 may be formed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As shown in fig. 4c, an etch forms peripheral contact opening 183 and source contact opening 186, peripheral contact opening 183 exposing peripheral contact structure 172, and source contact opening 186 exposing conductive layer 181. First, a third mask (not shown) is formed, the third mask having a plurality of first openings in the peripheral region 120 and a plurality of second openings in the core region 110, the first openings and the second openings exposing the buffer layer 189, and etching is performed through the first mask to form a source contact opening 186 in the dielectric layer 182 and the buffer layer 189 and a peripheral contact opening 183 in the semiconductor layer 101 and the buffer layer 189. Here, the position of the first opening corresponds to the position of the peripheral contact structure 172, so that the peripheral contact opening 183 subsequently formed through the first opening can expose the peripheral contact structure 172. The etching of source contact opening 186 stops at conductive layer 181, in other words, conductive layer 181 acts as an etch stop for source contact opening 186, and the etching of peripheral contact opening 183 stops at peripheral contact structure 172. In some embodiments, peripheral contact opening 183 and source contact opening 186 are formed using a dry etch process. In the embodiment of the present disclosure, the source contact opening 186 and the peripheral contact opening 183 can be formed at the same time by forming one mask, which simplifies the process steps and reduces the cost.

In the embodiment of the present disclosure, source contact opening 186 and peripheral contact opening 183 can be formed simultaneously by one etching process, so that the compatibility of the etching processes of source contact 188 and peripheral contact 187 is achieved.

In other embodiments, isolation openings 184 may also be formed in the stepped region 113, as shown in FIG. 4 c. The isolation opening 184 may be subsequently filled with an insulating material to form an isolation structure, and the isolation structure is used to divide the semiconductor layer into different portions, so as to facilitate subsequent electrical extraction. Isolation opening 184 may be formed in the same step as source contact opening 186 and peripheral contact opening 183 to simplify processing and reduce cost.

In some embodiments, after source contact opening 186 and peripheral contact opening 183 are formed, an isolation layer 185 is formed on sidewalls of source contact opening 186 and peripheral contact opening 183. As shown in fig. 4d, an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof is deposited on the first semiconductor structure 100. The isolation layer may be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof. In some embodiments, the isolation opening 184 may also be filled with an insulating material to form an isolation structure, and this filling step may be performed in the same step as the deposition of the insulating material described above. The etch removes the insulating material at the bottom of source contact opening 186 and peripheral contact opening 183 to form an isolation layer 185 at the sidewalls of source contact opening 186 and peripheral contact opening 183. Specifically, the insulating material is anisotropically processed to cause the etch selectivity of the insulating material at the sidewalls of source contact opening 186 and peripheral contact opening 183 to be different from the etch selectivity of the insulating material at the bottom of source contact opening 186 and peripheral contact opening 183, so that the insulating material at the bottom of source contact opening 186 and peripheral contact opening 183 can be etched away to obtain isolation layer 185 at the sidewalls of source contact opening 186 and peripheral contact opening 183, as shown in fig. 4 d.

As shown in fig. 4e, source contact opening 186 and peripheral contact opening 183 are filled with a conductive material to form source contact 188 and peripheral contact 187. Wherein source contact 188 is in contact with conductive layer 181 and peripheral contact 187 is in contact with peripheral contact structure 172. The isolation layer 185 of the sidewalls of the peripheral contact opening 183 serves to electrically isolate the peripheral contact 187 from the semiconductor layer 101.

Fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure, and as shown in fig. 5, the semiconductor device includes a first semiconductor structure 100, where the first semiconductor structure 100 includes a core region 110; the core region 110 includes a stacked structure 130 and a channel structure 140 penetrating the stacked structure 130; the core region 110 also includes a conductive layer 181, the conductive layer 181 overlying the channel layer 141 at the end of the channel structure 140 and in electrical contact with the channel layer 141.

In some embodiments, the first semiconductor structure 100 further includes a peripheral region 120, the peripheral region 120 including a semiconductor layer 101 and a peripheral contact structure 172 extending into the semiconductor layer 101; the conductive layer 181 covers the semiconductor layer 101, and a height difference is provided between the conductive layer 181 of the core region 110 and the conductive layer 181 of the peripheral region 120.

In some embodiments, the core region 110 further comprises a semiconductor layer 101, and the thickness of the conductive layer 181 is less than the thickness of the semiconductor layer 101.

In some embodiments, channel layer 141 is a doped channel layer, semiconductor layer 101 is a doped semiconductor layer; the doped semiconductor layer and the doped channel layer have the same doping type.

In some embodiments, first semiconductor structure 100 further includes a source contact 188 in electrical contact with conductive layer 181 and a peripheral contact 187 in electrical contact with peripheral contact structure 172.

In some embodiments, the semiconductor device further includes a second semiconductor structure 200 bonded to the first semiconductor structure 100, the second semiconductor structure 200 including a substrate 201 and peripheral circuitry located on the substrate 201.

In some embodiments, the semiconductor device is a 3D NAND memory.

It should be noted that the above description of the semiconductor device is similar to the above description of the embodiment of the manufacturing method of the semiconductor device, and has similar beneficial effects to the embodiment of the manufacturing method of the semiconductor device, and therefore, the description is omitted. For technical details not disclosed in the semiconductor device of the embodiment of the present disclosure, please refer to the description of the method for fabricating the semiconductor device of the embodiment of the present disclosure.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present disclosure, and shall cover the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (19)

1. A method of fabricating a semiconductor device, the method comprising:

forming a first semiconductor structure comprising a core region, the core region comprising a semiconductor layer, a stacked structure located on the semiconductor layer, and a channel structure extending through the stacked structure and into the semiconductor layer;

removing the semiconductor layer at the end of the channel structure to expose the end of the channel structure;

forming a conductive layer of the channel layer overlying an end of the channel structure, the conductive layer in electrical contact with the channel layer.

2. The method of claim 1, wherein the first semiconductor structure further comprises a peripheral region comprising a peripheral contact structure extending into the semiconductor layer; the thickness of the conductive layer is less than the thickness of the semiconductor layer.

3. The manufacturing method of a semiconductor device according to claim 1, wherein the channel structure includes a memory film and the channel layer; the storage film comprises a blocking layer, a storage layer and a tunneling layer along the radial direction of the channel structure; the removing the semiconductor layer at the end of the channel structure to expose the end of the channel structure comprises:

removing the semiconductor layer at the tail end of the channel structure;

removing the memory film surrounding the channel layer at the end of the channel structure to expose the end of the channel structure.

4. The method of fabricating a semiconductor device according to claim 1, wherein prior to said forming a conductive layer of the channel layer overlying the channel structure ends, the method further comprises:

carrying out an ion implantation process on the channel layer at the tail end of the channel structure to form a doped channel layer;

and carrying out activation treatment on the doped channel layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor layer is a doped semiconductor layer;

the doped semiconductor layer and the doped channel layer have the same doping type.

6. The method of manufacturing a semiconductor device according to claim 2, further comprising:

forming a dielectric layer, wherein the dielectric layer covers the conducting layer and the semiconductor layer;

carrying out planarization treatment on the dielectric layer so as to enable the upper surfaces of the dielectric layers of the peripheral area and the core area to be flush;

forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

7. The method of claim 6, wherein said forming a source contact in electrical contact with said conductive layer and a peripheral contact in electrical contact with said peripheral contact structure comprises:

forming a peripheral contact opening by etching through a first mask plate, wherein the peripheral contact opening penetrates through the dielectric layer, the conducting layer and the semiconductor layer and exposes the peripheral contact structure;

and etching through a second mask plate to form a source contact opening, wherein the source contact opening penetrates through the dielectric layer and exposes the conducting layer.

8. The method of claim 7, wherein said forming a source contact in electrical contact with said conductive layer and a peripheral contact in electrical contact with said peripheral contact structure further comprises:

Forming a peripheral contact in electrical contact with the peripheral contact structure within the peripheral contact opening;

a source contact is formed within the source contact opening in electrical contact with the conductive layer.

9. The method of manufacturing a semiconductor device according to claim 2, further comprising:

forming a dielectric layer, wherein the dielectric layer covers the conducting layer and the semiconductor layer;

carrying out planarization treatment on the dielectric layer so as to enable the dielectric layer in the core area to be flush with the upper surface of the semiconductor layer in the peripheral area;

forming a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

10. The method of claim 9, wherein said forming a source contact in electrical contact with said conductive layer and a peripheral contact in electrical contact with said peripheral contact structure comprises:

forming a source contact opening and a peripheral contact opening by etching through a third mask plate, wherein the source contact opening exposes the conductive layer, and the peripheral contact opening exposes the peripheral contact structure;

filling the source contact opening and the peripheral contact opening to form a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the forming of the source contact opening and the peripheral contact opening by etching through a third mask includes:

forming a patterned mask layer through a third mask plate, wherein the patterned mask layer is provided with a first opening positioned in the peripheral area and a second opening positioned in the core area; the first opening exposes the semiconductor layer, and the second opening exposes the dielectric layer;

and etching through the patterned mask layer to form the source contact opening in the dielectric layer and the peripheral contact opening in the semiconductor layer, wherein the etching of the source contact opening is stopped at the conductive layer.

12. The method for manufacturing a semiconductor device according to claim 9, wherein the method further comprises:

and forming a buffer layer, wherein the buffer layer covers the dielectric layer in the core region and the semiconductor layer in the peripheral region.

13. Method for manufacturing a semiconductor device according to claim 6 or 9, wherein prior to said forming a source contact in electrical contact with said conductive layer and a peripheral contact in electrical contact with said peripheral contact structure, said method further comprises:

Providing a second semiconductor structure, wherein the second semiconductor structure comprises a substrate and peripheral circuits formed on the substrate;

bonding the first semiconductor structure and the second semiconductor structure.

14. A semiconductor device, characterized in that the semiconductor device comprises:

a first semiconductor structure comprising a core region;

the core region comprises a stacking structure and a channel structure penetrating through the stacking structure;

the core region further includes a conductive layer overlying and in electrical contact with the channel layer at the end of the channel structure.

15. The semiconductor device of claim 14, wherein the first semiconductor structure further comprises a peripheral region comprising a semiconductor layer and a peripheral contact structure extending into the semiconductor layer; the conductive layer covers the semiconductor layer, and a height difference exists between the conductive layer of the core region and the conductive layer of the peripheral region.

16. The semiconductor device of claim 14, wherein the core region further comprises a semiconductor layer, wherein the conductive layer covers the semiconductor layer, and wherein the conductive layer has a thickness less than a thickness of the semiconductor layer.

17. The semiconductor device according to claim 15 or 16, wherein the channel layer is a doped channel layer, and the semiconductor layer is a doped semiconductor layer; the doped semiconductor layer and the doped channel layer have the same doping type.

18. The semiconductor device of claim 15, wherein the first semiconductor structure further comprises a source contact in electrical contact with the conductive layer and a peripheral contact in electrical contact with the peripheral contact structure.

19. The semiconductor device according to claim 14, further comprising:

a second semiconductor structure in bonding connection with the first semiconductor structure; the second semiconductor structure includes a substrate and peripheral circuitry located on the substrate.

Images