CN109166820B - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- CN109166820B CN109166820B CN201810989689.3A CN201810989689A CN109166820B CN 109166820 B CN109166820 B CN 109166820B CN 201810989689 A CN201810989689 A CN 201810989689A CN 109166820 B CN109166820 B CN 109166820B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention provides a semiconductor device manufacturing method and a semiconductor device, wherein photoetching and etching processes are carried out to form a first opening penetrating through a first substrate, a first dielectric layer and a second dielectric layer with partial thickness, then the photoetching and etching processes are carried out to form a second opening penetrating through the first substrate and the first dielectric layer with partial thickness, then a maskless etching process is carried out to expose a second metal layer below the first opening and a part of the first metal layer below the second opening, and finally an interconnection layer is formed to realize metal interconnection between two wafers. The invention can form the first opening and the second opening by only adopting two light covers, and realizes the interconnection of the first metal layer and the second metal layer, thereby simplifying the process and reducing the production cost.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device manufacturing method and a semiconductor device.
Background
With the trend of highly integrated semiconductor development, the integration of chips with different functions is the main development direction of semiconductor packaging technology, and wafer level stacking based on 3D-IC technology can achieve the goals of lower cost, faster speed and higher density. After wafer bonding, how to realize metal interconnection between wafers is an important process in semiconductor processing. The inventor finds that at present, three times of photoetching (requiring three photomasks) and three times of etching processes are generally adopted, the process is complex, and the production cost is high.
Disclosure of Invention
The invention aims to provide a semiconductor device manufacturing method and a semiconductor device, so as to simplify the process and reduce the production cost.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device.
Providing a first wafer and a second wafer which are bonded, wherein the first wafer comprises a first substrate, a first dielectric layer and a first metal layer, the second wafer comprises a second substrate, a second dielectric layer and a second metal layer, and the first dielectric layer faces the second dielectric layer;
performing photoetching and etching processes to form a first opening, wherein the first opening penetrates through the first substrate, the first dielectric layer and the second dielectric layer with partial thickness, and the first opening is positioned above the second metal layer;
performing photoetching and etching processes to form a second opening, wherein the second opening penetrates through the first substrate and the first dielectric layer with partial thickness, the second opening is positioned above part of the first metal layer, and the second opening is communicated with the first opening;
performing a maskless etching process to expose the second metal layer below the first opening and a part of the first metal layer below the second opening; and the number of the first and second groups,
and forming an interconnection layer, wherein the interconnection layer is electrically connected with the second metal layer and the first metal layer through the first opening and the second opening, so that the metal interconnection between the two wafers is realized.
The present invention also provides a semiconductor device comprising:
the wafer structure comprises a first wafer and a second wafer, wherein the first wafer comprises a first substrate, a first dielectric layer and a first metal layer, the second wafer comprises a second substrate, a second dielectric layer and a second metal layer, and the first dielectric layer is bonded facing the second dielectric layer;
the first opening penetrates through the first substrate, the first dielectric layer and the second dielectric layer with partial thickness, the first opening is located above the second metal layer, the second opening penetrates through the first substrate and the first dielectric layer with partial thickness, the second opening is located above the first metal layer, and the second opening is communicated with the first opening; and the number of the first and second groups,
an interconnect layer formed in the first opening and the second opening, the interconnect layer electrically connected to the first metal layer and the second metal layer.
The invention provides a semiconductor device manufacturing method, which comprises the steps of firstly executing photoetching and etching processes to form a first opening penetrating through a first substrate, a first dielectric layer and a second dielectric layer with partial thickness, wherein the first opening is positioned above a second metal layer, then executing photoetching and etching processes to form a second opening penetrating through the first substrate and the first dielectric layer with partial thickness, wherein the second opening is positioned above part of the first metal layer and is communicated with the first opening, then executing a maskless etching process to expose the second metal layer below the first opening and part of the first metal layer below the second opening, and finally forming an interconnection layer to realize metal interconnection between two wafers. Compared with the prior art, the first opening and the second opening can be formed and the interconnection of the first metal layer and the second metal layer can be realized only by adopting two photomasks by only executing two photoetching and etching processes and one maskless etching process, so that the process is simplified, and the production cost is reduced.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating two wafers bonded according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a first opening formed in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a first opening with a filling layer formed therein according to an embodiment of the present invention;
FIG. 5 is a schematic view of the second opening after being formed according to one embodiment of the present invention;
FIG. 6 is a schematic view of the first opening with the filling layer removed according to an embodiment of the invention;
FIG. 7 is a schematic diagram of exposing a first metal layer and a second metal layer according to an embodiment of the invention;
fig. 8 is a schematic diagram illustrating the first opening and the second opening after forming an interconnect layer;
wherein the reference numbers are as follows:
10-a first wafer;
101-a first substrate; 102-a first dielectric layer; 103-a first metal layer; 104-a first etch stop layer;
102 a-a first dielectric layer first portion; 102 b-a first dielectric layer second portion;
20-a second wafer;
201-a second substrate; 202-a second dielectric layer; 203-a second metal layer; 204-a second etch stop layer;
202 a-a second dielectric layer first portion; 202 b-a second dielectric layer second portion; 205-a passivation layer;
31-bonding interface;
41-a first opening; 42-a second opening;
50-a filler layer;
60-interconnect layer.
Detailed Description
The following provides a detailed description of the semiconductor device and a method for fabricating the same, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, including:
providing a first wafer and a second wafer which are bonded, wherein the first wafer comprises a first substrate, a first dielectric layer and a first metal layer, the second wafer comprises a second substrate, a second dielectric layer and a second metal layer, and the first dielectric layer faces the second dielectric layer;
performing photoetching and etching processes to form a first opening, wherein the first opening penetrates through the first substrate, the first dielectric layer and the second dielectric layer with partial thickness, and the first opening is positioned above the second metal layer;
performing photoetching and etching processes to form a second opening, wherein the second opening penetrates through the first substrate and the first dielectric layer with partial thickness, the second opening is positioned above part of the first metal layer, and the second opening is communicated with the first opening;
performing a maskless etching process to expose the second metal layer below the first opening and a part of the first metal layer below the second opening; and the number of the first and second groups,
and forming an interconnection layer, wherein the interconnection layer is electrically connected with the second metal layer and the first metal layer through the first opening and the second opening, so that the metal interconnection between the two wafers is realized.
It should be noted that the present invention does not limit which wafer the first wafer and the second wafer must be placed on top/bottom, but the positions of the upper wafer and the lower wafer can be interchanged. Herein, for simplicity and convenience of description, only one positional relationship of the two wafers is shown, and those skilled in the art can understand that all the technical contents described herein are also equally applicable to the case where the positions of the "first wafer" and the "second wafer" are reversed upside down, and the positional relationship of the layers of the stacked semiconductor device is also correspondingly reversed upside down. In some cases, it is preferable to put a wafer with a relatively large wafer bow (bow) underneath during the bonding process for two wafers. However, in this case, after the wafer bonding is finished, it is also possible to determine which wafer is on top and which wafer is on bottom finally by determining whether to turn upside down or not according to actual requirements.
Note that, in this document, the numbers "first", "second", "third", "fourth", and the like are only for distinguishing between various components or processes having the same name, and do not mean an order or positional relationship, and the like. In addition, for each different component having the same name, such as "first substrate" and "second substrate", "first dielectric layer" and "second dielectric layer", etc., it is not intended that they all have the same structure or component. For example, although not shown in the drawings, in most cases, components formed in the "first substrate" and the "second substrate" are different, and the structures of the substrates may also be different. In some embodiments, the substrate may be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate may be a composite substrate such as a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (sige-on-insulator substrate). It will be understood by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application. Various device (not limited to semiconductor device) components (not shown) may be formed in the substrate. The substrate may also have been formed with other layers or members, such as: gate structures, contact holes, dielectric layers, metal lines and vias, and the like.
The following describes the manufacturing method of the embodiment of the invention in detail with reference to fig. 2 to 8.
As shown in fig. 2, a first wafer 10 and a second wafer 20 after bonding are provided, where the first wafer 10 includes a first substrate 101, a first dielectric layer 102 and a first metal layer 103, the second wafer 20 includes a second substrate 201, a second dielectric layer 202 and a second metal layer 203, the first dielectric layer 102 faces the second dielectric layer 202, and the two wafers are bonded by using the intermolecular chemical force of the interface film of the bonding dielectric layer to form a bonding interface 31.
The first dielectric layer 102 includes a first dielectric layer first portion 102a and a first dielectric layer second portion 102b, and the first metal layer 103 is embedded between the first dielectric layer first portion 102a and the first dielectric layer second portion 102 b; the second dielectric layer 202 includes a second dielectric layer first portion 202a and a second dielectric layer second portion 202b, and the second metal layer 203 is embedded between the second dielectric layer first portion 202a and the second dielectric layer second portion 202 b.
Further, the first wafer 10 further includes a first etching stop layer 104, where the first etching stop layer 104 is located between the first metal layer 103 and the first dielectric layer second portion 102 b; the second wafer 20 further comprises a second etch stop layer 204, and the second etch stop layer 204 is located between the second metal layer 203 and the second dielectric layer second portion 202 b. The second wafer 20 further comprises a passivation layer 205 on the surface of the second portion 202b of the second dielectric layer.
Preferably, after bonding, the first wafer 10 and/or the second wafer 20 are thinned to reduce the thickness of the device, on one hand, the first opening 41 is easily formed after thinning, and on the other hand, the thickness of the whole bonded wafer is reduced to facilitate high integration of the wafer.
As shown in fig. 3, performing a photolithography and etching process to form a first opening 41, forming a first patterned photoresist layer on the surface of the first substrate 101 by using a first photomask, forming a photoresist opening above the second metal layer 203 after exposure and development, etching by using the first patterned photoresist layer as a mask, stopping etching on the second etching stop layer 204 to form the first opening 41, and then removing the first patterned photoresist layer on the surface of the first substrate 101. The first opening 41 penetrates through the first substrate 101, the first dielectric layer 102 and the second dielectric layer second portion 202b, and the first opening 41 is located above the second metal layer 203.
As shown in fig. 4, a filling layer 50 is formed, in this embodiment, a BARC (bottom anti-Reflective Coating) with good fluidity is used as the filling layer, the BARC fills a plurality of the first openings 41, and then the filling layer 50 in the first openings 41 is etched, so that the top surface of the remaining filling layer 50 is higher than the surface of the first metal layer 103.
As shown in fig. 5, performing a photolithography and etching process to form a second opening 42, using a second photomask to form a second patterned photoresist layer on the surface of the first substrate 101, forming a photoresist opening above a portion of the first metal layer 103 and a portion of the second metal layer 203, etching with the second patterned photoresist layer as a mask to form the second opening 42, and using the remaining filling layer 50 as an etching stop layer to make the bottom surface of the second opening 42 flush with the top surface of the remaining filling layer 50. The second opening 42 penetrates through the first substrate 101 and a part of the thickness of the first dielectric layer 102, the second opening 42 is located above a part of the first metal layer 103, and the second opening 42 is communicated with the first opening 41. And, the cross-sectional width of the second opening 42 is larger than the cross-sectional width of the first opening 41 (the cross-section referred to herein is a cross-section taken perpendicular to the first and second wafers).
As shown in fig. 6, the remaining filling layer 50 in the first opening 41 is removed by an etching process.
As shown in fig. 7, a maskless etching is performed to remove the second etch stop layer 204 at the bottom of the first opening 41, and to remove the first dielectric layer first portion 102a at the bottom of the second opening 42 and on the surface of the first metal layer 103, so as to expose the second metal layer 203 under the first opening 41 and a portion of the first metal layer 103 under the second opening 42. The etching is carried out without a photomask, and the maskless etching is directly carried out, so that the cost of the photomask can be saved. It should be noted that, in fig. 7, only the first dielectric layer first portion 102a on the surface of the first metal layer 103 is removed, but in a specific implementation, there may be a certain degree of over-etching, and the first dielectric layer first portion 102a on the side surface of the first metal layer 103 may also be removed, which does not affect the performance of the device.
As shown in fig. 8, an interconnect layer 60 is formed, and the interconnect layer 60 is electrically connected to the second metal layer 203 and the first metal layer 103 through the first opening 41 and the second opening 42, so as to implement metal interconnection between the two wafers.
The interconnect layer 60 is a conductive material, and may be copper or a copper alloy, and the first opening 41 and the second opening 42 may be filled with copper electroplating to cover the surface of the first substrate 101, and then a chemical mechanical polishing planarization process is performed to remove the interconnect layer on the surface of the first substrate 101.
An embodiment of the present invention further provides a semiconductor device, as shown in fig. 2, 7, and 8, including:
the wafer structure comprises a first wafer 10 and a second wafer 20, wherein the first wafer 10 comprises a first substrate 101, a first dielectric layer 102 formed on the first substrate 101 and a first metal layer 103 embedded in the first dielectric layer 102, the second wafer 20 comprises a second substrate 201, a second dielectric layer 202 and a second metal layer 203, and the first dielectric layer 102 is bonded to the second dielectric layer 202;
a first opening 41 and a second opening 42, wherein the first opening 41 penetrates through the first substrate 101, the first dielectric layer 102 and the partial thickness of the second dielectric layer 202, the first opening 41 is located above the second metal layer 203, the second opening 42 penetrates through the first substrate 101 and the partial thickness of the first dielectric layer 102, the second opening 42 is located above a portion of the first metal layer 103, and the second opening 42 is communicated with the first opening 41; and the number of the first and second groups,
an interconnection layer 60 formed in the first opening 41 and the second opening 42, the interconnection layer 60 being electrically connected to the first metal layer 103 and the second metal layer 203.
Further, the cross-sections of the first opening 41 and the second opening 42 perpendicular to the surfaces of the first wafer 10 and the second wafer 20 are inverted trapezoids.
In summary, the present invention provides a method for fabricating a semiconductor device, which includes performing a photolithography and etching process to form a first opening penetrating through a first substrate, a first dielectric layer and a second dielectric layer with a partial thickness, the first opening being located above a second metal layer, performing a photolithography and etching process to form a second opening penetrating through the first substrate and the first dielectric layer with a partial thickness, the second opening being located above a portion of the first metal layer and being in communication with the first opening, performing a maskless etching process to expose the second metal layer under the first opening and a portion of the first metal layer under the second opening, and finally forming an interconnection layer to achieve metal interconnection between two wafers. Compared with the prior art, the first opening and the second opening can be formed and the interconnection of the first metal layer and the second metal layer can be realized only by adopting two photomasks by only executing two photoetching and etching processes and one maskless etching process, so that the process is simplified, and the production cost is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A method for manufacturing a semiconductor device, comprising:
providing a first wafer and a second wafer which are bonded, wherein the first wafer comprises a first substrate, a first dielectric layer and a first metal layer, the second wafer comprises a second substrate, a second dielectric layer and a second metal layer, and the first dielectric layer faces the second dielectric layer;
performing photoetching and etching processes to form a first opening, wherein the first opening penetrates through the first substrate, the first dielectric layer and the second dielectric layer with partial thickness, and the first opening is positioned above the second metal layer;
performing photoetching and etching processes to form a second opening, wherein the second opening penetrates through the first substrate and the first dielectric layer with partial thickness, the second opening is positioned above part of the first metal layer, and the second opening is communicated with the first opening;
performing a maskless etching process to expose the second metal layer below the first opening and a part of the first metal layer below the second opening; and the number of the first and second groups,
forming an interconnection layer electrically connected with the second metal layer and the first metal layer through the first opening and the second opening to realize metal interconnection between the two wafers,
after forming the first opening and before forming the second opening, the method further comprises:
forming a filling layer, wherein the filling layer fills the first opening and covers the surface of the first substrate; and the number of the first and second groups,
performing an etch-back process to remove the filling layer on the surface of the first substrate and a part of the filling layer in the first opening, so that the top surface of the filling layer remaining in the first opening is higher than the surface of the first metal layer;
and in the process of forming the second opening, the residual filling layer is used as an etching stop layer, so that the bottom surface of the second opening is flush with the top surface of the residual filling layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein before the performing the maskless etching process, further comprising:
and removing the residual filling layer in the first opening.
3. The semiconductor device manufacturing method according to claim 1 or 2, wherein the step of forming an interconnect layer includes:
performing an electroplating process to form an interconnection layer, wherein the interconnection layer fills the first opening and the second opening and covers the surface of the first substrate; and the number of the first and second groups,
and performing a chemical mechanical polishing process, removing the interconnection layer on the surface of the first substrate and performing surface planarization treatment.
4. The manufacturing method of a semiconductor device according to claim 1 or 2, wherein a material of the interconnection layer is copper or a copper alloy.
5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the first dielectric layer comprises a first dielectric layer first portion and a first dielectric layer second portion, and the first metal layer is embedded between the first dielectric layer first portion and the first dielectric layer second portion; the second dielectric layer comprises a first part of the second dielectric layer and a second part of the second dielectric layer, and the second metal layer is embedded between the first part of the second dielectric layer and the second part of the second dielectric layer; the first wafer further comprises a first etching stop layer, and the first etching stop layer is positioned between the first metal layer and the second part of the first dielectric layer; the second wafer further comprises a second etching stop layer, and the second etching stop layer is located between the second metal layer and the second part of the second dielectric layer.
6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein before forming the first opening, the method further comprises:
and thinning the bonded first wafer and/or second wafer.
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| TW518683B (en) * | 2000-07-24 | 2003-01-21 | Nec Corp | Semiconductor device and method of manufacturing the same |
| CN104319258A (en) * | 2014-09-28 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | Through silicon via process |
| CN104377164A (en) * | 2014-09-28 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Through silicon var wafer interconnection process |
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| US9455158B2 (en) * | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
| CN104766806B (en) * | 2015-03-31 | 2018-06-26 | 武汉新芯集成电路制造有限公司 | The method of wafer three-dimensional integration |
| TWM518683U (en) * | 2015-12-31 | 2016-03-11 | Malzine Co Ltd | Structural improvement for storage basket |
| CN105742197B (en) * | 2016-03-11 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | A kind of bonding crystal circle structure and preparation method thereof |
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| TW518683B (en) * | 2000-07-24 | 2003-01-21 | Nec Corp | Semiconductor device and method of manufacturing the same |
| CN104319258A (en) * | 2014-09-28 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | Through silicon via process |
| CN104377164A (en) * | 2014-09-28 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Through silicon var wafer interconnection process |
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