CN108054137B - Metal interconnection structure and manufacturing method thereof - Google Patents
Metal interconnection structure and manufacturing method thereof Download PDFInfo
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- CN108054137B CN108054137B CN201711243083.7A CN201711243083A CN108054137B CN 108054137 B CN108054137 B CN 108054137B CN 201711243083 A CN201711243083 A CN 201711243083A CN 108054137 B CN108054137 B CN 108054137B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
Abstract
The invention provides a metal interconnection structure and a manufacturing method thereof.A substrate is provided with at least one metal interconnection layer, a dielectric layer is formed on the metal interconnection layer, the dielectric layer is etched to form a through hole, the through hole is filled with metal to form a through hole structure, and an aluminum lining layer is formed on the dielectric layer and the through hole structure. The aluminum liner layer can be used as a liner and a top metal layer, so that the top metal layer and a redistribution through hole layer are omitted, the process flow is simplified, and the production cost is reduced. Meanwhile, the thickness of the aluminum liner layer is reduced, whisker defects on the surface of the aluminum liner are reduced, and the influence on the subsequent process is reduced.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a metal interconnection structure and a manufacturing method thereof.
Background
In the back-end process of a semiconductor, a plurality of layers of metal interconnection structures can be arranged on a semiconductor substrate according to different requirements, each layer of metal interconnection structure comprises a metal interconnection line and an insulating layer, a groove and a through hole are formed in the insulating layer, then metal is deposited in the groove and the through hole, the deposited metal is the metal interconnection line, and copper is generally selected as a metal interconnection line material. Then, an aluminum pad is deposited on the basis of the structure, and the top interconnection structure is bonded with the aluminum pad to prepare for the subsequent packaging process.
In the conventional metal interconnect structure, the top metal layer 102 is connected to the aluminum pad layer 104 through the redistribution via layer 103 filled with aluminum, and the connection to the front metal interconnect layer 100 is realized through the via structure 101. The structure is shown in figure 1. The process comprises the following steps:
1. a substrate is provided, at least one metal interconnection layer 100 is formed on the substrate, and a first etching stop layer 110, a first insulating layer 120, a second etching stop layer 130 and a second insulating layer 140 are sequentially formed on the metal interconnection layer. The metal interconnection layer 100 (not shown in fig. 1) includes a dielectric layer and a metal layer formed in the dielectric layer;
2. sequentially etching the second insulating layer 140, the second etching stop layer 130, the first insulating layer 120 and the first etching stop layer 110 by adopting a photomask masking technology until the metal layer in the front metal interconnection layer 100 is exposed, and forming a metal through hole and a metal groove;
3. filling metal copper into the metal through hole and the metal groove, and planarizing by adopting Chemical Mechanical Polishing (CMP), so that the upper surface of the metal groove filled with copper is flush with the upper surface of the second insulating layer 140, and a through hole structure 101 and a top metal layer 102 are formed;
4. sequentially forming a third etch stop layer 150 and a third insulating layer 160 on the top metal layer 102 and the second insulating layer 140;
5. sequentially etching the third insulating layer 160 and the third etching stop layer 150 by using a photomask masking technique to form redistribution through holes;
6. depositing an aluminum layer on the redistribution via and the third insulating layer to form a redistribution via layer 103;
7. an aluminum pad layer 104 is etched on the aluminum layer using a photomask masking technique.
In the metal interconnection process, a photomask masking technology is used in the steps 2, 5 and 7, the process flow is complicated, and meanwhile, because aluminum is used as a liner, the critical dimension of the aluminum is large, and the thickness of aluminum deposition is thick. The thicker the aluminum pad, the greater the stress of the aluminum pad, and after the aluminum pad is deposited, whisker defects (whisker defects) on the surface of the aluminum pad are also aggravated, and when the size of the whisker defects is large enough, short circuits between adjacent aluminum pads are caused, and in the subsequent metallization pattern etching process, the etching is not clean, which affects the yield.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for manufacturing a metal interconnection structure, which comprises the following steps:
s01: providing a substrate, wherein at least one metal interconnection layer is formed on the substrate, and a dielectric layer is formed on the metal interconnection layer;
s02: etching the dielectric layer to form a through hole, and filling metal in the through hole to form a through hole structure;
s03: and forming an aluminum liner layer on the dielectric layer and the through hole structure.
Further, in step S01, the dielectric layer includes an etching stop layer and an insulating layer.
Further, in step S02, the via hole is filled with a metal, where the metal is copper or a copper-containing metal.
Further, in step S02, after the via hole is filled with metal, chemical mechanical polishing is performed.
Further, in step S02, the via exposes the metal interconnection layer.
Further, in step S02, the substrate includes a first region and a second region, and a dielectric layer, a via hole, a via structure, and an aluminum pad layer are formed in the first region, and the dielectric layer, the via hole, the via structure, and the aluminum pad layer are also formed in the second region.
Further, in step S02, the maximum diameter of the through hole in the second region is larger than the maximum diameter of the through hole in the first region.
Further, in step S02, the upper surface of the via structure in the first region is flush with the upper surface of the dielectric layer, and the upper surface of the via structure in the second region is lower than the upper surface of the dielectric layer.
Further, the step of forming the aluminum pad layer in step S03 includes:
forming an aluminum layer on the dielectric layer and the through hole structure;
the aluminum liner layer in the second area is provided with a recess which is used as an alignment mark;
and etching the aluminum layer in the first area through the alignment mark to form an aluminum liner layer.
Further, the thickness of the aluminum pad layer in step S03 is 100nm to 900nm, and the critical dimension is reduced by reducing the thickness of the aluminum pad layer, so that the aluminum pad layer can be used for wiring, thereby implementing the function of the top metal layer.
Correspondingly, the invention provides a metal interconnection structure, which is manufactured by the manufacturing method of the metal interconnection structure, and comprises the following steps:
the substrate is provided with at least one metal interconnection layer formed in the substrate;
a dielectric layer formed on the metal interconnection layer;
a via structure formed within the dielectric layer;
and the aluminum liner layer is formed on the dielectric layer and the through hole structure.
In summary, the present invention provides a metal interconnection structure and a method for fabricating the same, in which at least one metal interconnection layer is formed on a substrate, a dielectric layer is formed on the metal interconnection layer, the dielectric layer is etched to form a through hole, a metal is filled in the through hole to form a through hole structure, and an aluminum pad layer is formed on the dielectric layer and the through hole structure. The aluminum liner layer can be used as a liner and a top metal layer, so that the top metal layer and a redistribution through hole layer are omitted, the process flow is simplified, and the production cost is reduced.
Furthermore, compared with the prior art, the thickness of the aluminum lining layer is reduced, so that whisker-shaped defects on the surface of the aluminum lining layer are reduced, and the influence on the subsequent process is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a metal interconnect structure fabricated in the prior art;
FIG. 2 is a flow chart of a method for fabricating a metal interconnect structure according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a metal interconnect structure according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of an alignment mark in a second region of the prior art;
FIG. 5 is a schematic cross-sectional view of an alignment mark in a second region before copper recess is not implemented in accordance with the present invention;
FIG. 6 is a schematic cross-sectional view of the alignment mark in the second region after the copper recess is implemented according to the present invention.
Detailed Description
As described in the background art, the conventional method for manufacturing a metal interconnection structure has a complex process flow, and meanwhile, since aluminum is used as a liner, the critical dimension of the aluminum is large, the thickness of aluminum deposition is also thick, whisker defects (whiskerdefect) on the surface of the aluminum liner are also aggravated, when the size of the whisker defect is large enough, the adjacent aluminum liner is short-circuited, and in the subsequent metallization pattern etching process, the etching is not clean, which affects the yield.
Considering that metal aluminum can also be used as a metal wire and exhibits excellent performance at a certain line width, an aluminum liner layer can be used as both a liner and a top metal layer in a metal interconnection structure.
The invention provides a method for manufacturing a metal interconnection structure, which uses an aluminum liner layer as a liner and a top metal layer, omits the top metal layer and a redistribution through hole layer, simplifies the process flow, reduces the production cost, reduces the thickness of the aluminum liner layer, reduces the whisker-shaped defects on the surface of the aluminum liner, and reduces the influence on the subsequent process.
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
Fig. 2 is a flow chart of a method for fabricating a metal interconnection structure according to an embodiment of the present invention, fig. 3 is a schematic cross-sectional view of a metal interconnection structure according to an embodiment of the present invention,
as shown in fig. 2, the present invention provides a method for manufacturing a metal interconnection structure, which includes the following steps:
s01: providing a substrate, wherein at least one metal interconnection layer is formed on the substrate, and a dielectric layer is formed on the metal interconnection layer;
s02: etching the dielectric layer to form a through hole, and filling metal in the through hole to form a through hole structure;
s03: and forming an aluminum liner layer on the dielectric layer and the through hole structure.
The specific steps of the above method will be described in detail with reference to fig. 2 and 3.
In step S01, a substrate having at least one metal interconnection layer 300 formed thereon is provided, and a dielectric layer is formed on the metal interconnection layer 300.
The substrate may be a silicon substrate, or may be a substrate made of other suitable semiconductor materials, for example, a germanium substrate or a germanium-silicon substrate, which is not shown in fig. 3. Various semiconductor structures, such as active semiconductor devices, passive semiconductor devices, and the like, may be formed on the substrate.
At least one metal interconnection layer is formed on the substrate, and the method for manufacturing the metal interconnection layer is well known to those skilled in the art and is not described herein in detail. Only one metal interconnect layer 300 is shown in fig. 3, and the metal interconnect layer 300 includes a dielectric layer and a metal layer formed in the dielectric layer.
A dielectric layer is formed on the metal interconnection layer 300, and the dielectric layer includes an etch stop layer 310 and an insulating layer 320. The upper insulating layer 320 is generally thicker and the lower etch stop layer 310 is generally thinner. In this embodiment, the etching stop layer 310 is preferably silicon nitride, and the insulating layer 320 is preferably silicon oxide.
In step S02, the dielectric layer is etched to form a through hole, and the through hole is filled with metal to form the through hole structure 301.
Firstly, forming a photoresist layer on the insulating layer 320, exposing and developing the photoresist layer to form a patterned photoresist layer, exposing the insulating layer 320 at a position where a through hole is to be formed, then, etching the insulating layer 320 by using the patterned photoresist layer as a mask until the etching stop layer 310 is formed, continuing to etch the etching stop layer 310 until the metal interconnection layer 300 is exposed, specifically, exposing the metal layer in the metal interconnection layer 300, and finally removing the photoresist layer by an ashing process to form the through hole.
Then, the through hole is filled with copper by electroplating, and is planarized by chemical mechanical polishing, so as to form the through hole structure 301.
In step S03, an aluminum pad layer 302 is formed on the dielectric layer and the via structure 301.
Firstly, a thin metal aluminum layer is deposited on the insulating layer 320 and the through hole structure 301, a photoresist layer is formed on the metal aluminum layer, the photoresist is exposed and developed, the metal aluminum layer is exposed, a patterned photoresist layer is formed, then the patterned photoresist layer is used for masking, the metal aluminum layer is etched, and the aluminum pad layer 302 is formed.
The thickness of the aluminum pad layer 302 is 100nm-900nm, and the critical dimension is reduced by reducing the thickness of the aluminum pad layer, so that the aluminum pad layer can be used for wiring, and the function of a top metal layer is realized. Preferably, the aluminum liner layer 302 sequentially includes a lower diffusion-preventing layer, an aluminum layer and an upper anti-reflection layer on the insulating layer 320 and the via structure 301, and may be manufactured by a method in the prior art, which is not described herein again.
The difficulty in the process development of the present invention is the alignment of the through holes during the aluminum pad photolithography process. In the prior art, an alignment mark in another region of a substrate is generally used to align a through hole in an aluminum pad lithography process, that is, the substrate includes two regions, the first region is a chip region, the second region is an alignment mark region, and when a dielectric layer, a through hole structure, and an aluminum pad layer are formed in the first region (as described above), the dielectric layer, the through hole structure, and the aluminum pad layer are also formed in the second region, and an alignment mark is formed in the second region to implement the lithography process in the first region. The alignment mark does not belong to a wiring area of a circuit design, does not relate to connection between metals, is only a mark for assisting a photoetching process, and is not required to be connected with a previous layer of metal.
Fig. 4 is a schematic diagram of a conventional process at an Alignment Mark (Alignment Mark) in the second region, and since a redistribution via layer 401 is provided in the metal interconnect structure in the conventional process, an aluminum recess is formed at the redistribution via layer 401 when an aluminum layer 402 is deposited on the dielectric layer 400 and the redistribution via layer 401. In the process of performing the aluminum liner photolithography process, alignment can be performed through the aluminum recess at the alignment mark, but in the manufacturing method of the present invention, since the through hole is filled with copper and ground flat, after the aluminum layer 502 is deposited on the dielectric layer 500 and the through hole structure 501, the aluminum layer 502 on the through hole structure 501 is flat as in other regions, as shown in fig. 5, during the process of performing the aluminum liner layer photolithography process, the alignment mark is difficult to find, which causes alignment difficulty during photolithography, and subsequent steps cannot be performed.
In order to solve the above problems, the present invention utilizes a copper dishing (dishing) phenomenon, which is commonly seen in a copper polishing process. Copper dishing is a process defect for normal processes, and causes a decrease in the contact between two layers of metal (metal and via) and connectivity problems, and is therefore avoided in the process. The manufacturing method used by the invention can just utilize the phenomenon to make the copper recess at the position of the alignment mark as large as possible, so that the recess can be formed after the aluminum deposition, and the visibility of the alignment mark is enhanced, as shown in figure 6. The implementation method comprises the following steps: providing a substrate, where the substrate includes a first region and a second region, and while forming a dielectric layer, a via hole structure, and an aluminum pad layer in the first region (please refer to fig. 3 and related steps), the dielectric layer, the via hole structure, and the aluminum pad layer (please refer to fig. 6) are also formed in the second region, and an alignment mark is formed in the second region by controlling related process parameters, as shown in fig. 3 and 6, the specific steps are as follows:
first, in step S02, the dielectric layer is etched to form a via hole, such that the maximum diameter D of the via hole in the second region is obtained1Is larger than the maximum diameter D of the through hole in the first region2E.g. D1＝5D2，D1＝10D2Etc.;
secondly, filling metal copper in the through hole to form a through hole structure, wherein the diameter of the through hole in the first region is smaller than that of the through hole in the second region, and the two are at the same height, so that the capacity of the through hole in the first region is smaller than that of the through hole in the second region, and after the through hole structure is formed by filling the metal copper in the through hole, the upper surface of the through hole structure 301 in the first region is flush with the upper surface of the dielectric layer (insulating layer) 320, and the upper surface of the through hole structure 601 in the second region is lower than that of the dielectric layer (insulating layer) 600;
and then, forming an aluminum layer on the dielectric layer and the through hole structure. The aluminum layer on the via structure 301 in the first region is flat as in other regions, the aluminum layer 602 on the via structure 601 in the second region has a recess 603, and the recess 603 serves as an alignment mark;
finally, the aluminum layer in the first region is etched through the alignment mark 603, so as to form an aluminum pad layer 302.
In this embodiment, by controlling the copper filling amount of the through hole, the influence of the copper recess on the through hole structure 301 in the first region is avoided, and the copper recess of the through hole structure 601 in the second region is obvious, so that the aluminum recess 603 is formed after depositing the aluminum layer, and in the process of the aluminum pad layer 302 photolithography process, the aluminum recess 603 is used as an alignment mark to complete photolithography.
Correspondingly, the present invention further provides a metal interconnection structure, which is manufactured by the above manufacturing method of the metal interconnection structure, and please refer to fig. 3, where the metal interconnection structure includes:
a substrate (not shown), at least one metal interconnection layer 300 formed in the substrate;
a dielectric layer (an etching stop layer 310 and an insulating layer 320) formed on the metal interconnection layer;
a via structure 301 formed within the dielectric layer;
an aluminum pad layer 302 formed on the dielectric layer and via structure.
In summary, the present invention provides a metal interconnection structure and a method for fabricating the same, in which at least one metal interconnection layer is formed on a substrate, a dielectric layer is formed on the metal interconnection layer, the dielectric layer is etched to form a through hole, a metal is filled in the through hole to form a through hole structure, and an aluminum pad layer is formed on the dielectric layer and the through hole structure. The aluminum liner layer can be used as a liner and a top metal layer, so that the top metal layer and a redistribution through hole layer are omitted, the process flow is simplified, and the production cost is reduced.
Furthermore, compared with the prior art, the thickness of the aluminum lining layer is reduced, so that whisker-shaped defects on the surface of the aluminum lining layer are reduced, and the influence on the subsequent process is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (5)
1. A manufacturing method of a metal interconnection structure is characterized by comprising the following steps:
s01: providing a substrate, wherein at least one metal interconnection layer is formed on the substrate, and a dielectric layer is formed on the metal interconnection layer;
s02: etching the dielectric layer to form a through hole, filling metal copper in the through hole, and carrying out chemical mechanical polishing to form a through hole structure;
s03: forming an aluminum liner layer on the dielectric layer and the through hole structure;
the substrate comprises a first area and a second area, wherein a dielectric layer, a through hole structure and an aluminum backing layer are formed in the first area, the dielectric layer, the through hole structure and the aluminum backing layer are also formed in the second area, the through hole in the first area and the through hole in the second area are at the same height, the diameter of the through hole in the second area is larger than that of the through hole in the first area, and the step of forming the aluminum backing layer in the first area comprises the following steps:
forming an aluminum layer on the dielectric layer and the through hole structure;
the aluminum layer in the second area is provided with a recess which is used as an alignment mark;
and etching the aluminum layer in the first area through the alignment mark to form an aluminum liner layer.
2. The method of claim 1, wherein the dielectric layer comprises an etch stop layer and an insulating layer in sequence.
3. The method of claim 1, wherein the via in the first region exposes the metal interconnect layer.
4. The method of claim 1, wherein an upper surface of the via structure in the first region is flush with an upper surface of the dielectric layer, and an upper surface of the via structure in the second region is lower than the upper surface of the dielectric layer.
5. The method of claim 1, wherein the aluminum liner layer has a thickness of 100nm to 900 nm.
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