CN212570982U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN212570982U CN212570982U CN202021912435.0U CN202021912435U CN212570982U CN 212570982 U CN212570982 U CN 212570982U CN 202021912435 U CN202021912435 U CN 202021912435U CN 212570982 U CN212570982 U CN 212570982U
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Abstract
The utility model provides a semiconductor structure includes Si substrate, insulating layer and Cu post, wherein, the Cu post is arranged in the Si substrate, the lateral wall and the bottom of insulating layer cladding Cu post contact with the Si substrate, and the Cu post has first difference in height D1 with the insulating layer, the Si substrate has second difference in height D2 with the insulating layer, and second difference in height D2 is greater than first difference in height D1; the Cu column and the insulating layer have a first height difference D1, so that the electrical property of the device can be effectively prevented from being influenced; furthermore, the Si substrate and the insulating layer have a second height difference D2, and the second height difference D2 is greater than the first height difference D1, so that the connection of Cu metal on the inner side and the outer side of the insulating layer can be further avoided, and the electrical property of the device is effectively prevented from being influenced.
Description
Technical Field
The utility model belongs to the semiconductor manufacturing field relates to semiconductor structure.
Background
With the functions of integrated circuits becoming stronger and the performance and integration level becoming higher and higher, the packaging technology plays an increasingly important role in integrated circuit products, and the proportion of the packaging technology in the value of the whole electronic system becomes larger and larger. Wafer Level Package (WLP) technology has the advantages of miniaturization, low cost, high integration level, better performance, and higher energy efficiency, and thus has become an important packaging method for electronic devices such as mobile/wireless networks with high requirements, and is one of the most promising packaging technologies at present.
And a re-wiring layer (RDL) which can re-arrange the welding area positions of the welding pads of the chip and arrange the new welding areas according to an array, so that the RDL is widely applied to the WLP process. With the development of packaging technology, high-density and small-pitch RDL metal lines are urgently needed.
In the prior art, Cu metal is widely used in a WLP process as a conductive material, but because Cu metal has malleability, it is easy to remain Cu metal after a planarization process, and the remaining Cu metal may affect the electrical performance of a prepared device with high density and small pitch.
Therefore, it is necessary to provide a semiconductor structure to completely remove the residual Cu metal.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor structure for solving the problem of Cu metal remaining after the planarization process in the prior art.
To achieve the above and other related objects, the present invention provides a semiconductor structure, comprising: the Cu column is positioned in the Si substrate, the insulating layer covers the side wall and the bottom of the Cu column and is in contact with the Si substrate, the Cu column and the insulating layer have a first height difference, the Si substrate and the insulating layer have a second height difference, and the second height difference is larger than the first height difference.
Optionally, the range of the first height difference includes 0.1 μm to 0.5 μm.
Optionally, the second height difference ranges from 2 μm to 5 μm.
Optionally, a metal seed layer is further included between the insulating layer and the Cu pillar, and the metal seed layer and the Cu pillar have the same height.
Optionally, the insulating layer comprises SiO2Layer and Si3N4One or a combination of layers.
As described above, the semiconductor structure of the present invention includes the Si substrate, the insulating layer, and the Cu pillar, wherein the Cu pillar is located in the Si substrate, the insulating layer covers the sidewall and the bottom of the Cu pillar and contacts with the Si substrate, and the Cu pillar and the insulating layer have the first height difference D1, the Si substrate and the insulating layer have the second height difference D2, and the second height difference D2 is greater than the first height difference D1; the Cu column and the insulating layer have a first height difference D1, so that the electrical property of the device can be effectively prevented from being influenced; furthermore, the Si substrate and the insulating layer have a second height difference D2, and the second height difference D2 is greater than the first height difference D1, so that the connection of Cu metal on the inner side and the outer side of the insulating layer can be further avoided, and the electrical property of the device is effectively prevented from being influenced.
Drawings
FIG. 1 is a schematic diagram of a process flow for fabricating a semiconductor structure according to an embodiment.
FIG. 2 is a schematic structural diagram of the embodiment after planarization.
FIG. 3 is a schematic structural diagram of the embodiment after wet processing.
FIG. 4 is a schematic structural diagram after dry etching in the example.
Description of the element reference numerals
100 Si substrate
200 insulating layer
300 Cu column
400 Cu metal residue
D1 first difference in height
D2 second height difference
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Referring to fig. 1 to 4, the present embodiment provides a method for manufacturing a semiconductor structure, including the following steps:
providing a Si substrate 100;
patterning the Si substrate 100 to form a trench (not shown);
forming an insulating layer 200 in the trench to cover the bottom and sidewalls of the trench;
forming a Cu pillar 300 to fill the trench;
performing planarization to expose the Si substrate 100, the insulating layer 200 and the Cu pillars 300;
performing wet processing to remove the Cu metal residue 400 and a portion of the Cu pillar 300, so that the Cu pillar 300 and the insulating layer 200 have a first height difference D1;
the Si substrate 100 is dry etched such that the Si substrate 100 and the insulating layer 200 have a second height difference D2, and the second height difference D2 is greater than the first height difference D1.
In the method for manufacturing the semiconductor structure of this embodiment, after the planarization, the Cu metal residue 400 may be removed by the wet process, and the Cu pillar 300 and the insulating layer 200 have the first height difference D1, and further, a portion of the Si substrate 100 is removed by the dry etching, so that the Si substrate 100 and the insulating layer 200 have the second height difference D2, and the second height difference D2 is greater than the first height difference D1, thereby further avoiding the connection of the Cu metal inside and outside the insulating layer 200, and effectively avoiding the influence on the electrical performance of the device.
Referring to fig. 1, first, a Si substrate 100 is provided, and the Si substrate 100 is patterned to form a trench (not shown).
Specifically, the method of patterning the Si substrate 100 may use a conventional photolithography method, such as patterning using a mask, which may include, but is not limited to, a photoresist. The depth, width and distribution of the trenches can be selected as desired and are not overly limited herein.
Next, an insulating layer 200 is formed in the trench to cover the bottom and sidewalls of the trench.
As an example, the insulating layer 200 includes SiO2One or a combination of the layer and the Si3N4 layer can effectively prevent the formation of a conductive channel between the Cu pillar 300 formed later and the Si substrate 100 through the insulating layer 200 covering the bottom and the sidewall of the trench, thereby achieving a good insulating effect. The specific forming method, thickness and material of the insulating layer 200 may be selected according to the requirement, and are not limited herein. In this embodiment, the insulating layer 200 is made of SiO2Layer, but not limited thereto, the insulating layer 200 may also employ Si3N4Layer or SiO2Layer and Si3N4A stack of layers.
Illustratively, a step of forming a metal seed layer (not shown) is further included after the insulating layer 200 is formed and before the Cu pillar 300 is formed.
Specifically, the metal seed layer may be formed on the surface of the insulating layer 200 by a PVD method, and the metal seed layer may include a Ti/Cu metal seed layer or a Cu metal seed layer, but is not limited thereto and may be specifically selected according to needs. Preferably, the metal seed layer is a Cu metal seed layer, so that when the first height difference D1 is formed subsequently, the metal seed layer and the Cu pillar 300 have the same etching rate, and the metal seed layer and the Cu pillar 300 have the same height, thereby preventing the metal seed layer from being connected to the Cu metal outside the insulating layer 200.
Then, the Cu pillar 300 is formed to fill the trench.
Specifically, when the metal seed layer is disposed in the trench, the Cu pillar 300 may be formed by an electroplating method, but is not limited thereto, and for example, the Cu pillar 300 may also be formed by a patterned mask and a deposition method, which is not limited herein.
Next, planarization is performed to expose the Si substrate 100, the insulating layer 200, and the Cu pillars 300.
Illustratively, the planarization includes one or a combination of mechanical polishing and chemical mechanical polishing.
Specifically, in the embodiment, mechanical polishing is performed first, and then finer chemical mechanical polishing is performed, so as to obtain a smoother surface, but the planarization process is not limited thereto, and only mechanical polishing or only chemical mechanical polishing may be used as required, and is not limited herein. However, since Cu metal has good malleability, Cu metal residue 400 is formed near the edges of the Cu pillars 300 during the planarization process, and the Cu metal residue affects the electrical performance of the subsequently fabricated high-density, small-pitch devices, and therefore, the Cu metal residue 400 needs to be completely removed, see fig. 2.
Next, referring to fig. 3, a wet process is performed to remove the Cu metal residue 400 and a portion of the Cu pillar 300, so that the Cu pillar 300 and the insulating layer 200 have a first height difference D1.
As an example, the treatment liquid adopted by the wet treatment comprises an acidic solution which is chemically reacted with Cu metal, and the acidic solution comprises H2O2、H3PO4And H2SO4One or a mixed solution.
Specifically, the Cu metal residue 400 located at the edge of the Cu pillar 300 can be effectively removed by the wet process of the acidic solution, and further, the acidic solution can also remove a portion of the Cu pillar 300, so that the Cu pillar 300 and the insulating layer 200 have the first height difference D1, thereby further preventing the Cu metal residue 400 which is not completely removed from contacting the Cu pillar 300, so as to improve the electrical performance of a subsequently manufactured device.
By way of example, the range of the first height difference D1 includes 0.1 μm to 0.5 μm.
Specifically, the larger the value of the first height difference D1 is, the more beneficial it is to avoid the Cu metal residue 400 from contacting the Cu pillar 300, but the larger the first height difference D1 is, the more the insulating layer 200 may have defects such as cracks in the subsequent grinding process, and the more the insulating layer 300 may have a potential for electrical conduction between the Si substrate 100 and the Cu pillar 300, and therefore, in this embodiment, the first height difference D1 is preferably 0.3 μm, but is not limited thereto, and may also be, for example, 0.2 μm, 0.4 μm, and the like.
Next, referring to fig. 4, the Si substrate 100 is dry etched such that the Si substrate 100 and the insulating layer 200 have a second height difference D2, and the second height difference D2 is greater than the first height difference D1.
Specifically, by the dry etching, the Si substrate 100 and the insulating layer 200 have the second height difference D2, and the second height difference D2 is greater than the first height difference D1, so that the connection of Cu metal inside and outside the insulating layer 200 can be further avoided, and the electrical performance of the device is effectively prevented from being affected.
As an example, the range of the second height difference D2 includes 2 μm to 5 μm.
Specifically, the larger the value of the second height difference D2 is, the more beneficial it is to avoid the Cu metal residue 400 from contacting the Cu pillar 300, but the larger the second height difference D2 is, the more the insulating layer 200 may have defects such as cracks in the subsequent grinding process, and the more the insulating layer 300 may have a potential for electrical conduction between the Si substrate 100 and the Cu pillar 300, and therefore, in this embodiment, the second height difference D2 is preferably 3 μm, but is not limited thereto, and may also be, for example, 2 μm or 4 μm.
Referring to fig. 4, the present embodiment further provides a semiconductor structure, which can be manufactured by the above method, but is not limited thereto.
Specifically, the semiconductor structure comprises a Si substrate 100, an insulating layer 200 and a Cu pillar 300, wherein the Cu pillar 300 is located in the Si substrate 100, the insulating layer 200 covers the sidewall and the bottom of the Cu pillar 300 and is in contact with the Si substrate 100, the Cu pillar 300 and the insulating layer 200 have a first height difference D1, the Si substrate 100 and the insulating layer 200 have a second height difference D2, and the second height difference D2 is greater than the first height difference D1.
In the semiconductor structure of this embodiment, since the Cu pillar 300 and the insulating layer 200 have the first height difference D1, the electrical performance of the device can be effectively prevented from being affected; further, since the Si substrate 100 and the insulating layer 200 have the second height difference D2, and the second height difference D2 is greater than the first height difference D1, connection between the Cu metal inside and outside the insulating layer 200 can be further avoided, so as to effectively avoid affecting electrical performance of the device.
By way of example, the range of the first height difference D1 includes 0.1 μm to 0.5 μm.
Specifically, the larger the value of the first height difference D1 is, the more beneficial it is to avoid the Cu metal residue from contacting the Cu pillar 300, but the larger the first height difference D1 is, the more the insulating layer 200 may have defects such as cracks in the subsequent grinding process, and the more the insulating layer 300 may have a potential for electrical conduction between the Cu pillar 300 and the Si substrate 100, and therefore, in this embodiment, the first height difference D1 is preferably 0.3 μm, but is not limited thereto, and may also be, for example, 0.2 μm, 0.4 μm, and the like.
As an example, the range of the second height difference D2 includes 2 μm to 5 μm.
Specifically, the larger the second height difference D2 is, the more beneficial it is to avoid the Cu metal residue from contacting the Cu pillar 300, but the larger the second height difference D2 is, the more the insulating layer 200 may have defects such as cracks in the subsequent grinding process, and the more the insulating layer 300 may have a potential for electrical conduction between the Si substrate 100 and the Cu pillar 300, so in this embodiment, the second height difference D2 is preferably 3 μm, but is not limited thereto, and may also be, for example, 2 μm or 4 μm.
As an example, a metal seed layer (not shown) is further included between the insulating layer 200 and the Cu pillar 300, and the metal seed layer and the Cu pillar 300 have the same height.
Specifically, the metal seed layer may include a Ti/Cu metal seed layer or a Cu metal seed layer, but is not limited thereto, and may be selected according to needs. Preferably, the metal seed layer is a Cu metal seed layer, and the metal seed layer and the Cu pillar 300 have the same height, so as to prevent the metal seed layer from being connected to the Cu metal outside the insulating layer 200.
As an example, the insulating layer 200 includes SiO2Layer and Si3N4One or a combination of layers.
Specifically, the insulating layer 200 can effectively prevent a conductive channel from being formed between the Cu pillar 300 and the Si substrate 100, thereby achieving a good insulating effect. The specific forming method, thickness and material of the insulating layer 200 may be selected according to the requirement, and are not limited herein. In this embodiment, the insulating layer 200 is made of SiO2Layer, but not limited thereto, the insulating layer 200 may also employ Si3N4Layer or SiO2Layer and Si3N4A stack of layers.
To sum up, the semiconductor structure of the present invention includes a Si substrate, an insulating layer and a Cu pillar, wherein the Cu pillar is located in the Si substrate, the insulating layer covers the sidewall and the bottom of the Cu pillar and contacts with the Si substrate, and the Cu pillar and the insulating layer have a first height difference D1, the Si substrate and the insulating layer have a second height difference D2, and the second height difference D2 is greater than the first height difference D1; the Cu column and the insulating layer have a first height difference D1, so that the electrical property of the device can be effectively prevented from being influenced; furthermore, the Si substrate and the insulating layer have a second height difference D2, and the second height difference D2 is greater than the first height difference D1, so that the connection of Cu metal on the inner side and the outer side of the insulating layer can be further avoided, and the electrical property of the device is effectively prevented from being influenced.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A semiconductor structure, comprising: the Cu column is positioned in the Si substrate, the insulating layer covers the side wall and the bottom of the Cu column and is in contact with the Si substrate, the Cu column and the insulating layer have a first height difference, the Si substrate and the insulating layer have a second height difference, and the second height difference is larger than the first height difference.
2. The semiconductor structure of claim 1, wherein: the first height difference ranges from 0.1 μm to 0.5 μm.
3. The semiconductor structure of claim 1, wherein: the second height difference is in the range of 2 to 5 μm.
4. The semiconductor structure of claim 1, wherein: a metal seed layer is further arranged between the insulating layer and the Cu column, and the metal seed layer and the Cu column have the same height.
5. The semiconductor structure of claim 1, wherein: the insulating layer comprises SiO2Layer and Si3N4One or a combination of layers.
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| CN202021912435.0U CN212570982U (en) | 2020-09-04 | 2020-09-04 | Semiconductor structure |
| US17/465,449 US11973046B2 (en) | 2020-09-04 | 2021-09-02 | Semiconductor structure and method for preparing the same |
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| CN114141699A (en) * | 2020-09-04 | 2022-03-04 | 盛合晶微半导体(江阴)有限公司 | Semiconductor structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114141699A (en) * | 2020-09-04 | 2022-03-04 | 盛合晶微半导体(江阴)有限公司 | Semiconductor structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |