CN117153777A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117153777A
CN117153777A CN202311126040.6A CN202311126040A CN117153777A CN 117153777 A CN117153777 A CN 117153777A CN 202311126040 A CN202311126040 A CN 202311126040A CN 117153777 A CN117153777 A CN 117153777A
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China
Prior art keywords
substrate
back surface
dielectric layer
silicon
hole
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CN202311126040.6A
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Inventor
曾淑文
毛亚会
曾虹铭
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United Microelectronics Center Co Ltd
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United Microelectronics Center Co Ltd
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Priority to CN202311126040.6A priority Critical patent/CN117153777A/en
Publication of CN117153777A publication Critical patent/CN117153777A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: thinning and etching the back of the substrate structure provided with the through silicon via structure and the marking through hole structure, exposing the marking through hole structure, depositing a second dielectric layer on the back, arranging an opening structure at a position corresponding to the through silicon via structure, arranging a third dielectric layer on the side wall of the opening structure, removing the first dielectric layer on the bottom surface of the opening structure, integrally forming a back metal wiring layer on the surfaces of the opening structure and the second dielectric layer, and chemically and mechanically polishing the back metal wiring layer to make the surface flat. The application realizes the self-alignment of the back surface through the arrangement that the mark through hole structure is higher than the silicon through hole structure; meanwhile, the back metal and the patterned metal on the back are integrally formed and then flattened, so that the process steps for flattening the TSV back metal can be saved, and the production cost is reduced; in addition, through arranging the back metal wiring layer and then flattening, the flat and stable silicon through hole leading-out end surface with controllable process is obtained by a simple process, and the back multilayer wiring is realized.

Description

Semiconductor structure and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
The semiconductor technology is rapidly developed, the feature size of the integrated circuit is continuously reduced, and the conventional two-dimensional package cannot meet the requirements of the industry, so that the stacking mode based on the vertical interconnection of the TSVs (Through Silicon Via, through silicon vias) becomes the main stream direction of the development of the packaging technology due to the key advantages of short-distance interconnection and high-density integration.
The TSV technology is used for manufacturing vertical through holes among different device structures through etching and other technologies, and then metal is filled in the through holes to form conductive columns, so that electric interconnection is realized. By adopting a Via-First (Via-First) method, since the depth of the Via is smaller than the thickness of the substrate, metal is leaked from the back of the device through an etching process after the back of the device is thinned, and the heights of the leaked conductive posts are inconsistent in this way, so that the subsequent metal wiring process is affected.
Therefore, there is a need for a simple process that results in a planar TSV backside exposed metal.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solutions of the present application and is thus convenient for a person skilled in the art to understand, and it should not be construed that the above technical solutions are known to the person skilled in the art merely because these solutions are described in the background art section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a semiconductor structure and a method for fabricating the same, which are used for solving the problems of flatness and process efficiency of the exposed metal on the backside of the TSV in the prior art.
In order to achieve the above object, the present application provides a method for manufacturing a semiconductor structure, the method comprising:
arranging a through silicon via structure and a marked through hole structure in a substrate structure, wherein the substrate structure comprises a front surface and a back surface which are oppositely arranged, and the minimum distance from the marked through hole structure to the back surface of the substrate structure is smaller than the minimum distance from the through silicon via structure to the back surface of the substrate structure; a front metal layer structure is arranged on the front side of the substrate structure, and the front metal layer structure is in effective electrical connection with the through silicon via structure; the through silicon via structure, the marking through hole structure and the front metal layer structure are wrapped by a first dielectric layer;
bonding the front metal layer structure on a temporary substrate through a bonding layer, thinning the back surface of the substrate structure, wherein the through silicon via structure and the marking through hole structure are not exposed after thinning; etching the back surface of the substrate structure on the whole surface to expose the mark through hole structure with preset height as a counterpoint mark, wherein the silicon through hole structure is not exposed yet;
a second dielectric layer is arranged on the back surface of the substrate structure, and an opening structure is arranged on the back surface of the substrate structure at a position corresponding to the through silicon via structure so as to expose the first dielectric layer wrapping the through silicon via structure;
a third dielectric layer is arranged on the side wall of the opening structure, and the first dielectric layer which is exposed on the bottom surface of the opening structure and wraps the silicon through hole structure is removed;
filling back metal in the opening structure, and forming patterned metal on the surface of the second dielectric layer at the same time, wherein the patterned metal and the back metal are integrally formed to form a back metal wiring layer; and carrying out chemical mechanical polishing on the back metal wiring layer to make the surface flat.
Optionally, the length of the marking through hole structure parallel to the substrate structure is L1, and the length of the silicon through hole structure parallel to the substrate structure is L2, and L1> L2.
Alternatively, the ratio of L1 to L2 is greater than 1 and less than 1.2.
Optionally, after the back surface of the substrate structure is etched on the whole surface, the surface of the mark through hole structure, which is close to the back surface of the substrate structure, is 3 micrometers-10 micrometers higher than the surface of the silicon through hole structure, which is close to the back surface of the substrate structure.
Optionally, after the back surface of the substrate structure is etched on the whole surface, the height of the marked through hole structure exposed on the back surface of the substrate structure is less than 3 micrometers.
Optionally, the second dielectric layer has a thickness greater than 0.5 microns.
Optionally, an included angle θ between the sidewall and the bottom surface of the opening structure is greater than 90 degrees and less than 180 degrees.
Optionally, the maximum diameter of the opening structure is smaller than the diameter of the through silicon via structure.
Optionally, a thickness of the third dielectric layer on the sidewall of the opening structure is greater than 0.2 micrometers.
The application also provides a semiconductor structure which is obtained by adopting any one of the preparation methods,
as described above, the semiconductor structure and the method for manufacturing the same of the present application have the following beneficial effects:
the application realizes the self-alignment of the back surface through the arrangement that the mark through hole structure is higher than the silicon through hole structure;
the application utilizes the integrated forming of the back metal and the patterned metal on the back to planarize, thereby saving the process steps for realizing the planarization of the TSV back metal and reducing the production cost;
the application realizes the back multilayer wiring by arranging the back metal wiring layer and flattening, and obtaining the flat and stable silicon through hole leading-out end surface with controllable process by using a simple process.
Drawings
Fig. 1 is a schematic diagram showing a structure of a through-silicon via structure and a labeled through-hole structure in step 1 in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Fig. 2 is a schematic diagram showing a structure of the back surface of the thinned and etched substrate structure in step 2 in the method for manufacturing a semiconductor structure according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram showing a second dielectric layer and an opening structure disposed in step 3 in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram showing the third dielectric layer disposed in step 4 in the method for manufacturing a semiconductor structure according to an embodiment of the present application.
Fig. 5 is a schematic diagram showing a structure of providing a back metal wiring layer and planarizing a surface in step 5 in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Description of element reference numerals
10. A substrate structure; 11. a through silicon via structure; 12. marking the through hole structure; 13. a front side metal layer structure; 14. a first dielectric layer;
21. a bonding layer; 22. a temporary substrate; 23. a second dielectric layer; 24. an opening structure; 25. a third dielectric layer; 26. a back metal wiring layer; 261. a back metal; 262. patterning the metal.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Embodiment one:
as shown in fig. 1 to 5, the present application provides a method for preparing a semiconductor structure, which includes:
step 1: providing a through silicon via structure 11 and a marked through hole structure 12 in a substrate structure 10, wherein the substrate structure 10 comprises a front surface and a back surface which are oppositely arranged, and the minimum distance from the marked through hole structure 12 to the back surface of the substrate structure 10 is smaller than the minimum distance from the through silicon via structure 11 to the back surface of the substrate structure 10; a front metal layer structure 13 is arranged on the front surface of the substrate structure 10, and the front metal layer structure 13 is in effective electrical connection with the through silicon via structure 11; the through silicon via structure 11, the marking through hole structure 12 and the front side metal layer structure 13 are wrapped by a first dielectric layer 14;
step 2: bonding the front metal layer structure 13 to a temporary substrate 22 through a bonding layer 21, and thinning the back surface of the substrate structure 10, wherein the through silicon via structure 11 and the marking through hole structure 12 are not exposed after thinning; etching the back surface of the substrate structure 10 entirely to expose the mark through hole structure 12 with a preset height as an alignment mark, wherein the through silicon hole structure 11 is not exposed yet;
step 3: a second dielectric layer 23 is disposed on the back surface of the substrate structure 10, and an opening structure 24 is disposed on the back surface of the substrate structure 10 at a position corresponding to the through-silicon via structure 11 to expose the first dielectric layer 14 wrapping the through-silicon via structure 11;
step 4: a third dielectric layer 25 is arranged on the side wall of the opening structure 24, and the first dielectric layer 14 wrapping the through silicon via structure 11, which is exposed on the bottom surface of the opening structure 24, is removed;
step 5: filling back metal 261 in the opening structure 24, and forming patterned metal 262 on the surface of the second dielectric layer 23, wherein the patterned metal 262 and the back metal 261 are integrally formed to form a back metal wiring layer 26; the backside metal wiring layer 26 is subjected to chemical mechanical polishing to planarize the surface.
The method for fabricating a semiconductor structure according to the present application will be described in detail with reference to the accompanying drawings, wherein, it should be noted that the above-mentioned sequence does not strictly represent the sequence of the method for fabricating the semiconductor structure protected by the present application, and those skilled in the art can vary depending on the actual fabrication steps.
Firstly, as shown in fig. 1, step 1 is performed, a through-silicon via structure 11 and a marked through-hole structure 12 are disposed in a substrate structure 10, the substrate structure 10 includes a front surface and a back surface disposed opposite to each other, and a minimum distance from the marked through-hole structure 12 to the back surface of the substrate structure 10 is smaller than a minimum distance from the through-silicon via structure 11 to the back surface of the substrate structure 10; a front metal layer structure 13 is arranged on the front surface of the substrate structure 10, and the front metal layer structure 13 is in effective electrical connection with the through silicon via structure 11; the through-silicon via structure 11, the via mark structure 12 and the front side metal layer structure 13 are surrounded by a first dielectric layer 14.
In one embodiment, the length of the marking through hole structure 12 parallel to the substrate structure 10 is L1, and the length of the through silicon hole structure 11 parallel to the substrate structure 10 is L2, L1> L2.
According to the application, by setting the length relation between L1 and L2, the fact that the back surface height of the through silicon via structure 11 is lower than the back surface height of the mark through hole structure 12 under the subsequent TSV preparation process condition with the same depth-to-width ratio is realized, so that the through silicon via structure 11 is not exposed when the mark through hole structure 12 is etched, and the influence of metal pollution or the influence of the height uniformity of the through silicon via structure 11 on the flatness of the subsequent back surface metal 261 is avoided.
In one embodiment, the ratio of L1 to L2 is greater than 1 and less than 1.2.
Then, as shown in fig. 2, step 2 is performed, wherein the front metal layer structure 13 is bonded to a temporary substrate 22 through a bonding layer 21, the back surface of the substrate structure 10 is thinned, and neither the through-silicon via structure 11 nor the marked through-hole structure 12 is exposed after thinning; the back surface of the substrate structure 10 is etched entirely to expose the via structures 12 with a predetermined height as alignment marks, and the via structures 11 are not exposed yet.
In one embodiment, after the back surface of the substrate structure 10 is etched over the entire surface, the surface of the via structures 12 near the back surface of the substrate structure 10 is 3 micrometers to 10 micrometers higher than the surface of the via structures 11 near the back surface of the substrate structure 10.
The application sets the surface difference range of the back surfaces of the mark through hole structure 12 and the through silicon hole structure 11, ensures that the surface difference is enough, ensures that the mark through hole structure 12 can play a role in aligning the through silicon hole structure 11 and avoid influencing the through silicon hole structure 11, and simultaneously does not need to thin or etch for too long time when the difference is too large, thereby ensuring the process efficiency.
In one embodiment, the height of the via structures 12 exposed on the back surface of the substrate structure 10 after the back surface of the substrate structure 10 is etched is less than 3 microns.
The present application facilitates global planarization after subsequent metallization by providing a height to which the via structures 12 are exposed.
Next, as shown in fig. 3, step 3 is performed, in which a second dielectric layer 23 is disposed on the back surface of the substrate structure 10, and an opening structure 24 is disposed on the back surface of the substrate structure 10 at a position corresponding to the through-silicon via structure 11 to expose the first dielectric layer 14 surrounding the through-silicon via structure 11.
In one embodiment, the second dielectric layer 23 has a thickness greater than 0.5 microns.
By setting the thickness of the second dielectric layer 23, the application ensures that the first dielectric layer 14 on the back surface of the substrate structure 10 still exists after the first dielectric layer 14 on the bottom surface of the opening structure 24 is etched later, thereby playing an insulating and isolating role.
Then, as shown in fig. 4, step 4 is performed, a third dielectric layer 25 is disposed on the sidewall of the opening structure 24, and the first dielectric layer 14 wrapping the through-silicon via structure 11, which is exposed on the bottom surface of the opening structure 24, is removed.
In one embodiment, the included angle θ between the sidewall and the bottom surface of the opening structure 24 is greater than 90 degrees and less than 180 degrees.
In one embodiment, the maximum diameter of the opening structure 24 is smaller than the diameter of the through silicon via structure 11.
The application avoids the leakage phenomenon caused by the fact that the opening structure 24 contacts with the metal structure of the lower non-silicon through hole structure 11 when the opening structure 24 is arranged by arranging the relation between the maximum diameter of the opening structure 24 and the diameter of the silicon through hole structure 11.
In one embodiment, the thickness of the third dielectric layer 25 on the sidewalls of the opening structures 24 is greater than 0.2 microns.
The thickness of the third dielectric layer 25 is set so as to meet the insulation standard of the device structure.
Finally, as shown in fig. 5, step 5 is performed, in which the opening structure 24 is filled with a back metal 261, and a patterned metal 262 is formed on the surface of the second dielectric layer 23, and the patterned metal 262 and the back metal 261 are integrally formed to form a back metal wiring layer 26; the backside metal wiring layer 26 is subjected to chemical mechanical polishing to planarize the surface.
In the prior art, the back surface of the device is thinned, and then metal is exposed out of the back surface of the device through an etching process to realize back surface electric lead-out of TSVs (through silicon vias), but the exposed TSVs are inconsistent in height in the thinning and etching processes, so that the connection condition and the flatness of the wiring of the back surface metal 261 are affected, and the metal in the through silicon vias is easily ground and dispersed to other positions in the grinding and thinning process to form metal pollution. According to the scheme, the dielectric layer is arranged on the TSV exposed by back etching, then grinding and planarization are carried out, the requirement on the height uniformity of the metal column on the front side in the process is high, and the flatness of the metal 261 on the back of the TSV is difficult to realize. According to the application, the opening is arranged on the back surface of the TSV for metallization and planarization, so that the risk of metal pollution caused by direct grinding of the TSV is avoided; meanwhile, the planarization of the TSV back metal 261 is realized by using simple process steps, so that the requirement on the uniformity of the front height of the TSV is reduced; backside self-alignment of the opening arrangement is also achieved by the via structures 12, improving the accuracy of the backside metal 261 routing.
Embodiment two:
the application provides a semiconductor structure, which is obtained by adopting any one of the preparation methods in the first embodiment.
According to the application, the semiconductor structure is arranged by adopting the preparation method in the first embodiment, so that the semiconductor structure with low process cost, less structural pollution and flat TSV back metal surface can be obtained.
In summary, the semiconductor structure and the preparation method thereof can realize back self-alignment through the arrangement that the mark through hole structure is higher than the silicon through hole structure; meanwhile, the back metal and the patterned metal on the back are integrally formed and then flattened, so that the process steps for flattening the TSV back metal can be saved, and the production cost is reduced; in addition, through arranging the back metal wiring layer and then flattening, the flat and stable silicon through hole leading-out end surface with controllable process is obtained by a simple process, and the back multilayer wiring is realized.
Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method of fabricating a semiconductor structure, the method comprising:
arranging a through silicon via structure and a marked through hole structure in a substrate structure, wherein the substrate structure comprises a front surface and a back surface which are oppositely arranged, and the minimum distance from the marked through hole structure to the back surface of the substrate structure is smaller than the minimum distance from the through silicon via structure to the back surface of the substrate structure; a front metal layer structure is arranged on the front side of the substrate structure, and the front metal layer structure is in effective electrical connection with the through silicon via structure; the through silicon via structure, the marking through hole structure and the front metal layer structure are wrapped by a first dielectric layer;
bonding the front metal layer structure on a temporary substrate through a bonding layer, thinning the back surface of the substrate structure, wherein the through silicon via structure and the marking through hole structure are not exposed after thinning; etching the back surface of the substrate structure on the whole surface to expose the mark through hole structure with preset height as a counterpoint mark, wherein the silicon through hole structure is not exposed yet; a second dielectric layer is arranged on the back surface of the substrate structure, and an opening structure is arranged on the back surface of the substrate structure at a position corresponding to the through silicon via structure so as to expose the first dielectric layer wrapping the through silicon via structure;
a third dielectric layer is arranged on the side wall of the opening structure, and the first dielectric layer which is exposed on the bottom surface of the opening structure and wraps the silicon through hole structure is removed;
filling back metal in the opening structure, and forming patterned metal on the surface of the second dielectric layer at the same time, wherein the patterned metal and the back metal are integrally formed to form a back metal wiring layer; and carrying out chemical mechanical polishing on the back metal wiring layer to make the surface flat.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the via mark structure has a length L1 parallel to the substrate structure, and the via silicon structure has a length L2, L1> L2 parallel to the substrate structure.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein a ratio of L1 to L2 is greater than 1 and less than 1.2.
4. The method of claim 1, wherein after the back surface of the substrate structure is etched over the entire surface, the surface of the via mark structure adjacent to the back surface of the substrate structure is 3-10 microns higher than the surface of the via silicon structure adjacent to the back surface of the substrate structure.
5. The method of claim 1, wherein the height of the via mark structures exposed on the back surface of the substrate structure after the back surface of the substrate structure is etched is less than 3 microns.
6. The method of claim 1, wherein the second dielectric layer has a thickness greater than 0.5 microns.
7. The method of claim 1, wherein an included angle θ between a sidewall and a bottom surface of the opening structure is greater than 90 degrees and less than 180 degrees.
8. The method of manufacturing a semiconductor structure of claim 1, wherein a maximum diameter of the opening structure is smaller than a diameter of the through silicon via structure.
9. The method of claim 1, wherein the thickness of the third dielectric layer on the sidewalls of the opening structure is greater than 0.2 microns.
10. A semiconductor structure obtained by the method of any one of claims 1 to 9.
CN202311126040.6A 2023-09-01 2023-09-01 Semiconductor structure and preparation method thereof Pending CN117153777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311126040.6A CN117153777A (en) 2023-09-01 2023-09-01 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311126040.6A CN117153777A (en) 2023-09-01 2023-09-01 Semiconductor structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN117153777A true CN117153777A (en) 2023-12-01

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