CN113594117B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113594117B CN113594117B CN202110859263.8A CN202110859263A CN113594117B CN 113594117 B CN113594117 B CN 113594117B CN 202110859263 A CN202110859263 A CN 202110859263A CN 113594117 B CN113594117 B CN 113594117B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title description 58
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 230000000149 penetrating effect Effects 0.000 claims abstract description 7
- 238000009826 distribution Methods 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 15
- 238000013461 design Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 238000005530 etching Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a first semiconductor substrate on which at least one functional device is formed; and a second semiconductor substrate opposite to the first semiconductor substrate. The second semiconductor substrate includes: a plurality of main chip regions, each main chip region being provided with at least one connection via, each of the at least one connection via penetrating through the second semiconductor substrate for electrical connection with one or more of the at least one functional device, and a scribe line region between the plurality of main chip regions. The dicing street area is provided with: an additional pattern, and a plurality of additional vias, at least one of the plurality of additional vias being located between the additional pattern and at least one of the plurality of main chip regions adjacent to the additional pattern.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing the same.
Background
With the rapid development of integrated circuits, the latter molar age gradually approaches, and the integration level cannot be increased by simply reducing the line width size. Integrated circuit applications diversify, and emerging fields such as smart phones, internet of things, automotive electronics, high performance computing, 5G, artificial intelligence, etc. also put forward higher demands on integrated circuit chips. And the silicon interposer technology based on Through Silicon Vias (TSVs) can provide homogeneous and heterogeneous integration, so that the inter-chip interconnection of high-end chips and the high-speed interconnection of electrical signals among multiple layers are realized. The silicon interposer technology based on the silicon through holes provides a solution for silicon-based 2.5D/3D system level packaging, and realizes more functions, smaller size and higher speed.
Disclosure of Invention
According to some embodiments of the present disclosure, there is provided a semiconductor device including: a first semiconductor substrate on which at least one functional device is formed; and a second semiconductor substrate opposite to the first semiconductor substrate, the second semiconductor substrate including: a plurality of main chip regions, each main chip region being provided with at least one connection via penetrating the second semiconductor substrate for electrical connection with the at least one functional device; and a dicing street region located between the plurality of main chip regions, the dicing street region being provided with: attaching a graph; and a plurality of additional through holes, at least one of the plurality of additional through holes being located between the additional pattern and at least one of the plurality of main chip regions adjacent to the additional pattern.
According to some embodiments of the present disclosure, there is also provided a method of manufacturing a semiconductor device, including: providing a first semiconductor substrate on which at least one functional device is formed; providing a second semiconductor substrate, the second semiconductor substrate comprising: a plurality of main chip regions, each main chip region being provided with at least one connection via, each of the at least one connection via penetrating through the second semiconductor substrate; and a dicing street region located between the plurality of main chip regions, the dicing street region being provided with: an additional pattern, and a plurality of additional vias, at least one of the plurality of additional vias being located between the additional pattern and at least one of the plurality of main chip regions adjacent to the additional pattern; and bonding the first semiconductor substrate with the second semiconductor substrate such that the first semiconductor substrate is opposite the second semiconductor substrate, wherein each of the at least one connection via is electrically connected with one or more of the at least one functional device.
These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.
Drawings
Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:
fig. 1A is a schematic cross-sectional structure of a semiconductor device in the related art;
FIG. 1B is a schematic plan view of a semiconductor substrate of the semiconductor device of FIG. 1A;
FIG. 1C is a schematic view of one main chip region and scribe line region in the semiconductor substrate of FIG. 1B;
fig. 2A is a schematic cross-sectional structure of a semiconductor device according to some embodiments of the present disclosure;
2B-2D are schematic diagrams of a main chip region and a scribe line region, respectively, of a second semiconductor substrate in the semiconductor device of FIG. 2A, according to some embodiments of the present disclosure;
FIG. 2E is a schematic diagram of the distribution of additional vias in the scribe line region of FIG. 2D according to some embodiments of the present disclosure;
FIG. 3A is a schematic illustration of additional patterns and additional vias in the scribe line region of FIGS. 2B-2D according to some embodiments of the present disclosure;
FIG. 3B is a schematic illustration of additional patterns and additional vias in the scribe line region of FIGS. 2B-2D according to some embodiments of the present disclosure; and
Fig. 4 is a schematic flow chart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.
Detailed Description
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under …," "under …," "lower," "under …," "over …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary terms "below …" and "below …" may encompass both orientations above … and below …. Terms such as "before …" or "before …" and "after …" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B.
It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, in no event "on …" or "directly on …" should be construed as requiring one layer to completely cover an underlying layer.
Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such an interchange would cause a conflict. It should be understood that the term "film" includes layers and should not be construed to indicate vertical or horizontal thickness unless otherwise indicated. It should be noted that the thicknesses of the material layers of the semiconductor device shown in the drawings are only schematic and do not represent actual thicknesses.
In the process of manufacturing through silicon vias, the process steps such as photolithography process, etching process and the like are generally required. Since additional patterns of non-through-silicon via structures are required to be added on the mask of the through-silicon via in the photolithography process, the additional patterns are usually located in a different dicing street area from the main chip area where the through-silicon via is located, and the patterns accompanying the through-silicon via are transferred into the semiconductor substrate sequentially through the photolithography process and the etching process.
The inventors have found that, due to the difference in the dimensions of the additional pattern and the through-silicon via, the etching depth of the additional pattern is different from that of the through-silicon via during etching, resulting in a difference in stress around the additional pattern and that around the through-silicon via after the etching process. The difference between the stress around the additional pattern and the stress around the through-silicon via is liable to cause cracks at the additional pattern during or after the formation of the through-silicon via penetrating the semiconductor substrate through the outcrop process of the through-silicon via.
Fig. 1A is a schematic cross-sectional structure of a semiconductor device 100 in the related art; fig. 1B is a schematic plan view of the semiconductor substrate 110 in the semiconductor device 100 of fig. 1A; fig. 1C is a schematic view of one main chip region 110a and a scribe line region 110b adjacent to the main chip region 110a in the semiconductor substrate 110 in fig. 1A.
The structure of the semiconductor device 100 is described below with reference to fig. 1A to 1C.
As shown in fig. 1A and 1B, the semiconductor device 100 includes a semiconductor substrate 110, and the semiconductor substrate 110 includes a plurality of main chip regions 110a and scribe line regions 110B located between the main chip regions 110a (the broken line in fig. 1A shows the boundary between the main chip regions 110a and the scribe line regions 110B). As shown in fig. 1A, each main chip region is provided with a plurality of connection through holes 111, and the connection through holes 111 penetrate through the semiconductor substrate 110 for electrical connection with devices on other semiconductor substrates, forming a three-dimensional integrated semiconductor device.
As shown in fig. 1A and 1C, the scribe line region 110b is provided with an additional pattern 112 for providing a positional reference in the related process of forming the connection via 121 in the second semiconductor substrate 110 to align the second semiconductor substrate 110. The additional graphic 112 may be arranged in various distribution patterns, such as two different distribution patterns as shown in FIG. 1C. Referring to fig. 1A, the pattern density of the additional pattern 112 is significantly smaller than that of the connection via 111 located in the main chip region 110 a. Meanwhile, the pattern size of the additional pattern 112 is smaller than the size of the connection via 111. In some examples, the additional pattern 112 is composed of a rectangular block pattern with a surface of 2 μm×19 μm, and the connection via 111 is a vertical hole with a diameter of 10 μm-30 μm. Since the pattern size of the additional pattern is smaller than the size of the connection via hole, the pattern depth of the additional pattern is smaller than the pattern depth of the connection via hole after the etching process, resulting in a difference in stress around the additional pattern and stress around the connection via hole. In other examples, the pattern size of the additional pattern 112 may be larger than the size of the connection via 111, which also results in a difference in stress around the additional pattern 112 and the connection via 111 after the etching process. The connection via 111 penetrating the semiconductor substrate 110 needs to be formed through a deposition process, an outcrop process, etc. after the etching process. Since there is a difference in stress around the additional pattern 112 and stress around the connection via 111, stress concentration tends to occur at the additional pattern 112 during or after the outcrop process, thereby generating a crack at the additional pattern 112, which affects the reliability and yield of the connection via 111 in the main chip region 110a when the crack extends to the main chip region 110 a.
Embodiments of the present disclosure provide a semiconductor device that improves the pattern density of scribe line regions and improves the stress distribution around the pattern of scribe line regions. Therefore, the difference between the stress around the scribe line region pattern and the stress around the main chip region pattern is reduced, thereby reducing the probability of stress concentration at the additional pattern of the scribe line region during or after the outcrop process, and thus reducing the probability of crack generation at the additional pattern. Meanwhile, when the additional pattern of the scribe line region generates a crack, the crack can be prevented from extending to the main chip region, thereby improving the reliability and yield of the semiconductor device.
It should be noted that the term "additional pattern" according to the present disclosure refers to any pattern disposed in a scribe line region different from the main chip region, including, for example, but not limited to, alignment marks, overlay marks, patterns for performing electrical tests, and the like.
Fig. 2A is a schematic cross-sectional structure of a semiconductor device 200 according to some embodiments of the present disclosure; fig. 2B-2D are schematic diagrams of a main chip region 210a and a scribe line region 210B, respectively, of the second semiconductor substrate 210 in the semiconductor device 200 of fig. 2A, according to some embodiments of the present disclosure; FIG. 2E is a schematic diagram of the distribution of additional vias 233 in scribe line region 210b of FIG. 2D according to some embodiments of the present disclosure; FIG. 3A is a schematic illustration of additional patterns 222a and additional vias 223 in scribe line region 210B of FIGS. 2B-2D according to some embodiments of the present disclosure; and fig. 3B is a schematic illustration of additional patterns 222B and additional vias 223 in scribe line region 210B in fig. 2B-2D according to some embodiments of the present disclosure.
The structure of the semiconductor device 200 according to one embodiment is described below with reference to fig. 2A-2E, 3A, and 3B.
The semiconductor device 200 includes a first semiconductor substrate 210 and a second semiconductor substrate 220.
The first semiconductor substrate 210 may be any type of semiconductor substrate including a semiconductor-on-insulator substrate, and the like.
At least one functional device 211 is formed in the first semiconductor substrate 210. The functional device 211 may be any device including a source, a drain, and a gate. An integrated circuit may be formed by combining one or more of the functional devices 211. For example, the functional device 211 may be a CMOS transistor, a finfet, etc., without limitation.
According to some embodiments, interconnect structures are formed to electrically connect the source, drain, and gate electrodes in functional device 211 to external circuitry. As shown in fig. 2A, the interconnect structure includes a dielectric layer 212 formed on the surface of the first semiconductor substrate 210, and a contact hole 213 and a re-wiring layer 214 formed in the dielectric layer 212. In some embodiments, the material of dielectric layer 212 includes, but is not limited to, silicon oxide, silicon nitride, and the like. The contact hole 213 in the dielectric layer 212 and the re-wiring layer 214 may be made of the same conductive material, such as copper or aluminum, without limitation.
The second semiconductor substrate 220 may be any type of semiconductor substrate including, but not limited to, a silicon substrate, a silicon nitride substrate, and the like.
The second semiconductor substrate 220 is opposite to the first semiconductor substrate 210, and the second semiconductor substrate 220 includes a main chip region 220a and a scribe line region 220b.
A connection via 221 is provided in the main chip region 220a for electrically connecting the functional device 211 on the first semiconductor substrate 210 to an external circuit. In some embodiments, the via 221 in the second semiconductor substrate 200 is electrically connected to an interconnect structure on the first semiconductor substrate 210, thereby electrically connecting the functional device 211 in the first semiconductor substrate 210 to an external circuit. According to some embodiments, the connecting via 221 has a diameter in the range of 10 μm-30 μm. According to some embodiments, a plurality of diameter connection vias 221, for example, a connection via having a diameter of 10 μm and a connection via having a diameter of 20 μm, are simultaneously provided in the first semiconductor substrate 210. The connection via 221 formed after the outcrop process penetrates the second semiconductor substrate 220. According to some embodiments, the depth of the connection via 221 may be 100 μm to 200 μm according to the thickness of the second semiconductor substrate 220.
The scribe line region 220b is provided with an additional pattern 222 for providing a positional reference in the related process of forming the connection via 221 in the second semiconductor substrate 220 to align the second semiconductor substrate 220. Since the additional pattern 222 is different in size from the connection via 221, after the etching process, the etching depth of the additional pattern 222 is different from that of the connection via 221, resulting in a difference in stress around the additional pattern 222 and that around the connection via 221. The difference between the stress around the additional pattern 222 and the stress around the connection via 221 tends to cause cracks at the additional pattern 222 during or after the outcrop process.
To help avoid cracking at the additional pattern 222 during or after the outcrop process of the connection via 221, in an embodiment according to the present disclosure, as shown in fig. 2A, a plurality of additional vias 223 are further provided in the scribe line region 220b, at least one additional via 223 of the plurality of additional vias 223 being located between the additional pattern 222 and the main chip region 220 a.
The provision of the additional via 223 improves the pattern distribution density in the scribe line region 220b, thereby improving the stress distribution around the additional pattern 222 in the scribe line region 220b after the etching process. This helps to alleviate the difference between the stress around the additional pattern 222 in the scribe line region 220b and the stress around the connection via 221 in the main chip region 220a, thereby reducing the probability of stress concentration at the additional pattern 222 during or after the outcrop process, and thus reducing the probability of crack generation.
Further, at least one additional via 223 is disposed to be located between the additional pattern 222 and the main chip region 220 a. The additional through holes 223 may have a circular hole shape, which has a uniform stress distribution on the circumference and a small possibility of stress concentration. Even if a crack is generated at the additional pattern 222, after the crack extends to the additional through hole 223, since the additional through hole 223 is less likely to be concentrated in stress, the probability that the crack further extends through the additional through hole 223 is reduced, thereby having an effect of preventing the crack from extending.
According to some embodiments, the additional via 223 has the same dimensions as the connection via 221. In some embodiments, the diameter of the additional via 223 ranges from 10 μm to 30 μm. According to some embodiments, additional through holes 223 of various diameters, for example, additional through holes of 10 μm diameter and additional through holes of 20 μm diameter, are simultaneously provided in the scribe line region 220 b. According to some embodiments, the additional via 223 penetrates the second semiconductor substrate 220 after the outcrop process, as with the connection via 221. According to some embodiments, the thickness of the second semiconductor substrate 220, as well as the connection via 221, the depth of the additional via 223 may be 100 μm-200 μm. The size of the additional via 223 is set to be the same as the size of the connection via 221, so that the design of the additional via 223 and the design of the connection via 221 may be made to use the same design rule (e.g., use the same minimum design rule definition value), and the manufacturing process of the additional via 223 is simplified.
It is to be understood that the above-described setting of the size of the additional through hole 223 to be the same as the size of the connection through hole 221 is merely exemplary. Those skilled in the art will appreciate that additional through holes of other sizes may be provided to achieve the technical effects of the present disclosure.
According to some embodiments, as shown in fig. 2A, each of the plurality of additional vias 223 and the additional pattern 222 is filled with a material 224 that is the same as a material filled in one or more of the plurality of connection vias 221. In the subsequent process of exposing the connection via 221 (e.g., thinning process or grinding process), since the additional via 223 and the additional pattern 222 in the scribe line region 220b are filled with the same material 224 as the connection via 221 in the main chip region 220a, the removal rate of the material in the scribe line region 220b and the main chip region 220a is the same in the process of exposing the connection via 221. The difference of external pressure or internal stress caused by the difference of the removal rate of the filling material in the dicing street area 220b and the main chip area 220a is avoided, thereby reducing the occurrence probability of stress concentration and reducing the occurrence probability of cracks.
Meanwhile, since the additional through holes 223 in the scribe line region 220b and the additional patterns 222 are filled with the same material 224 as the connection through holes 221 in the main chip region, the difference in stress around the patterns in the scribe line region 220b and the main chip region 220a is only due to the difference in pattern shape, pattern size and pattern distribution density, avoiding further difference in stress due to the difference in filling material. This may reduce the difference in stress around the pattern of scribe line region 220b and the stress around the pattern of main chip region 220a, improving stress distribution. Further, this also allows the fabrication process of the additional via 223 and the additional pattern 222 to be incorporated into the fabrication process of the connection via 221 of the main chip region, making the fabrication process simple.
According to some embodiments, the filled material 224 includes, but is not limited to, a metallic material such as copper, aluminum, and the like. In some embodiments, the filled material 224 includes multiple layers of material, such as silicon oxide, silicon nitride, copper, etc., that are sequentially stacked from the sidewall to the center of the connection via 221, formed through multiple deposition processes.
According to some embodiments, the plurality of additional through holes 223 are distributed in the scribe line region 220b to form a first distribution pattern at the surface of the scribe line region 220b, at least a portion of which is located between the additional pattern 222 and the at least one main chip region 220 a. This provides an additional through hole 223 between each point in the additional pattern 222 where stress concentration may occur to cause crack generation and the main chip region 220a, further increasing the likelihood that the additional through hole 223 prevents crack generated in the scribe line region 220b from extending to the main chip region 220 a.
As shown in fig. 2B, in some embodiments according to the present disclosure, the first distribution pattern of the plurality of additional via holes 223 formed in the scribe line region 220B includes a sub-pattern 223a and a sub-pattern 223B. Wherein the sub-pattern 223a is located between the additional pattern 222a and the main chip region 220 a; the sub-pattern 223b is located between the additional pattern 222b and the main chip region 220a. According to some embodiments, the additional feature 222a is an overlay mark and the additional feature 222b is an alignment mark.
As shown in fig. 2C, in some embodiments according to the present disclosure, the plurality of additional vias 223 form a first distribution pattern in the scribe line region 220b including a ring-shaped sub-pattern 223C, the sub-pattern 223C surrounding the main chip region 220a. Thus, two portions of the sub-pattern 223c are located between the additional pattern 222a and the main chip region 220a and between the additional pattern 222b and the main chip region 220a, respectively.
As shown in fig. 2D, in some embodiments according to the present disclosure, the first distribution pattern formed by the plurality of additional via holes 223 in the scribe line region 220b includes a ring-shaped sub-pattern 223D and a sub-pattern 223e, the sub-pattern 223D surrounding the additional pattern 222a, and the sub-pattern 223e surrounding the additional pattern 222b. Thus, a portion of the sub-pattern 223d (e.g., the portion in the dashed box C) is located between the additional pattern 222a and the main chip region 220a, and a portion of the sub-pattern 223e is located between the additional pattern 222b and the main chip region 220a.
It is to be understood that the arrangements shown in fig. 2B, 2C and 2D are merely exemplary. It will be appreciated by those skilled in the art that any other shape of sub-pattern may be provided such that the sub-pattern partially or fully encloses the main chip area and/or the additional pattern, all of which may achieve the technical effects of the present disclosure.
The distribution of the plurality of additional via holes 223 constituting the sub-pattern is further described with reference to fig. 2E. Fig. 2E is a schematic distribution diagram of a plurality of additional vias of a portion in a dashed box C of the sub-pattern 223D in fig. 2D. According to some embodiments, as shown in fig. 2E, the plurality of additional through holes 223 between the additional pattern 222a and at least one main chip region 220a adjacent to the additional pattern 222a includes: a first subset of additional vias 223A distributed along a first trajectory (indicated by arrow a); and a second subset of additional vias 223B distributed along a second trajectory (indicated by arrow B), the first trajectory being parallel to the second trajectory.
In the example of fig. 2E, when a crack is generated at the additional pattern 222a and extends to an additional via 223 adjacent to the additional pattern 222a (i.e., an additional via 223 in a first additional subset of vias 223A distributed along the first trajectory a), and the additional via 223 adjacent to the additional pattern 222a fails to prevent the crack from extending, an additional via 223 in a second additional subset of vias 223B distributed along the second trajectory B can prevent the crack from extending further, thereby further reducing the probability of the crack extending to the main chip region 220 a.
According to some embodiments, as shown in fig. 2E, the additional vias 223 in the first additional subset of vias 223A are staggered with respect to the additional vias 223 in the second additional subset of vias 223B. This causes the area between two adjacent additional vias 223 in the first additional via subset 223A to be opposite to a corresponding one of the additional vias 223 in the second additional via subset 223B. When a crack extends from the region between the two additional vias 223 in the first additional via subset 223A, the corresponding additional via 223 in the second additional via subset 223B can prevent it from extending, raising the chance that the additional via 223 prevents the crack from extending.
It is to be understood that the arrangement in fig. 2E is merely exemplary. It will be appreciated by those skilled in the art that the additional vias 223 of the first distribution pattern may also include a third subset of additional vias distributed along a third track parallel and adjacent to the second track, a fourth subset of additional vias distributed along a fourth track parallel and adjacent to the third track, or other subsets of additional vias distributed along other tracks, etc., without limitation.
In some embodiments, as shown in fig. 2E, an angle θ between the opening center of any one of the first additional via subset 223A and a line connecting respective opening centers of two additional vias 223 adjacent to the additional via 223 in the second additional via subset 223B is 60 °.
According to some embodiments, the additional pattern includes a plurality of block patterns arranged to form a second distribution pattern on the surface of the scribe line region. In some embodiments, the distribution of the additional through holes in the scribe line region is set according to a second distribution pattern of the additional pattern formed on the surface of the scribe line region, so as to improve the effect of the additional through holes on improving the pattern distribution density in the scribe line region and prevent the probability of crack propagation.
An exemplary distribution of additional vias in the scribe line region is described below with reference to fig. 3A and 3B. Wherein the additional patterns shown in fig. 3A and 3B correspond to the additional pattern 222a and the additional pattern 222B in fig. 2C, respectively, and the additional through holes 223C and 223I may be collectively referred to as an additional through hole 223.
As shown in fig. 3A and 3B, the additional pattern 222A and the additional pattern 222B each include four block patterns 222A each having a rectangular surface distribution shape. The second division patterns 222X (fig. 3A) and the second division patterns 222Y (fig. 3B) are formed by the arrangement of the block patterns 222A.
It should be understood that the arrangement shown in fig. 3A and 3B is merely exemplary. It will be appreciated by those skilled in the art that the surface distribution of the block pattern in the scribe line region may be any polygonal shape such as triangle, square, pentagon, etc.
According to some embodiments, the plurality of block patterns 222A in the additional pattern 222A are sequentially arranged along each side of the polygon to form the second division pattern 222X, and the plurality of additional via holes 223 further include at least one additional via hole 223I located inside the second division pattern 222X. Illustratively, as shown in fig. 3A, four block patterns 222A of the additional patterns 222A are sequentially arranged along each side of the quadrangle to form a second division pattern 222X. It is to be understood that the arrangement in fig. 3A is merely exemplary. It should be understood by those skilled in the art that the block pattern 222A may be arranged along any polygon such as a triangle, a quadrangle, a pentagon, etc. to form the second division pattern 222X, which is not limited herein.
In some embodiments, at least one additional via 223I is disposed inside the second division pattern 222X, such that when the additional pattern 222a generates a crack and extends inside the second division pattern 222X, the additional via 223I located inside the second division pattern 222X can further prevent the crack from extending, avoiding the crack from finally extending to the main chip region 220a. Meanwhile, the additional through holes 223I are provided inside the second division pattern 222X such that the additional through holes 223 are distributed not only in the region between the additional pattern 222a and the main chip region 220a, but also in the region inside the second division pattern 222X formed by the additional pattern 222 a. By expanding the distribution range of the additional via holes 223, the additional via holes 223 can improve the distribution density of the patterns of the region inside the second division pattern 222X formed by the additional patterns 222a, thereby improving the stress distribution around the patterns of the region inside the second division pattern 222X, and further reducing the probability of occurrence of stress concentration.
According to some embodiments, as shown in fig. 3A and 3B, four block patterns 222A of the additional patterns 222A form a second division pattern 222X on the surface of the scribe line region, and four block patterns 222A of the additional patterns 222B form a second division pattern 222Y on the surface of the scribe line region. Wherein the second division pattern 222X includes a plurality of corners 301, 302, 303, … …, 308 protruding outward from the center thereof, and the second division pattern 222Y includes a plurality of corners 309, 310, 311, 312 protruding outward from the center thereof. The additional through holes 223 further include corresponding first additional through holes 223C opposite each of the corners protruding outward in the second division patterns 222X and 222Y.
The corners of the second distribution pattern 222X or the second distribution pattern 222Y protruding outward correspond to corners of the block pattern 222A in the additional pattern 222A or the additional pattern 222b, and there is a high probability that stress concentration occurs at the corners of the block pattern 222A. Therefore, the probability that the crack extends outward from the corner of the block pattern 222A of the additional pattern 222A or the additional pattern 222b is also large. When a crack is generated at a corner of the block pattern 222A of the additional pattern 222A or 222b and extends outward, the first additional through hole 223C can prevent the crack at the corresponding corner from extending. In this way, the probability that the additional through hole 223 prevents crack propagation can be further improved.
According to some embodiments, a line connecting a center of the opening area of each first additional via 223C at the surface of the scribe line area and a vertex of the corresponding angle is an angular bisector of the corresponding angle. With continued reference to fig. 3A, the opening of the first additional via 223C opposite the outwardly protruding corner 301 in the second division pattern 222X is located on the angular bisector of the corner 301, with the line connecting the vertex of the corner 301. That is, if the angle 301 is a right angle, the angle α between the line and the extension lines of both sides of the angle 301 is 45 °. Thus, when the opposite corner cracks, the probability that crack propagation encounters the first additional through hole 223C is raised, and the probability that crack propagation is prevented by the additional through hole 223 is further raised.
According to some embodiments, a pitch of each first additional via 223C between an opening area of the surface of the scribe line area 220b and a vertex of the corresponding corner is greater than or equal to a minimum design rule definition value. As shown in fig. 3A, a distance D between the first additional via 223C of the corner 301 corresponding to the second division pattern 222X and the vertex of the corner 301 is equal to or larger than the minimum design rule definition value. The minimum design rule definition value is a safe distance between patterns defined according to process conditions, default configuration conditions, and the like when layout design is performed. At the minimum setting rule definition value, no connection or short circuit or the like occurs between the figures.
According to some embodiments, as shown in fig. 2A-2D, a pitch between any two additional vias 223 of the plurality of additional vias 223, a pitch between any one additional via 223 of the plurality of additional vias 223 and the additional pattern 222, and a pitch between any one additional via 223 of the plurality of additional vias 223 and any one main chip region 220a of the plurality of main chip regions 220a in the second semiconductor substrate 220 are all greater than or equal to a minimum design rule definition value.
Embodiments of the present disclosure also provide a method of manufacturing a semiconductor device.
Fig. 4 illustrates a schematic flow chart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.
One implementation of a method 400 of fabricating a semiconductor device is described below with reference to fig. 4 and 2A.
In step 410, a first semiconductor substrate 210 is provided on which at least one functional device 211 is formed.
The first semiconductor substrate 210 may be any type of semiconductor substrate including a semiconductor-on-insulator substrate, and the like.
At least one functional device 211 is formed on the first semiconductor substrate 210, and the functional device 211 may be any device including a source, a drain, and a gate. An integrated circuit may be formed by combining one or more of the functional devices 211. For example, the functional device 211 may be a CMOS transistor, a finfet, etc., without limitation. According to some embodiments, the process of forming the at least one functional device 211 on the first semiconductor substrate 210 includes, but is not limited to, an ion implantation process, a photolithography process, an etching process, a deposition process, a grinding process, and the like.
According to some embodiments, an interconnect structure is also formed after forming at least one functional device 211 on the first semiconductor substrate 210, the interconnect structure being used to electrically connect the functional device 211 to an external circuit. As shown in fig. 2A, the interconnect structure includes a dielectric layer 212 formed on the surface of the first semiconductor substrate 210, and a contact hole 213 and a re-wiring layer 214 formed in the dielectric layer 212. In some embodiments, the material of dielectric layer 212 includes, but is not limited to, silicon oxide, silicon nitride, and the like. The contact hole 213 in the dielectric layer 212 and the re-wiring layer 214 may be made of the same conductive material, such as copper or aluminum, without limitation. According to some embodiments, the process of forming the interconnect structure includes, but is not limited to, a photolithography process, an etching process, a deposition process, a grinding process, and the like.
In step 420, a second semiconductor substrate 220 is provided.
The second semiconductor substrate 220 includes a plurality of main chip regions 220a and scribe line regions 220b between the plurality of main chip regions 220 a. Each of the main chip regions 220a is provided with at least one connection via 221, and each connection via 221 of the at least one connection via 221 penetrates the second semiconductor substrate 220. The scribe line region 220b is provided with an additional pattern 222 and a plurality of additional through holes 223. At least one additional via of the plurality of additional vias 223 is located between the additional pattern 222 and at least one main chip region 220a adjacent to the additional pattern 222 of the plurality of main chip regions 220 a.
According to some embodiments, the process of forming the connection via 221, the additional pattern 222, and the additional via 223 in the second semiconductor substrate 220 includes, but is not limited to, a photolithography process, an etching process, a thinning process, a grinding process, and the like. After the photolithography process, the etching process, the thinning process, the polishing process, and the like described above, the connection via 221 completes the exposure process and penetrates the second semiconductor substrate 220.
The provision of the additional via 223 improves the pattern distribution density in the scribe line region 220b, thereby improving the stress distribution around the additional pattern 222 in the scribe line region 220b after the etching process. This helps to alleviate the difference between the stress around the additional pattern 222 in the scribe line region 220b and the stress around the connection via 221 in the main chip region 220a, thereby reducing the probability of stress concentration at the additional pattern 222 during or after the outcrop process, and thus reducing the probability of crack generation.
Further, at least one additional via 223 is disposed to be located between the additional pattern 222 and the main chip region 220 a. The additional through holes 223 may have a circular hole shape, which has a uniform stress distribution on the circumference and a small possibility of stress concentration. Even if a crack is generated at the additional pattern 222, after the crack is extended to the additional through hole 223, since the additional through hole 223 is less likely to be concentrated in stress, the probability that the crack is further extended through the additional through hole 223 is reduced, thereby having an effect of preventing the crack from being extended.
The arrangement of the plurality of additional through holes 223 in the scribe line region 220B may be as described above with reference to fig. 2A-2E and fig. 3A-3B, and will not be repeated here.
In step 430, the first semiconductor substrate 210 is bonded to the second semiconductor substrate 220 such that the first semiconductor substrate 210 is opposite to the second semiconductor substrate 220. Each of the at least one connection via 221 is electrically connected to one or more of the at least one functional device 211.
According to some embodiments, the method of bonding the first semiconductor substrate 210 to the second semiconductor substrate 220 includes, but is not limited to, a bonding process or the like.
According to the manufacturing method of the semiconductor device, the manufactured semiconductor device improves the pattern density of the cutting channel region and improves the stress distribution around the pattern of the cutting channel region. Therefore, the stress distribution difference between the scribe line region and the main chip region is reduced, and the probability of crack generation of the additional pattern of the scribe line region is reduced. Meanwhile, when the additional pattern of the scribe line region generates cracks due to stress concentration, it is possible to prevent the cracks from extending to the main chip region. Therefore, the manufactured semiconductor device has improved yield and reliability.
While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed and the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims (14)
1. A semiconductor device, comprising:
a first semiconductor substrate on which at least one functional device is formed; and
a second semiconductor substrate opposite to the first semiconductor substrate, the second semiconductor substrate comprising:
a plurality of main chip regions, each main chip region being provided with at least one connection via, each of the at least one connection via penetrating through the second semiconductor substrate for electrical connection with one or more of the at least one functional device; and
A scribe line region located between the plurality of main chip regions, the scribe line region being provided with:
attaching a graph; and
a plurality of additional vias, at least one of the plurality of additional vias being located between the additional pattern and at least one of the plurality of main chip regions adjacent to the additional pattern,
wherein the plurality of additional through holes are distributed in the scribe line region to form a first distribution pattern on a surface of the scribe line region, and the first distribution pattern includes a sub-pattern entirely surrounding the additional pattern.
2. The semiconductor device of claim 1, wherein at least a portion of the first distribution pattern is located between the additional pattern and the at least one main chip region.
3. The semiconductor device of claim 2, wherein the first distribution pattern comprises at least one sub-pattern, each sub-pattern at least partially surrounding a corresponding one of the at least one main chip region.
4. The semiconductor device of claim 2, wherein an additional via of the plurality of additional vias corresponding to the at least a portion of the first distribution pattern comprises:
A first subset of additional vias distributed along the first trajectory; and
a second subset of additional vias distributed along a second trajectory, the second trajectory being parallel to the first trajectory.
5. The semiconductor device of claim 4, wherein additional vias in the first additional subset of vias are staggered with respect to additional vias in the second additional subset of vias.
6. The semiconductor device of claim 5, wherein an angle between an opening center of any one of the first additional via subset and a line connecting respective opening centers of two additional vias of the second additional via subset adjacent to the additional via is 60 degrees.
7. The semiconductor device of claim 1, wherein the additional pattern comprises a plurality of block patterns arranged to form a second distribution pattern on a surface of the scribe line region.
8. The semiconductor device of claim 7, wherein the second distribution pattern includes a plurality of corners protruding outward from a center of the second distribution pattern, and wherein the plurality of additional vias includes a plurality of first additional vias, each first additional via opposing a corresponding one of the plurality of corners at an opening region of a surface of the scribe line region.
9. The semiconductor device according to claim 8, wherein a line connecting a center of an opening region of each first additional via at a surface of the scribe line region and a vertex of the corresponding corner is an angular bisector of the corresponding corner.
10. The semiconductor device of claim 8, wherein a pitch of each first additional via between an opening area of a surface of the scribe line area and a vertex of the corresponding corner is greater than or equal to a minimum design rule definition value.
11. The semiconductor device of claim 7, wherein the plurality of block patterns are sequentially arranged along sides of a polygon to form the second division pattern, and wherein the plurality of additional vias further comprise at least one additional via located inside the second division pattern.
12. The semiconductor device according to any one of claims 1 to 11, wherein a pitch between any two of the plurality of additional vias, a pitch between any one of the plurality of additional vias and the additional pattern, and a pitch between any one of the plurality of additional vias and any one of the plurality of main chip regions are each greater than or equal to a minimum design rule definition value.
13. The semiconductor device according to any one of claims 1 to 11, wherein each of the plurality of additional vias and the additional pattern is filled with a material identical to a material filled in one or more of the plurality of connection vias.
14. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor substrate on which at least one functional device is formed;
providing a second semiconductor substrate, the second semiconductor substrate comprising:
a plurality of main chip regions, each main chip region being provided with at least one connection via, each of the at least one connection via penetrating through the second semiconductor substrate; and
a scribe line region located between the plurality of main chip regions, the scribe line region being provided with:
attaching a graph; and
a plurality of additional vias, at least one of the plurality of additional vias being located between the additional pattern and at least one of the plurality of main chip regions adjacent to the additional pattern,
wherein the plurality of additional through holes are distributed in the scribe line region to form a first distribution pattern on a surface of the scribe line region, and the first distribution pattern includes a sub-pattern entirely surrounding the additional pattern; and
And bonding the first semiconductor substrate with the second semiconductor substrate such that the first semiconductor substrate is opposite the second semiconductor substrate, wherein each of the at least one connection via is electrically connected with one or more of the at least one functional device.
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