JP2012151230A - Protection element and semiconductor device having protection element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protection element that can be formed in a relatively small area and can be operated as a protection element even if miniaturization of the element size is advanced.SOLUTION: A protection element includes: a first-conductivity-type well region 3 formed in a semiconductor substrate 1; a second-conductivity-type well region 4 formed adjacent to the first-conductivity-type well region 3; a MOS transistor of a second-conductivity-type channel formed in the first-conductivity-type well region 3; first wiring electrically connected to the first-conductivity-type well region 3, a source region of the MOS transistor, and a gate of the MOS transistor; and second wiring electrically connected to a drain region of the MOS transistor and the second-conductivity-type well region 4.

Description

  The present invention relates to a protection element for measures against ESD and the like, and a semiconductor device provided with this protection element.

As a protection element against ESD (Electro Static Discharge), a GGMOS (Gate Grounded MOSFET) structure is widely used.
When this GGMOS structure is employed, the chip area can be reduced by combining the output driver function and the protection element function.

The protection element using GGMOS receives an ESD surge current by utilizing a parasitic bipolar operation between the drain, channel and source of the MOSFET and protects the internal circuit.
The operating principle of this protective element is that the channel substrate potential is raised by the ESD surge current, and when the trigger potential Vt1 is exceeded, a bipolar current begins to flow between the source, the channel and the drain. After the holding voltage Vh, a surge current flows through the open bipolar path.

The MOSFET has a reduced ESD withstand voltage due to scaling and a reduction in gate length due to scaling, and the withstand voltage BVox of the gate insulating film is significantly reduced.
On the other hand, the trigger potential Vt1 that enters the operating point where the GGMOS acts as a protective element and flows a surge current has a gradual decrease tendency even after scaling, and therefore reverses to BVox <Vt1 after the 90 nm generation. Since Vt1 becomes relatively high, it becomes difficult to operate as a protection element depending on the surge potential.

Due to such problems, it has become difficult to use GGMOS as a protection element after the 90 nm generation, and it is a problem that BVox <Vt1 and the ESD design window cannot be entered (FIG. 1 of Non-Patent Document 1). 1, see FIG. 2).
One reason for the gradual decrease in Vt1 even when the MOSFET is scaled is that, since the channel substrate concentration generally increases with scaling, the potential increase due to the substrate current cannot be expected due to the low resistance of the channel. It is done.

As a defect example of the 65 nm generation, it has been reported that the breakdown of the gate insulating film occurs when Vt1> BVox of the protective element (see Non-Patent Document 2).
Further, as a configuration of a protection element other than GGMOS, a DTSCR (Diode Triggered Silicon Control Rectifier) that can set Vt1 low has been reported (see Non-Patent Document 1).

  Therefore, in the generation of 90 nm or less, an RC circuit or a diode-type protection element is provided instead of the protection element having the GGMOS structure.

Mergens. Et al, IEEE Transactions on Devices and Materials Reliability, Vol.5 No.3, Sep, pp.532-542,2005 Guido Notermans, “Gate Oxide Protection and ggNMOSTs in 65nm”, 30th EOS / ESD symposium, proceeding, 2008

The RC circuit and the diode-type protection element require a relatively large area.
For this reason, in a semiconductor device using a protection element, there are restrictions on the downsizing of the device and the freedom of layout design.
Therefore, even when the design rule is reduced to 90 nm or less, a configuration capable of forming a protective element with a relatively small area is required.

  In order to solve the above-described problems, the present invention provides a protective element that can be formed with a relatively small area and can be operated as a protective element even if the element size is miniaturized. To do. Moreover, the semiconductor device provided with this protection element is provided.

The protection element of the present invention includes a semiconductor substrate, a first conductivity type well region formed in the semiconductor substrate, and a second conductivity formed in the semiconductor substrate adjacent to the first conductivity type well region. And a well region of the mold.
Also, a second conductivity type channel MOS transistor formed in the first conductivity type well region is included.
Further, the first wiring electrically connected to the first conductivity type well region, the source region of the MOS transistor, and the gate of the MOS transistor, the drain region of the MOS transistor, and the second conductivity type well region are electrically connected. Connected second wiring.

  The semiconductor device of the present invention includes a circuit element and a protection element connected to the circuit element and having the configuration of the protection element of the present invention.

According to the above-described configuration of the protection element of the present invention, the second conductivity type well region is formed adjacent to the first conductivity type well region where the MOS transistor is formed, and the drain region of the MOS transistor and the second conductivity type well region are formed. A conductive type well region is electrically connected to the second wiring.
Thus, when a surge input is input from the second wiring, not only from the drain region of the MOS transistor but also from the PN junction surface between the first conductivity type well region and the second conductivity type well region. Can be injected.
Therefore, since the amount of injected carriers is greatly increased, the potential rises when a surge input is applied, so that the trigger potential can be lowered and the protection element can be operated quickly.

  According to the above-described configuration of the semiconductor device of the present invention, since the protection element of the present invention is connected to the circuit element, the protection element can be operated quickly and the circuit element can be protected from surge input.

According to the present invention described above, since the trigger potential can be lowered and the protection element can be operated quickly, the element can be operated as a protection element even if the element size is miniaturized.
In addition, since the protection element can be configured in the range of the first conductivity type well region including the MOS transistor and the adjacent second conductivity type well region, the protection element can be formed with a relatively small area. it can.

It is a schematic block diagram (sectional drawing) of the protection element of 1st Embodiment. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is a schematic block diagram (sectional drawing) of the protection element of 2nd Embodiment. It is a schematic block diagram (sectional drawing) of the protection element of 3rd Embodiment. It is a manufacturing process figure which shows the manufacturing method of the protection element of FIG. It is sectional drawing which shows the method of isolation | separation of the N type buried region in case a semiconductor substrate is N type. It is sectional drawing which shows the isolation | separation method of the N type buried region when a semiconductor substrate is a P type. FIG. 2 is a cross-sectional view of a configuration in which an N-type buried region is removed from the configuration of FIG. 1. It is a circuit block diagram which shows the example of a connection of an internal circuit and a protection element. It is a schematic sectional drawing of the protection element of a comparative example. It is a figure which shows the relationship between the drain voltage of each sample of an Example and a comparative example, and an electric current.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. First Embodiment 2. FIG. Second Embodiment 3. FIG. Third embodiment 4. Modification 5 Application Example 6 Experiment

<1. First Embodiment>
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of the protective element according to the first embodiment.
The protection element of the present embodiment is a protection element for measures against ESD or the like.

As shown in FIG. 1, a second conductivity type, here N type buried region 2 is formed at a certain depth from the surface of the semiconductor substrate 1. A well region of the first conductivity type, here Pwell region 3, is formed on the N type buried region 2, and a second conductivity type channel, here N, is formed on the right side of the surface of the Pwell region 3. A type channel MOSFET (field effect type MOS transistor) is formed.
The N-type channel MOSFET includes an N-type source / drain region 6, a P-type channel region 7 therebetween, N-type LDD regions 8 formed on the left and right of the surface of the channel region 7, and a semiconductor substrate 1. The gate insulating film 10 and the gate electrode 11 are formed on the surface.

The semiconductor substrate 1 on the right side of the Pwell region 3 has a second conductivity type well region, here Nwell region 4, for electrically connecting the N type buried region 2 and the surface of the semiconductor substrate 1. Is formed.
An element isolation layer 5 made of a field oxide film buried in the semiconductor substrate 1 is formed around each of the Pwell region 3, the MOSFET, and the Nwell region 4.
Further, silicide layers 9 made of metal silicide are formed on the surfaces of the Pwell region 3, the MOSFET source / drain region 6, and the Nwell region 4. A silicide layer 12 made of the same metal silicide is also formed on the gate electrode 11.
Sidewalls 13 made of an insulating layer are formed on the side walls of the gate electrode 11 and the silicide layer 12.

A plug layer 14 embedded in an interlayer insulating layer 15 is connected to the silicide layers 9 and 12 on the Pwell region 3 and Nwell region 4 and the gate electrode 11.
A wiring layer 16 is formed on the interlayer insulating layer 15 so as to be connected to the plug layer 14. Two wiring layers 16 are formed on the left and right. The left wiring layer 16 (first wiring) is electrically connected to the Pwell region 3, the MOSFET source region, and the gate electrode 11. The right wiring layer 16 (second wiring) is electrically connected to the drain region of the MOSFET and the Nwell region 4.

Further, for example, of the two wiring layers 16, the left wiring layer 16 (first wiring) is connected to the ground terminal (ground terminal), and the right wiring layer 16 (second wiring) is used as the input / output terminal. Connecting.
In this way, the left wiring layer 16 (first wiring) and the right wiring layer 16 (second wiring) are electrically connected between the protective element such as the ground terminal and the input / output terminal and the outside of the protective element. Electrically connect to the external terminal to be connected.

As the semiconductor substrate 1, a silicon substrate or a semiconductor substrate made of other semiconductors (Ge, compound semiconductor, etc.) can be used.
As a metal constituting the metal silicide of the silicide layers 9 and 12, nickel, cobalt, titanium, or the like can be used.
The gate electrode 11 can be formed of polysilicon or the like.
As the insulating layer of the sidewall 13, a TEOS (Tetraethyl orthosilicate) oxide film or the like can be used.
As the metal material of the plug layer 14 and the wiring layer 16, tungsten, copper, aluminum, or the like can be used.

In the protection element of the present embodiment, in particular, the Nwell region 4 and the other wiring layer 16 on the right are electrically connected. Therefore, a surge input is applied to a terminal (pad) connected to the wiring layer 16. If so, carriers are injected from the wiring layer 16 into the Nwell region 4. Since the N well region 4 and the N type buried region 2 connected therebelow have the same conductivity type, carriers are also injected into the N type buried region 2.
As a result, carriers are injected from the PN junction surface with both the right Nwell region 4 and the lower N-type buried region 2 with respect to the Pwell region 3, so that many carriers are injected from the PN junction surface having a large area. Can be injected. For this reason, a current flows with a lower drain voltage, and the trigger potential Vt1 can be lowered to satisfy Vt1 <BVox.

The protection element of the present embodiment can be manufactured, for example, as described below.
Using an N-type silicon substrate as the semiconductor substrate 1, an SiO ₂ film 21 and an Si ₃ N ₄ film 22 are sequentially deposited on the N-type silicon substrate.
Thereafter, a resist (not shown) is formed so as to cover the surface, and patterning is performed so that a portion to be an active region remains. Then, using this resist pattern as a mask, the Si ₃ N ₄ film 22, the SiO ₂ film 21, and the silicon substrate 1 are sequentially etched to form a groove (trench region) 23.
At this time, the silicon substrate is etched at a depth of, for example, 350 to 400 nm.
The region where the Si ₃ N ₄ film 22 is left becomes an active region later, and the trench region later becomes an element isolation layer.

Thereafter, the groove 23 is filled with the SiO ₂ layer 24. For example, a dense film with good step coverage can be formed by embedding using a high-density plasma CVD (Chemical Vapor doposition) method.
Subsequently, polishing is performed by CMP (Chemical Mechanical Polish) to flatten the surface. In the region near the boundary of the Si ₃ N ₄ film 22, it is polished to the extent that the SiO ₂ layer 24 on _{the Si} 3 _{N 4} film 22 can be removed. As a result, as shown in FIG. 2, the SiO ₂ layer 24 remains only in the groove 23.

Next, the Si ₃ N ₄ film 22 is removed by, for example, hot phosphoric acid to form an active region.
Subsequently, the surface of the active region is oxidized with a thickness of, for example, 10 nm to form an oxide film (sacrificial oxide film) 26.

  Next, ion implantation for forming the Pwell region 3, the N-type buried region 2, and the channel region 7 for adjusting the Vth of the NMOSFET is performed in the region where the NMOSFET is to be formed. Further, ion implantation for forming the Nwell region 4 is performed in a region adjacent to the region for forming the NMOSFET.

In the Pwell region 3 and the channel region 7, for example, boron is ion-implanted in three stages. Ion implantation of each stage, 200~300keV, and ^{2 × 10 13 atoms / cm 2} , 100keV, and ^{2 × 10 13 atoms / cm 2} , and ^{20keV, 3 × 10 12 atoms /} cm 2 and the like. In this case, the Pwell region 3 is formed by two-stage ion implantation with different depths.
The N-type buried region 2 is formed of, for example, phosphorus at 400 to 500 keV and 3 × 10 ¹³ atoms / cm ² .
The Nwell region 4 for connection to the N-type buried region 2 is formed by, for example, ion implantation of phosphorus at 50 to 200 keV, 3 × 10 ¹³ atoms / cm ² .
In this manner, as shown in FIG. 3, the N-type buried region 2, the Pwell region 3, the Nwell region 4, and the channel region 7 can be formed. Further, as shown in FIG. 3, the element isolation layer 5 is formed from the SiO ₂ layer 24 remaining inside the trench.

Next, the oxide film (sacrificial oxide film) 26 is removed with a hydrofluoric acid solution.
Thereafter, an oxide film to be the gate insulating film 10 is formed to a thickness of about 7 nm on the surface of the silicon substrate by dry oxidation (oxygen, 700 ° C.).
Next, a polysilicon layer is deposited to a thickness of 150 to 200 nm by a low pressure CVD method. The conditions of the low pressure CVD method are, for example, SiH ₄ as a source gas and a deposition temperature of 580 to 620 ° C.
Further, after patterning the resist by lithography, the polysilicon layer is patterned by anisotropic etching using the resist as a mask to form a gate electrode 11 on the gate insulating film 10 as shown in FIG. Form. At this time, for example, patterning is performed so that the gate length is 100 nm to 250 nm.

Subsequently, for example, arsenic is ion-implanted at 5 keV and 2 × 10 ¹⁴ atoms / cm ² in the region where the NMOSFET is to be formed, thereby forming an N-type LDD region 8 as shown in FIG.

Next, in order to form the sidewall spacer, a TEOS (Tetraethyl orthosilicate) oxide film is deposited with a thickness of 150 to 200 nm by, for example, a CVD method.
Subsequently, anisotropic etching is performed on the TEOS oxide film to form sidewalls 13 on the sidewalls of the gate electrode 11 as shown in FIG.

Next, for example, phosphorus is ion-implanted in the region where the NMOSFET is formed at 10 to ¹⁵ keV and 1 × 10 ^{15 to} 3 × 10 ¹⁵ atoms / cm ² , thereby forming an N-type source as shown in FIG. -The drain region 6 is formed.
Thereafter, impurities are activated by RTA (Rapid Thermal Annealing) at 1000 ° C. for 5 seconds to form a MOSFET. In addition, annealing can be performed at 1050 ° C. for 0 sec by the Spike RTA method for the purpose of promoting dopant activation and suppressing diffusion.

Next, a metal film for forming a silicide, for example, a nickel film is deposited on the surface with a film thickness of 10 nm by sputtering.
Next, the RTA method is performed under the conditions of 400 to 500 ° C. for 30 seconds to silicide only the surface of silicon (silicon substrate and polysilicon layer of the gate electrode 11).
Thereafter, unreacted nickel remaining on the field oxide film of the element isolation layer 5 is removed by H ₂ SO ₄ / H ₂ O ₂ .
Subsequently, for example, by performing RTA at 500 ° C. for 30 seconds, a silicide layer 9 made of a low-resistance NiSi layer is formed on the surface of the semiconductor substrate 1 as shown in FIG. Then, a silicide layer 12 made of a low resistance NiSi layer is formed.

It is also possible to form NiSi ₂ as the silicide layers 9 and 12 by depositing NiPt.
Further, the silicide layers 9 and 12 can be formed even if other materials such as cobalt and titanium are used. In any case, the temperature of the RTA can be set as appropriate.

Subsequently, wiring is formed so as to obtain a desired circuit.
That is, the plug layer 14 made of a metal material is formed in the interlayer insulating layer 15 so as to be connected to the silicide layers 9 and 12 on the diffusion layer (Pwell region 3 and Nwell region 4) and on the gate. Further, a wiring layer 16 is formed on the interlayer insulating layer 15 so as to be connected to the plug layer 14. As the material of the plug layer 14 and the wiring layer 16, a metal material such as tungsten, copper, or aluminum is used. The Pwell region 3, the MOSFET source region, and the gate electrode 11 are electrically connected to the left wiring layer 16, and the MOSFET drain region and the Nwell region 4 are electrically connected to the right wiring layer 16. To do.
In this way, the protection element shown in FIG. 1 can be manufactured.

According to the configuration of the protection element of the present embodiment described above, the N-type buried region 2 is formed under the Pwell region 3 and the Nwell region 4 formed adjacent to the left and right. The drain region of the NMOSFET formed in the Pwell region 3 and the Nwell region 4 are electrically connected to the right wiring layer 16.
Thus, when a surge input is input from the right wiring layer 16, not only from the drain region of the NMOSFET, but also from the PN junction surface between the Pwell region 3, the Nwell region 4, and the N-type buried region 2 Can be injected.
Therefore, the amount of injected carriers is greatly increased, so that the potential rises when a surge input is applied, so that the trigger potential Vt1 can be lowered and the protection element can be operated quickly.
Thus, the trigger potential Vt1 can be lowered and the protection element can be operated quickly, so that it can be operated as a protection element even if the element size is miniaturized. For example, the protective element can be operated before the breakdown voltage of the gate insulating film of the internal circuit to which the protective element is connected to protect the internal circuit.

In addition, according to the configuration of the present embodiment, since the protection element can be configured in the range of the Pwell region 3 including the MOSFET and the adjacent Nwell region 4, it is possible to form the protection element with a relatively small area. Is possible.
In addition, the area of the protection element can be reduced as compared with an RC circuit or a diode-type protection element.

And the semiconductor device provided with the protection element can be comprised using the protection element of this Embodiment.
For example, the protection element according to the present embodiment is arranged around the circuit element constituting the semiconductor device so that surge input is input to the protection element.

<2. Second Embodiment>
FIG. 9 shows a schematic configuration diagram (cross-sectional view) of the protection element according to the second embodiment.
In the present embodiment, the well regions and the conductivity types of the MOSFETs are reversed with respect to the configuration of the first embodiment. That is, the first conductivity type is N-type, the second conductivity type is P-type, a PMOSFET is formed in the Nwell region, and a Pwell region is formed adjacent to the Nwell region.

  In this embodiment, as shown in FIG. 9, a P-type buried region 17 is formed in the semiconductor substrate 1, an Nwell region 18 and a Pwell region 19 are formed thereon, and a PMOSFET is formed in the Nwell region 18. Form. The source / drain region 6 and the LDD region 8 of the MOSFET are N-type in the first embodiment, but are P-type in the present embodiment. The channel region 7 of the MOSFET is P-type in the first embodiment, but is N-type in the present embodiment.

Further, for example, of the two wiring layers 16, the left wiring layer 16 (first wiring) electrically connected to the source region and the gate electrode 11 is connected to the input / output terminal, and the drain region and the Pwell region 19. The right wiring layer 16 (second wiring) connected to is connected to the power supply terminal.
In this manner, the left wiring layer 16 (first wiring) and the right wiring layer 16 (second wiring) are electrically connected between the protective element such as the input / output terminal and the power supply terminal and the outside of the protective element. Electrically connect to the external terminal to be connected.

  Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given and redundant description is omitted.

According to the configuration of the protection element of the present embodiment described above, the P-type buried region 17 is formed under the Nwell region 18 and the Pwell region 19 formed adjacent to the left and right. The drain region of the PMOSFET formed in the Nwell region 18 and the Pwell region 19 are electrically connected to the right wiring layer 16.
Thus, when a surge input is input from the right wiring layer 16, not only from the drain region of the PMOSFET, but also from the PN junction surface between the Nwell region 18, the Pwell region 19, and the P-type buried region 17. Can be injected.
Therefore, the amount of injected carriers is greatly increased, so that the potential rises when a surge input is applied, so that the trigger potential Vt1 can be lowered and the protection element can be operated quickly.
Thus, the trigger potential Vt1 can be lowered and the protection element can be operated quickly, so that it can be operated as a protection element even if the element size is miniaturized. For example, the protective element can be operated before the breakdown voltage of the gate insulating film of the internal circuit to which the protective element is connected to protect the internal circuit.

In addition, according to the configuration of the present embodiment, the protection element can be configured in the range of the Nwell region 18 including the MOSFET and the adjacent Nwell region 19, so that the protection element can be formed with a relatively small area. Is possible.
In addition, the area of the protection element can be reduced as compared with an RC circuit or a diode-type protection element.

And the semiconductor device provided with the protection element can be comprised using the protection element of this Embodiment.
For example, the protection element according to the present embodiment is arranged around the circuit element constituting the semiconductor device so that surge input is input to the protection element.

<3. Third Embodiment>
FIG. 10 shows a schematic configuration diagram (cross-sectional view) of the protection element of the third embodiment.
In this embodiment, the area of the PN junction interface is widened to facilitate carrier injection.

  In the present embodiment, as shown in FIG. 10, irregularities are provided at the interface between the Pwell region 3 and the N-type buried region 2. As a result, the area of the interface of the PN junction can be widened to facilitate carrier injection.

  Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given and redundant description is omitted.

The protection element of the present embodiment can be manufactured, for example, as described below.
First, the N-type buried region 2 is formed slightly thicker than that in the first embodiment.
Next, the Pwell region 3, two steps of ion implantation (e.g., 200～300KeV, and ^{2 × 10 13 atoms / cm 2} , 100keV, 2 × 10 13 atoms / cm 2) by forming. However, a resist mask is used at a location where the PN junction surface is desired to be increased during two-stage deep ion implantation (for example, 200 to 300 keV, 2 × 10 ¹³ atoms / cm ² ). Then, as shown in the manufacturing process diagram of FIG. 11, a portion 3 </ b> A in which a P-type impurity is implanted into the Nwell region 2 and changed to the Pwell region 3, and a portion that is not implanted and remains in the Nwell region 2 are formed. . In FIG. 11, the Pwell region 3A below the broken line is formed by two-stage deep ion implantation, and the Pwell region 3B above the broken line is formed by two-stage shallow ion implantation. Formed.
In this manner, as shown in FIG. 10, irregularities can be provided at the interface between the Pwell region 3 and the N-type buried region 2.

According to the configuration of the present embodiment described above, the N-type buried region 2 is formed under the Pwell region 3 and the Nwell region 4 formed adjacent to the left and right. The drain region of the NMOSFET formed in the Pwell region 3 and the Nwell region 4 are electrically connected to the right wiring layer 16.
Accordingly, similarly to the first embodiment, the amount of injected carriers can be greatly increased, so that the potential rise when a surge input is input becomes faster, the trigger potential Vt1 is lowered, and the protection element Can be operated quickly.
Thus, the trigger potential Vt1 can be lowered and the protection element can be operated quickly, so that it can be operated as a protection element even if the element size is miniaturized. For example, the protective element can be operated before the breakdown voltage of the gate insulating film of the internal circuit to which the protective element is connected to protect the internal circuit.

In addition, according to the configuration of the present embodiment, since the protection element can be configured in the range of the Pwell region 3 including the MOSFET and the adjacent Nwell region 4, it is possible to form the protection element with a relatively small area. Is possible.
In addition, the area of the protection element can be reduced as compared with an RC circuit or a diode-type protection element.

  Furthermore, according to the configuration of the present embodiment, irregularities are provided at the interface between the Pwell region 3 and the N-type buried region 2. As a result, the area of the interface of the PN junction can be widened and carriers can be easily injected, so that the potential rise when a surge input is further increased, the trigger potential Vt1 is reduced, and the protection element is It can be operated quickly.

And the semiconductor device provided with the protection element can be comprised using the protection element of this Embodiment.
For example, the protection element according to the present embodiment is arranged around the circuit element constituting the semiconductor device so that surge input is input to the protection element.

  In addition, it is also possible to apply the structure which provided the unevenness | corrugation in the interface of PN junction of 3rd Embodiment to the structure of 2nd Embodiment which has PMOSFET shown in FIG. That is, it is possible to increase the area of the PN junction interface by providing irregularities at the interface between the Nwell region 18 and the P-type buried region 17 in FIG.

  In the case where unevenness is provided at the interface of the PN junction, the direction of the unevenness is not limited to the direction shown in FIG. For example, a configuration having irregularities in the front-rear direction of FIG. 10 may be used.

<4. Modification>
In each of the above-described embodiments, the N-type buried region 2 and the P-type buried region 17 are formed in a planar pattern wider than the combined pattern of the well regions 3, 4, 18, and 19 thereon.
On the other hand, the N-type buried region 2 and the P-type buried region 17 may be formed in substantially the same plane pattern as the pattern obtained by combining the well regions 3, 4, 18 and 19 thereon.

Further, the N-type buried region 2 and the P-type buried region 17 can be provided with a buried region having a depth and impurity concentration similar to those of the protective element in the circuit element.
When manufacturing this structure, the protection element embedded region and the circuit element embedded region can be formed at the same time.
However, if the protection element embedded region and the circuit element embedded region are formed continuously, an unnecessary current may flow in the circuit element embedded region when a surge is input.
For this reason, it is necessary to electrically isolate the buried region between the protection element and the circuit element.

  As a configuration in which both buried regions are electrically separated, a configuration in which the buried region is separated just outside the protective element is shown in the cross-sectional views of FIGS. FIG. 12 shows a case where the semiconductor substrate 1 is N-type and the N-type buried region 2 is separated. FIG. 13 shows a case where the semiconductor substrate 1 is P-type and the N-type buried region 2 is separated.

In the configuration shown in FIG. 12, the semiconductor substrate 1 is N-type, and the semiconductor substrate 1 has the same conductivity type as the N-type buried region 2. For this reason, if not only the N-type buried region 2 is insulated and separated but also the semiconductor substrate 1 is not insulated and separated, an unnecessary current may flow through the semiconductor substrate 1.
Therefore, in the configuration shown in FIG. 12, the semiconductor substrate 1 and the N-type buried region 2 are separated by the insulating layer 20 in which the hole formed by the trench is filled so as to penetrate the semiconductor substrate 1 and the N-type buried region 2. is doing. As the material of the insulating layer 20, SiO ₂ or other insulating materials can be used, and the same material as that of the element isolation layer 5 may be used.

As a method of forming the insulating layer 20 shown in FIG. 12, for example, the following method can be considered.
First, a non-through hole that penetrates the N-type buried region 2 but does not reach the bottom of the semiconductor substrate 1 is formed in the semiconductor substrate 1 by trench processing.
Next, this non-through hole is filled with the insulating layer 20.
Thereafter, the back surface side of the semiconductor substrate 1 is shaved until the insulating layer 20 is exposed on the back surface.
In this way, the insulating layer 20 penetrating the semiconductor substrate 1 and the N-type buried region 2 can be formed, and the protection element and the circuit element can be electrically separated.

In the configuration shown in FIG. 13, the semiconductor substrate 1 is P-type, and the semiconductor substrate 1 is of a conductivity type opposite to the N-type buried region 2. For this reason, even if the semiconductor substrate 1 is not separated, unnecessary current does not flow through the semiconductor substrate 1.
Therefore, in the configuration shown in FIG. 13, the N-type buried region 2 is formed in a pattern separated from the protection element and the periphery of the protection element. Since there is a P-type semiconductor substrate 1 between the separated N-type buried regions 2, unnecessary current does not flow.

As in the second embodiment, when the P-type buried region 17 is formed, depending on the conductivity type relationship between the semiconductor substrate 1 and the P-type buried region 17, Alternatively, a configuration similar to that shown in FIG. 13 may be selected.
When the P-type buried region 17 is formed in the N-type semiconductor substrate 1, since the conductivity type is reversed, the P-type buried region 17 is separated by the protective element and its surroundings as in FIG. To form a patterned pattern.
When the P-type buried region 17 is formed in the P-type semiconductor substrate 1, the conductivity type is the same. Therefore, as in FIG. 12, the insulating layer 20 penetrating the P-type buried region 17 and the semiconductor substrate 1. Is formed to separate the protective element from its surroundings.

Furthermore, as a modification, a configuration in which the embedded well regions 2 and 17 are excluded from the configuration shown in FIGS. For example, a configuration shown in a sectional view in FIG. 14 can be considered.
Even in this configuration, since the Nwell region 4 and the Pwell region 19 on the right side in the figure are electrically connected to the wiring layer 16, the carrier from the PN junction surface at the interface with the Nwell region 4 and Pwell region 19 on the right side Can be injected. Thereby, the trigger potential Vt1 can be lowered.

  The configurations of the above-described embodiments and modifications can be combined as appropriate as long as the configurations do not contradict each other.

<5. Application example>
As described above, a semiconductor device including a protection element can be formed using the protection element of each embodiment. The protection elements of the respective embodiments are arranged around the circuit elements constituting the semiconductor device so that surge input is input to the protection elements.

Here, FIG. 15 shows a circuit configuration diagram of an example of connection between an internal circuit as a circuit element and a protection element.
As shown in FIG. 15, two protection elements 31 and 32 are connected between the internal circuit 30 and the terminal. As the terminals, there are provided three terminals from the top in the figure: a Vdd terminal, an I / O terminal (input / output terminal), and a ground terminal (Gnd.). A first protection element 31 is connected to each wiring from the Vdd terminal and the I / O terminal, and a second protection element 32 is connected to each wiring from the I / O terminal and the ground terminal.
For example, in the first protective element 31 and the second protective element 32, the left wiring layer 16 (first wiring) and the right wiring layer 16 (first wiring) shown in FIGS. 2 wiring) is electrically connected to the internal circuit 30 which is a circuit element and the three terminals in FIG. For example, the first wiring of the first protection element 31 is connected to the Vdd terminal, and the second wiring of the first protection element 31 and the first wiring of the second protection element 32 are connected to the input / output terminal. The second wiring of the second protection element 32 is connected to the ground terminal. In this case, three terminals, that is, a Vdd terminal, an I / O terminal (input / output terminal), and a ground terminal (Gnd.) Are, for example, an external that electrically connects a package or chip of a semiconductor device and the outside thereof. Corresponds to the terminal.

The first protection element 31 and the second protection element 32 may have either a configuration having an NMOSFET as shown in FIG. 1 or a configuration having a PMOSFET as shown in FIG. .
For example, both the first protection element 31 and the second protection element 32 may have an NMOSFET. In this case, each part of the two protection elements 31 and 32 can be formed simultaneously in the same manufacturing process.
Further, for example, the first protection element 31 may have a PMOSFET, and the second protection element 32 may have an NMOSFET. In this case, as shown in FIGS. 12 and 13, even if the well region is not insulated and separated, the same potential can be prevented from the power source to the ground.

Note that the names of the terminals (Vdd, I / O, Gnd.) In FIG. 15 indicate potentials supplied to the terminals when the semiconductor device is used.
In particular, at the time of manufacturing a semiconductor device, each terminal is still in a floating state in terms of potential, and a positive surge input or a negative surge input may be input to any terminal.

<6. Experiment>
Here, a sample of the protective element was actually manufactured and the characteristics were examined.
First, the protective element according to the first embodiment shown in FIG. 1 was produced and used as a sample of the example.
On the other hand, as shown in FIG. 16, the drain and wiring layer 16 and the Nwell region 4 are not electrically connected without providing the plug layer 14 between the wiring layer 16 connected to the drain and the Nwell region 4. It was. Otherwise, a protective element was produced in the same manner as in the example, and this was used as a sample for comparison.

Electrical stress was applied to each sample of the example and the comparative example. Specifically, an ESD surge was applied to the pad on the right wiring layer 16 on the drain side, and the pad on the left wiring layer 16 on the other source and gate side was grounded to the ground level.
Then, the drain voltage (ESD surge voltage) was changed, and the change of the current flowing in the channel of the MOSFET was examined.
As a measurement result, the relationship between the drain voltage and the current of each sample is shown in FIG.

As shown in FIG. 17, in the comparative example (GGMOS structure), Vt1 was about 10V. In contrast, in the example, Vt1 was about 3V and 7V lower.
In the comparative example, after reaching Vt1, the drain voltage drops by snapback, whereas in the example, the drain voltage rises gently. This is presumably because, in the embodiment, since a large amount of carriers are injected, the breakdown proceeds little by little and no snapback occurs.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 Semiconductor substrate, 2 N type buried region, 3,19 Pwell region, 4,18 Nwell region, 5 element isolation layer, 6 source / drain region, 7 channel region, 8 LDD region, 9,12 silicide layer, 10 gate Insulating film, 11 gate electrode, 13 sidewall, 14 plug layer, 15 interlayer insulating layer, 16 wiring layer, 17 P-type buried region, 20 insulating layer, 30 internal circuit, 31 first protection element, 32 second Protective element

Claims (12)

A semiconductor substrate;
A first conductivity type well region formed in the semiconductor substrate;
A second conductivity type well region formed in the semiconductor substrate adjacent to the first conductivity type well region;
A second conductivity type channel MOS transistor formed in the first conductivity type well region;
A first wiring electrically connected to the well region of the first conductivity type, the source region of the MOS transistor, and the gate of the MOS transistor;
A protection element including a drain region of the MOS transistor and a second wiring electrically connected to the well region of the second conductivity type.   The protection element according to claim 1, further comprising a second conductivity type buried region connected below the first conductivity type well region and the second conductivity type well region.   The protective element according to claim 2, wherein unevenness is formed on a joint surface between the first conductivity type well region and the second conductivity type buried region.   The protection element according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.   The protection element according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.   2. The protection element according to claim 1, wherein the first wiring is electrically connected to a ground terminal, and the second wiring is electrically connected to an input / output terminal.   The protection element according to claim 1, wherein the first wiring is electrically connected to an input / output terminal, and the second wiring is electrically connected to a power supply terminal. Circuit elements;
A semiconductor substrate connected to the circuit element; a first conductivity type well region formed on the semiconductor substrate; and a first conductivity type well region formed on the semiconductor substrate adjacent to the first conductivity type well region, A second conductivity type well region; a second conductivity type channel MOS transistor formed in the first conductivity type well region; the first conductivity type well region; a source region of the MOS transistor; A protection including a first wiring electrically connected to the gate of the MOS transistor, and a second wiring electrically connected to the drain region of the MOS transistor and the well region of the second conductivity type A semiconductor device comprising an element.   9. The semiconductor device according to claim 8, wherein the protection element further includes a second conductivity type buried region connected under the first conductivity type well region and the second conductivity type well region.   The semiconductor substrate is of a second conductivity type, and further includes an insulating layer that is formed around the protection element so as to penetrate the semiconductor substrate and the embedded region of the second conductivity type and insulate and isolate the protection element. The semiconductor device according to claim 9.   The semiconductor according to claim 8, wherein the first wiring of the protection element is electrically connected to a ground terminal, and the second wiring of the protection element is electrically connected to an input / output terminal. apparatus.   The semiconductor according to claim 8, wherein the first wiring of the protection element is electrically connected to an input / output terminal, and the second wiring of the protection element is electrically connected to a power supply terminal. apparatus.