TW202228271A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first transistor, a second transistor, a first guard ring, a second guard ring, a first conductive plug, and a second conductive plug. The substrate has a first conductive type and includes a first well having a second conductive type different from the first conductive type and a second well having the first conductive type in the first well. The first guard ring disposed in the second well has the first conductive type and surrounds the first transistor. The second guard ring disposed in the first well has the second conductive type and surrounds the second transistor. The first conductive plug is disposed on and electrically connected with the first guard ring. The second conductive plug is disposed on and electrically connected with the second guard ring. At least one of the first conductive plug and the second conductive plug has a portion embedded in the substrate.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a guard ring.

In integrated circuits with complementary metal oxide semiconductor (CMOS), it is often due to parasitic PNPN silicon controlled rectifier (SCR) or parasitic NPN or PNP bipolar junction transistor (bipolar junction transistor, BJT) and produce a latch-up effect (Latch-Up), causing the integrated circuit to not operate normally. For example, in a CMOS device, a parasitic NPN transistor and a parasitic PNP transistor (PNP) can form a parasitic SCR with a PNPN structure. That is, a parasitic SCR may be formed between the source of the P-type metal oxide semiconductor (PMOS) (connected to the VDD voltage) and the source of the N-type metal oxide semiconductor (NMOS) (connected to the VSS voltage). When the parasitic SCR is turned on to produce a latch-up effect, a short circuit will occur between the source (VDD) of the PMOS and the source (VSS) of the NMOS, causing the CMOS device to fail to operate normally.

The present invention provides a semiconductor device and a method of fabricating the same. By burying a conductive plug electrically connected to a guard ring in a substrate, the resistance of the well region under the transistor is reduced to prevent undesired latch-up.

The present invention provides a semiconductor device including a substrate, a first transistor, a second transistor, a first guard ring, a second guard ring, a first conductive plug and a second conductive plug. The substrate has a first conductivity type and includes a first well region and a second well region located in the first well region. The first well region has a second conductivity type different from the first conductivity type. The second well region has the first conductivity type. The first transistor is disposed on the second well region and includes a first gate structure and a first source/drain. The first gate structure is disposed on the second well region. The first source/drain has a second conductivity type and is disposed in the second well regions on opposite sides of the first gate structure. A second transistor is disposed on the first well region and includes a second gate structure and a second source/drain. The second gate structure is disposed on the first well region. The second source/drain has a first conductivity type and is disposed in the first well region on opposite sides of the second gate structure. The first guard ring has a first conductivity type and is disposed in the second well region and surrounds the first transistor. The second guard ring has a second conductivity type and is disposed in the first well region and surrounds the second transistor. The first conductive plug is disposed on the first guard ring and is electrically connected with the first guard ring. The second conductive plug is disposed on the second guard ring and is electrically connected with the second guard ring. At least one of the first conductive plug and the second conductive plug has a portion buried in the substrate.

In an embodiment of the present invention, the above-mentioned first guard ring has a first part and a second part. The depth of the first portion in the second well zone is greater than the depth of the second portion in the second well zone.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a first isolation structure and a second isolation structure. The first isolation structure is between the first source/drain and the first guard ring and between the second source/drain and the second guard ring. The second isolation structure is in the substrate and the first guard ring and the second guard ring are located between the first isolation structure and the second isolation structure. The depth of the first portion is greater than the depth of the first isolation structure and the second isolation structure in the substrate, and the depth of the second portion is less than the depth of the first isolation structure and the second isolation structure in the substrate.

In an embodiment of the present invention, the above-mentioned second guard ring has a third part and a fourth part. The depth of the fourth portion in the first well zone is greater than the depth of the third portion in the first well zone.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a first isolation structure and a second isolation structure. The first isolation structure is between the first source/drain and the first guard ring and between the second source/drain and the second guard ring. The second isolation structure is in the substrate and the first guard ring and the second guard ring are located between the first isolation structure and the second isolation structure. The depth of the fourth portion is greater than the depth of the first isolation structure and the second isolation structure in the substrate, and the depth of the third portion is smaller than the depth of the first isolation structure and the second isolation structure in the substrate.

In an embodiment of the present invention, the aforementioned second portion and the aforementioned third portion are adjacent to each other.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a dielectric layer. A dielectric layer is disposed on the substrate and covers the first and second transistors, wherein the first and second conductive plugs are disposed in the dielectric layer.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a metal silicide layer. The metal silicide layer is disposed on the first gate structure, the second gate structure, the first source/drain and the second source/drain.

In an embodiment of the present invention, one of the above-mentioned first conductive plug and the second conductive plug has a portion embedded in the substrate, and the other of the above-mentioned first conductive plug and second conductive plug One is placed on the base.

The present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A first isolation structure and a second isolation structure are formed in the substrate having the first conductivity type. The substrate includes a first well region with a second conductivity type and a second well region with the first conductivity type, and the second well region is disposed in the first well region. A first gate structure is formed on the second well region of the substrate. A second gate structure is formed on the first well region of the substrate. A groove between the first isolation structure and the second isolation structure is formed in at least one of the first well region and the second well region. A first doping process is performed to form a second guard ring with a second conductivity type and a first source/drain electrode in the first well region and the second well region, respectively, wherein the second guard ring is disposed on the first isolation between the structure and the second isolation structure, and the first source/drain electrodes are disposed on opposite sides of the first gate structure. A second doping process is performed to form a second source/drain electrode and a first guard ring with a first conductivity type in the first well region and the second well region, respectively, wherein the second source/drain electrode is disposed at On opposite sides of the second gate structure, a first guard ring is disposed between the first isolation structure and the second isolation structure. A dielectric layer covering the first gate structure and the second gate structure is formed on the substrate, wherein the dielectric layer has a first opening exposing the first source/drain and the second source/drain and exposing the The first guard ring and the second guard ring have second openings, and the positions of the second openings correspond to the positions of the grooves. Fill the first opening and the second opening with conductive material to form source/drain contact plugs on the first source/drain and the second source/drain, and form the first guard ring and the second guard A first conductive plug and a second conductive plug are respectively formed on the ring. At least one of the first conductive plug and the second conductive plug has a portion buried in the substrate.

In an embodiment of the present invention, the above-mentioned first doping process includes the following steps. A mask pattern is formed on the substrate, wherein the mask pattern exposes the second well region between the first gate structure and the first isolation structure and the first well region between the first isolation structure and the second isolation structure. A dopant having a second conductivity type is implanted into the first well region and the second well region exposed by the mask pattern. Remove the mask pattern.

In an embodiment of the present invention, the above-mentioned second doping process includes the following steps. A mask pattern is formed on the substrate, wherein the mask pattern exposes a first well region between the second gate structure and the first isolation structure and a second well region between the first isolation structure and the second isolation structure. A dopant having a first conductivity type is implanted into the first well region and the second well region exposed by the mask pattern. Remove the mask pattern.

In an embodiment of the present invention, the step of forming the groove includes using the first isolation structure and the second isolation structure as a mask, and removing the first well area and the second isolation structure between the first isolation structure and the second isolation structure. at least one of the two well zones.

In an embodiment of the present invention, the above-mentioned grooves, the first isolation structure and the second isolation structure are simultaneously formed by the following steps. An isolation structure is formed in the substrate. The isolation structure is patterned to form a first isolation structure, a second isolation structure, and a groove between the first isolation structure and the second isolation structure.

In an embodiment of the present invention, the above-mentioned manufacturing method of a semiconductor device further includes, before forming the dielectric layer, forming the first gate structure, the second gate structure, the first source/drain, and the second source A metal silicide layer is formed on the drain, the first guard ring and the second guard ring.

Based on the above, in the semiconductor device and the manufacturing method thereof of the present invention, the resistance of the well region under the transistor is reduced by burying the conductive plug electrically connected to the guard ring in the substrate to prevent undesired latch-up effect .

The present invention is more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions will not be repeated in the following paragraphs.

It will be understood that when an element such as that is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection, and "electrically connected" or "coupled" may refer to the presence of other elements between two elements. As used herein, "electrically connected" may include physical connections (eg, wired connections) and physical disconnects (eg, wireless connections).

The terminology used herein is used to illustrate exemplary embodiments only, and not to limit the disclosure. In this case, the singular includes the plural unless the context clearly dictates otherwise.

1 to 7 are schematic cross-sectional views of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein the structure shown in FIG. 2 can be formed by different embodiments shown in (a) or (b) of FIG. 1 . FIG. 8 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1( a ), a first isolation structure STI1 and a second isolation structure STI2 are formed in the substrate 100 having the first conductivity type. The substrate 100 may include a first well region 102 having the second conductivity type and a second well region 104 having the first conductivity type. The first conductivity type may be different from the second conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. Alternatively, the first conductivity type can also be N-type, and the second conductivity type can also be P-type. The substrate 100 may be a semiconductor substrate. In some embodiments, the following steps may be employed to form the first well region 102 and the second well region 104 in the substrate 100 . First, a patterned mask (not shown) is formed on the substrate 100 . Next, ion implantation is performed on the substrate 100 exposed by the patterned mask, so that the dopant having the second conductivity type can be implanted into the substrate 100 to form the first well region 102 in the substrate 100 . Then, another patterned mask (not shown) is formed on the first well region 102 . Then, ion implantation is performed on the first well region 102 exposed by the patterned mask, so that dopants with the first conductivity type can be implanted into the first well region 102 , so that the first well region 102 can be implanted in the first well region 102 . A second well region 104 is formed therein. Thereafter, after forming the second well region 104, the patterned mask may be removed. The above-mentioned patterned mask can include any suitable mask material such as photoresist.

The first isolation structure STI1 and the second isolation structure STI2 may be spaced apart from each other. In some embodiments, the second isolation structure STI2 may surround the first isolation structure STI1 (as shown in FIG. 8 ). In some embodiments, the following steps may be employed to form the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 . First, a patterned mask (not shown) is formed on the substrate 100 to define regions of the first isolation structure STI1 and the second isolation structure STI2 to be preformed subsequently. Next, a portion of the substrate 100 exposed by the patterned mask is removed through the aforementioned regions to form a first trench (not shown) and a second trench (not shown). Then, the patterned mask is removed and an insulating material is filled in the first trench and the second trench to form the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 , respectively. Although the above process is described with a shallow trench isolation (STI) structure as an exemplary embodiment, the present invention is not limited thereto. In other embodiments, the first isolation structure STI1 and the second isolation structure STI2 may also be isolation structures such as field oxide (FOX) layers. The patterned mask described above may include any suitable mask material such as photoresist. The insulating material may include any material suitable as an isolation structure, such as oxides.

Next, a second gate structure GS2 and a first gate structure GS1 are respectively formed on the first well region 102 and the second well region 104 of the substrate 100 . The first gate structure GS1 may be formed on the region defined by the first isolation structure STI1 in the second well region 104, and the second gate structure GS2 may be formed in the first well region 102 by the first isolation structure STI1. on the defined area. The first gate structure GS1 may include a gate GE1, a gate dielectric layer GD1 and a spacer SP1. The second gate structure GS2 may include a gate GE2, a gate dielectric layer GD2 and a spacer SP2. The gate electrodes GE1 and GE2 may include polysilicon or metal gate materials. The gate dielectric layers GD1 and GD2 may include silicon dioxide or a high-k (high-k) gate dielectric material. The spacers SP1 , SP2 may include nitride-based sidewall spacers (eg, including SiN) or oxide-based sidewall spacers (eg, SiO ₂ , SiOC, etc.).

In some embodiments, the first gate structure GS1 and the second gate structure GS2 may be formed through the following steps. First, a gate oxide material layer (not shown) and a gate material layer (not shown) are sequentially formed on the substrate 100 . Next, the gate material layer and the gate oxide material layer are patterned to form a gate dielectric layer GD2 on the first well region 102 and a gate electrode GE2 on the gate dielectric layer GD2, and the gate dielectric layer GD2 is formed on the second well region 104 A gate dielectric layer GD1 and a gate electrode GE1 located on the gate dielectric layer GD1 are formed thereon. Then, a spacer material layer (not shown) is formed on the substrate 100 to cover the top surfaces of the gate electrodes GE1 , GE2 and the sidewalls of the gate electrodes GE1 , GE2 and the gate dielectric layers GD1 , GD2 . Then, a process such as etching back is performed on the spacer material layer to remove the spacer material layer on the gate electrodes GE1, GE2 and the top surface of the substrate 100 and remain on the gate electrodes GE1, GE2 and the gate dielectric layer GD1, A layer of spacer material on the sidewalls of GD2 such that spacers SP1, SP2 are formed on the sidewalls of the gate electrodes GE1, GE2 and the gate dielectric layers GD1, GD2.

Referring to FIG. 2 , a groove 106 between the first isolation structure STI1 and the second isolation structure STI2 is formed in at least one of the first well region 102 and the second well region 104 . The depth of the grooves 106 may be greater than the depths of the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 . In some embodiments, the groove 106 may surround the first gate structure GS1 and/or the second gate structure GS2. In the embodiment shown in FIG. 2, a groove 106 is formed in the first well region 102 and the second well region 104 between the first isolation structure STI1 and the second isolation structure STI2, but the present invention does not use this method. limited. The grooves 106 may also be formed in one of the first well 102 and the second well 104 without being formed in the other of the first well 102 and the second well 104 .

In some embodiments, the grooves 106 may be formed through the following steps. First, a patterned mask (not shown) is formed on the substrate 100 to define regions of the grooves 106 to be formed subsequently. Next, the first well region 102 and the second well region 104 exposed by the patterned mask are removed through the region to form the groove 106 . For example, as shown in FIG. 2, the patterned mask exposes the first well region 102 and the second well region 104 between the first isolation structure STI1 and the second isolation structure STI2, so the grooves 106 are respectively formed in In the first well region 102 and the second well region 104 between the first isolation structure STI1 and the second isolation structure STI2. After that, the patterned mask is removed.

In some embodiments, in the step of removing the first well region 102 and the second well region 104 exposed by the patterned mask, the first isolation structure STI1 and the second isolation structure STI2 may be used as self-alignment The mask is used to remove the first well region 102 and the second well region 104 between the first isolation structure STI1 and the second isolation structure STI2, but the invention is not limited thereto. In other embodiments, the groove 106 , the first isolation structure STI1 and the second isolation structure STI2 can also be formed simultaneously by the following steps. Referring to FIG. 1( b ) and FIG. 2 , first, an isolation structure STI is formed in the substrate 100 . Next, the isolation structure STI is patterned to form the first isolation structure STI1, the second isolation structure STI2 and the groove 106 between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the following steps may be used to perform a patterning process on the isolation structure STI. First, a patterned mask (not shown) is formed on the substrate 100 to define regions where the grooves 106 are to be formed subsequently. Next, the isolation structure STI exposed by the patterned mask is removed through the region to form the first isolation structure STI1 , the second isolation structure STI2 and the space between the first isolation structure STI1 and the second isolation structure STI2 Groove 106 . After that, the patterned mask is removed.

Referring to FIG. 3, a first doping process is performed to form a guard ring GR2 and a source/drain electrode SD1 with a second conductivity type in the first well region 102 and the second well region 104, respectively. The guard ring GR2 may be disposed between the first isolation structure STI1 and the second isolation structure STI2, and the source/drain electrode SD1 may be disposed on opposite sides of the first gate structure GS1. In some embodiments, the first doping process may include the following steps. First, a mask pattern PR1 is formed on the substrate 100 . The mask pattern PR1 may expose the second well region 104 between the first gate structure GS1 and the first isolation structure STI1 and the first well region 102 between the first isolation structure STI1 and the second isolation structure STI2. Next, dopants with the second conductivity type are implanted into the first well region 102 and the second well region 104 exposed by the mask pattern PR1 to form a guard ring GR2 in the first well region 102 , and the A source/drain electrode SD1 is formed in the second well region 104 . After that, the mask pattern PR1 is removed. The mask pattern PR1 may include any suitable material as a mask, such as photoresist. In some embodiments, when the first doping process is performed, the gate GE1 of the first gate structure GS1 is also implanted with the same dopant (eg, the above-mentioned dopant having the second conductivity type).

Referring to FIG. 4 , a second doping process is performed to form a source/drain SD2 and a guard ring GR1 with a first conductivity type in the first well region 102 and the second well region 104 , respectively. The source/drain SD2 may be disposed on opposite sides of the second gate structure GS2, and the guard ring GR1 may be disposed between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the second doping process may include the following steps. First, a mask pattern PR2 is formed on the substrate 100 . The mask pattern PR2 may expose the first well region 102 between the second gate structure GS2 and the first isolation structure STI1 and the second well region 104 between the first isolation structure STI1 and the second isolation structure STI2. Next, dopants with a first conductivity type are implanted into the first well region 102 and the second well region 104 exposed by the mask pattern PR2 to form a source/drain electrode SD2 in the first well region 102 , And a guard ring GR1 is formed in the second well region 104 . After that, the mask pattern PR2 is removed. The mask pattern PR2 may include any suitable material as a mask, such as photoresist. In some embodiments, when the second doping process is performed, the gate GE2 of the second gate structure GS2 is also implanted with the same dopant (eg, the above-mentioned dopant having the first conductivity type).

Referring to FIG. 5 , the source/drain electrodes SD1 and SD2 and the guard rings GR1 and GR2 are annealed. In some embodiments, a rapid thermal process (RTP) may be used for annealing to eliminate implant damage and reduce doping in source/drain SD1, SD2 and guard rings GR1, GR2 diffusion of things. As shown in FIG. 5 , the source/drain electrode SD1 and the source/drain electrode SD2 are slightly diffused under the spacers SP1 and SP2, respectively, and the guard rings GR1 and GR2 are slightly diffused to the first isolation structure STI1 and the second isolation structure STI1 and the second isolation structure. Below the structure STI2.

Next, a metal silicide layer 108 is formed on the first gate structure GS1 , the second gate structure GS2 , the source/drain electrodes SD1 and SD2 and the guard rings GR1 and GR2 . The material of the metal silicide layer 108 may include silicides of cobalt, titanium or nickel, such as titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi). The etch rate ratio of titanium silicide to oxide is about 1:50 to 1:200. The etch rate ratio of cobalt silicide to oxide is about 1:10.

In some embodiments, the metal silicide layer 108 may be formed through the following steps. First, a metal layer (not shown) containing a metal such as cobalt, titanium, or nickel is formed on the substrate 100 . The metal layer may be conformally formed on the first isolation structure STI1, the second isolation structure STI2, the groove 106, the guard rings GR1, GR2, the source/drain electrodes SD1, SD2, the first gate structure GS1 and the second gate structure on the surface of GS2. In the area where metal silicide does not need to be formed, a dielectric layer can be formed first and yellow photo-etching is used to define the opening, and the opening can expose the position where the metal silicide is to be formed (such as the silicon substrate or the surface of the gate). Next, the metal layer is annealed, so that the metal layer reacts with the film layer containing doped silicon to form a metal silicide layer. After that, the unreacted metal layer is removed. That is, the metal silicide layer 108 is formed on the guard rings GR1, GR2, the source/drain electrodes SD1, SD2, and the gate electrodes GE1, GE2 in contact with the metal silicide material layer. In other embodiments, the metal silicide layer 108 can also be subjected to a salicide process after the dielectric layer 200 having the first opening 202 and the second opening 204 (as shown in FIG. 6 ) is formed. , to form the metal silicide layer 108 on the source/drain electrodes SD1 and SD2 exposed by the first opening 202 and the guard rings GR1 and GR2 exposed by the second opening 204, and on the exposed surface of the opening (not shown) A metal silicide layer 108 is formed on the gate electrodes GE1 and GE2, but the invention is not limited to this. In other embodiments, in some processes, the metal silicide layer 108 may not need to be formed.

Referring to FIG. 6 , a dielectric layer 200 covering the first gate structure GS1 and the second gate structure GS2 is formed on the substrate 100 . The dielectric layer 200 has a first opening 202 exposing the source/drain SD1 and the source/drain SD2 and a second opening 204 exposing the guard ring GR1 and the guard ring GR2. In some embodiments, the location of the second opening 204 may correspond to the location of the trench 106 . The material of the dielectric layer 200 may include silicon oxide.

In some embodiments, the dielectric layer 200 may be formed through the following steps. First, a dielectric covering the first gate structure GS1 , the second gate structure GS2 , the first isolation structure STI1 , the second isolation structure STI2 , the source/drain electrodes SD1 and SD2 and the guard rings GR1 and GR2 is formed on the substrate 100 . A layer of electrical material (not shown), wherein the layer of dielectric material also fills the trenches 106 . Next, a patterned mask (not shown) is formed on the dielectric material layer to define regions of the first opening 202 and the second opening 204 to be formed subsequently. After that, the dielectric material layer exposed by the patterned mask is removed through the region to form a first opening 202 exposing the source/drain electrodes SD1 and SD2 and a second opening 204 exposing the guard rings GR1 and GR2 . Then, the patterned mask is removed. In some embodiments, the dielectric material layer exposed by the patterned mask may be removed in a single-step or two-step manner, but the invention is not limited thereto. In some embodiments, as described above, the metal silicide layer process may be performed after the dielectric layer 200 having the first opening 202 and the second opening 204 is formed in some processes.

7, the first opening 202 and the second opening 204 are filled with conductive material to form source/drain contact plug SDC1 and source/drain on the source/drain SD1 and the source/drain SD2 The drain is in contact with the plug SDC2, and a conductive plug CP1 and a conductive plug CP2 are formed on the guard ring GR1 and the guard ring GR2, respectively. at least one of the conductive plug CP1 and the conductive plug CP2 has a portion buried in the substrate 100, which can reduce the resistance of the well region under the transistor (eg, the resistance of the first well region 102 and the second well region 104), to prevent undesired latch-up effects.

In some embodiments, the conductive plugs CP1 , CP2 and the source/drain contact plugs SDC1 , SDC2 may be formed through the following steps. First, a barrier material layer (not shown) is formed on the surface of the dielectric layer 200 and the surfaces of the first opening 202 and the second opening 204 . The barrier material layer does not fill the first openings 202 and the second openings 204 while leaving the central portions of the first openings 202 and the second openings 204 . Next, a conductive material layer (not shown) is formed on the barrier material layer. The conductive material layer fills the central portions of the first opening 202 and the second opening 204 . After that, the barrier material layer and the conductive material layer on the dielectric layer 200 are removed by a planarization process to form source/drain contact plugs including the barrier layer BL and the conductive layer CL in the first opening 202 SDC1 and SDC2, and conductive plugs CP1 and CP2 including a barrier layer BL and a conductive layer CL are formed in the second opening 204 . The material of the barrier layer BL may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The material of the conductive layer CL can be, for example, metal, metal alloy, metal nitride, metal silicide, or a combination thereof. In some exemplary embodiments, the metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride can be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or combinations thereof. The metal silicide is, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.

Hereinafter, the semiconductor device 10 according to an embodiment will be described with reference to FIGS. 7 and 8 . Although the semiconductor device 10 shown in FIGS. 7 and 8 is described by taking the above-mentioned manufacturing method as an example, the manufacturing method of the semiconductor device 10 of the present invention is not limited to this. The same or similar components are designated by the same or similar reference numerals, and the connection relationship, materials and manufacturing processes of other components have been described in detail above, so they will not be repeated hereinafter.

FIG. 8 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Fig. 7 is a schematic cross-sectional view taken along the line A-A' of Fig. 8 . For convenience of description, FIG. 8 only shows the first isolation structure STI1, the second isolation structure STI2, the first source/drain SD1, the second source/drain SD2, the first gate structure GS1, the first A schematic top view of the two-gate structure GS2, the first guard ring GR1, and the second guard ring GR2, so as to clearly understand the corresponding relationship of each component.

7 and 8, the semiconductor device 10 may include a substrate 100, a first transistor T1, a second transistor T2, a first guard ring GR1, a second guard ring GR2, a first isolation structure STI1, and a second isolation structure STI2 , the first conductive plug CP1 , the second conductive plug CP2 , the metal silicide layer 108 and the dielectric layer 200 .

The substrate 100 may have a first conductivity type and include a first well region 102 and a second well region 104 in the first well region 102 . The first well region 102 has a second conductivity type different from the first conductivity type. The second well region 104 has a first conductivity type.

The first transistor T1 may be disposed on the second well region 104 and include a first gate structure GS1 and a first source/drain SD1. The first gate structure GS1 may be disposed on the second well region 104 . The first source/drain SD1 may have a second conductivity type and be disposed in the second well regions 104 on opposite sides of the first gate structure GS1.

The second transistor T2 may be disposed on the first well region 102 and include a second gate structure GS2 and a second source/drain SD2. The second gate structure GS2 may be disposed on the first well region 102 . The second source/drain SD2 may have a first conductivity type and be disposed in the first well regions 102 on opposite sides of the second gate structure GS2.

The first guard ring GR1 may have a first conductivity type and be disposed in the second well region 104 and surround the first transistor T1. The first guard ring GR1 may be disposed between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the depth of the first guard ring GR1 in the substrate 100 may be greater than the depths of the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 . In other words, the bottom end of the first guard ring GR1 may be located at a lower level than the bottom ends of the first isolation structure STI1 and the second isolation structure STI2.

The second guard ring GR2 may have the second conductivity type and be disposed in the first well region 102 and surround the second transistor T2. The second guard ring GR2 may be disposed between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the depth of the second guard ring GR2 in the substrate 100 may be greater than the depths of the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 . In other words, the bottom end of the second guard ring GR2 may be located at a lower level than the bottom ends of the first isolation structure STI1 and the second isolation structure STI2.

The first isolation structure STI1 may be disposed in the substrate 100 between the first source/drain electrode SD1 and the first guard ring GR1 and between the second source/drain electrode SD2 and the second guard ring GR2.

The second isolation structure STI2 may be positioned in the substrate 100 and configured to surround the first guard ring GR1 and the second guard ring GR2, and the second isolation structure STI2 may have a position between the first guard ring GR1 and the second guard ring GR2 part.

The first conductive plug CP1 can be disposed on the first guard ring GR1 and the first guard ring GR1 is electrically connected. In some embodiments, the first conductive plug CP1 may be in contact with the first guard ring GR1 and surround the first transistor T1. In some embodiments, the first conductive plug CP1 may have a portion buried in the substrate 100 . In other words, the portion of the first conductive plug CP1 buried in the substrate 100 may be located between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the bottom end of the first conductive plug CP1 and the bottom ends of the first isolation structure STI1 and the second isolation structure STI2 may be located at the same level, but the invention is not limited thereto. In other embodiments, the bottom end of the first conductive plug CP1 and the bottom ends of the first isolation structure STI1 and the second isolation structure STI2 may be located at different levels.

The second conductive plug CP2 may be disposed on the second guard ring GR2 and electrically connected to the second guard ring GR2. In some embodiments, the second conductive plug CP2 may be in contact with the second guard ring GR2 and surround the second transistor T2. In some embodiments, the second conductive plug CP2 may have a portion buried in the substrate 100 . In some embodiments, the second conductive plug CP2 may have a portion buried in the substrate 100 . In other words, a portion of the second conductive plug CP2 buried in the substrate 100 may be located between the first isolation structure STI1 and the second isolation structure STI2. In some embodiments, the bottom end of the second conductive plug CP2 and the bottom ends of the first isolation structure STI1 and the second isolation structure STI2 may be located at the same level, but the invention is not limited thereto. In other embodiments, the bottom end of the second conductive plug CP2 and the bottom ends of the first isolation structure STI1 and the second isolation structure STI2 may be located at different levels.

The metal silicide layer 108 may be disposed on the first gate structure GS1, the second gate structure GS2, the first source/drain SD1 and the second source/drain SD2. In some embodiments, the metal silicide layer 108 has a portion buried in the substrate 100 and a portion above the substrate 100 . That is, the bottom end of the metal silicide layer 108 is buried in the substrate 100 , and the top end of the metal silicide layer 108 is located above the substrate 100 .

The dielectric layer 200 may be disposed on the substrate 100 and cover the first transistor T1 and the second transistor T2. The first conductive plug CP1 and the second conductive plug CP2 may be disposed in the dielectric layer 200 . In some embodiments, the first conductive plug CP1 and the second conductive plug CP2 may extend from the dielectric layer 200 into the substrate 100 .

Hereinafter, a semiconductor device 20 of another embodiment will be described with reference to FIGS. 9 and 10 . The semiconductor device 20 shown in FIGS. 9 and 10 is similar to the semiconductor device 10 shown in FIGS. 7 and 8 , and the main difference between the semiconductor device 10 and the semiconductor device 20 is that the first conductive plug CP11 and The second conductive plug CP22 has a portion buried in the substrate 100 and a portion not buried in the substrate 100 , and the first guard ring GR11 and the second guard ring GR22 have portions disposed under the isolation structures STI1 and STI2 and disposed adjacent to the substrate The surface of 100 is located between the isolation structures STI1 and STI2. The same or similar components are designated by the same or similar reference numerals, and the connection relationship, materials and manufacturing processes of other components have been described in detail above, so they will not be repeated hereinafter.

9 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 10 is a schematic top view of a semiconductor device according to another embodiment of the present invention. Fig. 9 is a schematic cross-sectional view taken along the line A-A' of Fig. 10 . For convenience of description, FIG. 10 only shows the first isolation structure STI1, the second isolation structure STI2, the first source/drain SD1, the second source/drain SD2, the first gate structure GS1, the first A schematic top view of the two-gate structure GS2, the first guard ring GR11, and the second guard ring GR22, so as to clearly understand the corresponding relationship of each component.

Referring to FIGS. 9 and 10 , the first guard ring GR11 may have a first portion P1 and a second portion P2. The depth of the first portion P1 in the second well region 104 may be greater than the depth of the second portion P2 in the second well region 104 . In some embodiments, the depth of the first portion P1 may be greater than the depth of the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 , and the depth of the second portion P2 may be smaller than the depth of the first isolation structure STI1 and the second isolation structure Depth of STI2 in substrate 100 . That is, the bottom end of the first part P1 may be disposed at a lower level than the bottom ends of the first isolation structure STI1 and the second isolation structure STI2, and the bottom end of the second part P2 may be disposed at a lower level than the first isolation structure The bottom ends of the STI1 and the second isolation structure STI2 are at a high level. In some embodiments, from a top view, the first part P1 and the second part P2 are respectively the right half ring and the left half ring of the first guard ring GR11, but the present invention is not limited to this, the first part P1 and The second part P2 can be adjusted according to design, and its shape and size can be the same or different from each other.

The first conductive plug CP11 may include a first portion P11 connected with the first portion P1 of the first guard ring GR11 and a second portion P12 connected with the second portion P2 of the first guard ring GR11. In other words, the bottom end of the first part P11 may be disposed at a lower level than the bottom end of the second part P12. In some embodiments, the first portion P11 may have a portion buried in the substrate 100 , while the second portion P12 is disposed on the substrate 100 without having a portion buried in the substrate 100 .

The second guard ring GR22 may have a third portion P3 and a fourth portion P4. The depth of the fourth portion P1 in the first well region 102 may be greater than the depth of the third portion P3 in the first well region 102 . In some embodiments, the depth of the fourth portion P4 may be greater than the depth of the first isolation structure STI1 and the second isolation structure STI2 in the substrate 100 , and the depth of the third portion P3 may be smaller than the depth of the first isolation structure STI1 and the second isolation structure STI1 The depth of the structure STI2 in the substrate 100 . That is to say, the bottom end of the third part P3 may be disposed at a higher level than the bottom ends of the first isolation structure STI1 and the second isolation structure STI2, and the bottom end of the fourth part P4 may be disposed at a higher level than the bottom end of the first isolation structure STI1 and the second isolation structure STI2 The bottom ends of the structure STI1 and the second isolation structure STI2 are at a low level.

The second conductive plug CP22 may include a first portion P21 connected with the third portion P3 of the second guard ring GR22 and a second portion P22 connected with the fourth portion P4 of the second guard ring GR11. In other words, the bottom end of the first portion P21 may be disposed at a higher level than the bottom end of the second portion P22. In some embodiments, the first portion P21 may be disposed on the substrate 100 without a portion buried in the substrate 100 , and the second portion P12 may have a portion buried in the substrate 100 .

Based on the above, the first conductive plug CP11 and the second conductive plug CP22 respectively have the first parts P11 and P22 embedded in the substrate 100 and the second parts P12 and P21 not embedded in the substrate 100 , so that the junction breakdown voltage can be maintained. . In some embodiments, the first portion P1 of the first guard ring GR11 and the third portion P3 of the second guard ring GR22 are adjacent to each other.

11 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention. The semiconductor device 30 shown in FIG. 11 is similar to the semiconductor device 10 shown in FIG. 7 , and the main difference between the semiconductor device 10 and the semiconductor device 30 is that the semiconductor device 30 shown in FIG. The structure of the device 30 in the region R1 is the same as that of the semiconductor device 10 shown in FIG. 7 , and details are not repeated here. In some embodiments, the region R1 may be a peripheral circuit region, but is not limited thereto. In some embodiments, region R2 may be an electrostatic discharge (ESD) region or other device region.

Referring to FIG. 11 , in the region R2 of the semiconductor device 30 , the guard ring GR3 having the first conductivity type may be located in the second well region 104 in the substrate 100 , and the depth of the guard ring GR3 in the substrate 100 may be smaller than that of the first conductivity type. A depth of the isolation STI1 and the second isolation structure STI2 in the substrate 100 . In other words, the bottom end of the guard ring GR3 may be disposed at a higher level than the bottom ends of the first isolation structure STI1 and the second isolation structure STI2. From this, it can be seen that the semiconductor device and the manufacturing method thereof of the above-mentioned embodiments have a flexible design margin, and the user can adjust the positions of the regions R1 and R2 according to the design.

To sum up, in the semiconductor device and the manufacturing method thereof of the above-mentioned embodiments, the resistance of the well region under the transistor is reduced by burying the conductive plug electrically connected to the guard ring in the substrate to prevent undesired Latch-up effect.

In addition, in the semiconductor device and the manufacturing method thereof of the above-mentioned embodiments, since the resistance of the first well region and the second well region is not reduced by adjusting the doping concentration of the first well region and the second well region, the resistance thereof can be reduced. The electric field between the source and drain is maintained.

In addition, the semiconductor device and the manufacturing method thereof of the above-mentioned embodiments can have a flexible design margin, which can be adjusted by the user according to the design.

10, 20, 30: Semiconductor devices 100: base 102: The first well area 104: The second well area 106: Groove 108: Metal silicide layer 200: Dielectric layer 202: The first opening 204: Second Opening BL: Barrier Layer CL: Conductive layer CP1, CP2, CP11, CP22: Conductive plugs GS1, GS2, GS3: Gate structure GE1, GE2, GE3: gate GD1, GD2, GD3: gate dielectric layer GR1, GR2, GR3, GR11, GR22: guard ring PR1, PR2: mask pattern P1, P2, P3, P4, P11, P12, P21, P22: Parts R1, R2: area SP1, SP2, SP3: Spacers STI1, STI2: isolation structure SD1, SD2, SD3: source/drain SDC1, SDC2, SDC3: source/drain contact plugs T1, T2: Transistor

1 to 7 are schematic cross-sectional views of a method for fabricating a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic top view of a semiconductor device according to an embodiment of the present invention. 9 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 10 is a schematic top view of a semiconductor device according to another embodiment of the present invention. 11 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

10: Semiconductor device

100: base

102: The first well area

104: The second well area

108: Metal silicide layer

200: Dielectric layer

BL: Barrier Layer

CL: Conductive layer

CP1, CP2: Conductive plug

GS1, GS2: gate structure

GE1, GE2: gate

GD1, GD2: gate dielectric layer

GR1, GR2: guard ring

SP1, SP2: Spacers

STI1, STI2: isolation structure

SD1, SD2: source/drain

SDC1, SDC2: source/drain contact plugs

T1, T2: Transistor

Claims (15)

A semiconductor device, comprising: a substrate having a first conductivity type and including a first well region and a second well region located in the first well region, the first well region having a second conductivity type different from the first conductivity type, so the second well region has the first conductivity type; The first transistor is disposed on the second well region, and includes: a first gate structure disposed on the second well region; and a first source/drain electrode having the second conductivity type and disposed in the second well regions on opposite sides of the first gate structure; A second transistor is disposed on the first well region and includes: a second gate structure disposed on the first well region; and a second source/drain electrode having the first conductivity type and disposed in the first well region on opposite sides of the second gate structure; a first guard ring having a first conductivity type and disposed in the second well region and surrounding the first transistor; a second guard ring having a second conductivity type and disposed in the first well region and surrounding the second transistor; a first conductive plug, disposed on the first guard ring and electrically connected to the first guard ring; and a second conductive plug, disposed on the second guard ring and electrically connected to the second guard ring, wherein at least one of the first conductive plug and the second conductive plug has a portion embedded in the substrate. The semiconductor device of claim 1, wherein the first guard ring has a first portion and a second portion, and the depth of the first portion in the second well region is greater than that of the second portion in the second well the depth of the area. The semiconductor device of claim 2, further comprising: a first isolation structure between the first source/drain and the first guard ring and between the second source/drain and the second guard ring; and a second isolation structure in the substrate with the first guard ring and the second guard ring located between the first isolation structure and the second isolation structure, wherein the depth of the first portion is greater than the depth of the first isolation structure and the second isolation structure in the substrate, and the depth of the second portion is smaller than the first isolation structure and the second isolation structure The depth of the structure in the substrate. The semiconductor device of claim 2, wherein the second guard ring has a third portion and a fourth portion, the depth of the fourth portion in the first well region is greater than that of the third portion in the first well region The depth of a well area. The semiconductor device according to claim 4, further comprising: a first isolation structure between the first source/drain and the first guard ring and between the second source/drain and the second guard ring; and a second isolation structure in the substrate with the first guard ring and the second guard ring located between the first isolation structure and the second isolation structure, wherein the depth of the fourth portion is greater than the depth of the first isolation structure and the second isolation structure in the substrate, and the depth of the third portion is smaller than the depth of the first isolation structure and the second isolation structure The depth of the isolation structure in the substrate. The semiconductor device of claim 4, wherein the second portion and the third portion are adjacent to each other. The semiconductor device according to claim 1, further comprising: a dielectric layer disposed on the substrate and covering the first transistor and the second transistor, wherein the first conductive plug and the second conductive plug are disposed in the dielectric layer . The semiconductor device according to claim 1, further comprising: A metal silicide layer is disposed on the first gate structure, the second gate structure, the first source/drain and the second source/drain. The semiconductor device of claim 1, wherein one of the first conductive plug and the second conductive plug has the portion buried in the substrate, the first conductive plug and The other one of the second conductive plugs is disposed on the substrate. A method of manufacturing a semiconductor device, comprising: forming a first isolation structure and a second isolation structure in a substrate having a first conductivity type, wherein the substrate includes a first well region having a second conductivity type and a second well region having the first conductivity type, and the second well area is configured in the first well area; forming a first gate structure on the second well region of the substrate; forming a second gate structure on the first well region of the substrate; forming a groove between the first isolation structure and the second isolation structure in at least one of the first well region and the second well region; performing a first doping process to form a second guard ring and a first source/drain electrode with the second conductivity type in the first well region and the second well region, respectively, wherein the first Two guard rings are arranged between the first isolation structure and the second isolation structure, and the first source/drain is arranged on opposite sides of the first gate structure; A second doping process is performed to form a second source/drain electrode and a first guard ring with the first conductivity type in the first well region and the second well region, respectively, wherein the first Two source/drain electrodes are disposed on opposite sides of the second gate structure, and the first guard ring is disposed between the first isolation structure and the second isolation structure; forming a dielectric layer covering the first gate structure and the second gate structure on the substrate, wherein the dielectric layer has exposed the first source/drain and the second gate a first opening of the source/drain and a second opening exposing the first guard ring and the second guard ring, and the position of the second opening corresponds to the position of the trench; and Filling conductive material in the first opening and the second opening to form source/drain contact plugs on the first source/drain and the second source/drain, and A first conductive plug and a second conductive plug are respectively formed on the first guard ring and the second guard ring, wherein at least one of the first conductive plug and the second conductive plug has a portion embedded in the substrate. The method for manufacturing a semiconductor device according to claim 10, wherein the first doping process comprises the following steps: forming a mask pattern on the substrate, the mask pattern exposing the second well region between the first gate structure and the first isolation structure and the first isolation structure and the the first well region between the second isolation structures; implanting a dopant having the second conductivity type into the first well region and the second well region exposed by the mask pattern; and The mask pattern is removed. The method for manufacturing a semiconductor device according to claim 10, wherein the second doping process comprises the following steps: forming a mask pattern on the substrate, the mask pattern exposing the first well region and the first isolation structure and the first isolation structure between the second gate structure and the first isolation structure the second well region between second isolation structures; implanting a dopant having the first conductivity type into the first well region and the second well region exposed by the mask pattern; and The mask pattern is removed. The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming the groove comprises: Using the first isolation structure and the second isolation structure as a mask, removing the first well area and the second well area between the first isolation structure and the second isolation structure at least one of. The method for manufacturing a semiconductor device according to claim 10, wherein the groove, the first isolation structure and the second isolation structure are simultaneously formed by the following steps: forming isolation structures in the substrate; and The isolation structure is patterned to form the first isolation structure, the second isolation structure, and the groove between the first isolation structure and the second isolation structure. The method for manufacturing a semiconductor device according to claim 10, further comprising: Before forming the dielectric layer, the first gate structure, the second gate structure, the first source/drain, the second source/drain, the first A metal silicide layer is formed on the guard ring and the second guard ring.

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