TW201830697A - Semiconductor substrate structures and methods for forming the same and semiconductor devices - Google Patents

Abstract

A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.

Description

 Semiconductor substrate structure, method of forming same and semiconductor device  

This invention relates to semiconductor technology, and more particularly to semiconductor substrate structures for semiconductor devices and methods of forming the same.

In the semiconductor industry, a silicon-on-insulator (SOI) substrate is a silicon-insulator-silicon substrate that can replace a conventional germanium substrate, including a buried oxide layer. Between the bottom layer and the top layer. The advantages of the overlying insulation coating technology over conventional bulk crucible substrates include lower leakage current, higher power efficiency, lower parasitic capacitance, and resistance to latch-up.

However, in general, the overlying insulating layer device suffers from the problem of a backside bias effect, which is also referred to as a substrate bias effect. The backside biasing effect occurs when the breakdown voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) is affected by the voltage applied to the handling wafer. To minimize the effects of the backside biasing effect, the designer adds additional circuitry.

Although the insulating layer on the insulating layer of the semiconductor device and the forming method thereof are sufficient for their intended use, they are not completely satisfactory in all respects, and therefore, the insulating layer of the semiconductor device is covered. There are still some problems in the technical aspects of the substrate that need to be improved.

The present invention provides an embodiment of a semiconductor substrate structure of a semiconductor device and a method of forming the same. The backside bias effect changes the breakdown voltage of a metal-oxide-semiconductor field effect transistor (MOSFET), which is one of the major problems with semiconductor devices having a germanium-on-insulator substrate. In order to overcome the foregoing problems, the embodiment of the present invention implants an N-type buried layer and a P-type buried layer in the overlying substrate on the insulating layer, so that an additional mask can be formed in the overall process of the semiconductor device. In the case of other additional circuits, the backside biasing effect can be eliminated.

According to some embodiments, a semiconductor substrate structure is provided. The semiconductor substrate structure comprises a substrate having a first conductivity type. The semiconductor substrate structure also includes an oxide layer disposed on the substrate. The semiconductor substrate structure further includes a semiconductor layer disposed on the oxide layer. In addition, the semiconductor substrate structure further includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type; and a second disposed in the semiconductor layer and above the first buried layer A buried layer having a first conductivity type, wherein the first buried layer is spaced apart from the second buried layer by a distance.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. The semiconductor device also includes an oxide layer disposed on the substrate. The semiconductor device further includes a semiconductor layer disposed on the oxide layer. Further, the semiconductor device includes a first buried layer disposed within the semiconductor layer having a second conductivity type opposite to the first conductivity type. The semiconductor device further includes a second buried layer disposed within the semiconductor layer and over the first buried layer, having a first conductivity type, wherein the first buried layer is spaced apart from the second buried layer by a distance. The semiconductor device further includes a source electrode and a drain electrode disposed above the semiconductor layer, and a gate structure disposed above the semiconductor layer and between the source electrode and the drain electrode.

According to some embodiments, a method of forming a semiconductor substrate structure is provided. The method includes providing a substrate having a first conductivity type, forming an oxide layer on the substrate, and forming a semiconductor layer on the oxide layer. Moreover, the method further includes forming a first buried layer in the semiconductor layer, wherein the first buried layer has a second conductivity type opposite to the first conductivity type; and forming a first layer within the semiconductor layer and over the first buried layer A buried layer, wherein the second buried layer has a first conductivity type, and the first buried layer and the second buried layer are separated by a distance.

100a, 100c‧‧‧ semiconductor base structure

100b‧‧‧Semiconductor device

101‧‧‧Base

103‧‧‧Oxide layer

105‧‧‧Semiconductor layer

107‧‧‧First buried layer

109‧‧‧Second buried layer

111‧‧‧Elevation layer

113a, 113b‧‧‧ isolation structure

115‧‧‧First Well Area

117‧‧‧Second well area

121‧‧‧First doped area

123‧‧‧Second doped area

125‧‧‧ Third doped area

127‧‧‧Interlayer dielectric layer

129‧‧‧汲electrode

129a, 131a, 131b‧‧‧ perforation

131‧‧‧Source electrode

The views of the embodiments of the present invention can be further understood by the following detailed description in conjunction with the accompanying drawings. It is worth noting that various features may not be drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1A-1B is a cross-sectional view showing an exemplary continuous process for forming a semiconductor substrate structure in accordance with some embodiments of the present invention.

2A-2F are cross-sectional schematic views illustrating an exemplary continuous process for forming a semiconductor device in accordance with some embodiments of the present invention.

Fig. 3 is a schematic cross-sectional view showing a semiconductor device in accordance with another embodiment of the present invention.

The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, reference to a first element formed above a second element in the description may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements. An embodiment that makes the first and second components not in direct contact. Furthermore, embodiments of the invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to refer to the It will be appreciated that additional operations may be provided before, during and after the methods described below, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Embodiments for forming a semiconductor substrate structure are provided below. 1A-1B is a cross-sectional view illustrating an exemplary continuous process for forming a semiconductor substrate structure 100a, in accordance with some embodiments of the present invention.

According to some embodiments, as shown in FIG. 1A, an oxide layer 103 is formed on the substrate 101, and a semiconductor layer 105 is formed on the oxide layer 103. The substrate 101 may be made of tantalum or other semiconductor material, or the substrate 101 may comprise other elemental semiconductor materials such as germanium (Ge). In some embodiments, substrate 101 is made of a compound semiconductor, such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, substrate 101 is an N-type substrate. In other embodiments, substrate 101 is a P-type substrate.

In some embodiments, the structures of the substrate 101, the oxide layer 103, and the semiconductor layer 105 are formed by a process of separation by implantation of oxygen (SIMOX). In the process of oxygen ion implantation isolation, the oxygen ion beam is implanted into the germanium wafer with high energy. The implanted oxygen ions then react with the ruthenium and form an oxide layer 103 under the surface of the tantalum wafer by a high temperature annealing process. In this process, a portion of the germanium wafer under the oxide layer 103 is the substrate 101, and a portion of the germanium wafer above the oxide layer 103 is the semiconductor layer 105.

In other embodiments, the structures of the substrate 101, the oxide layer 103, and the semiconductor layer 105 are formed by a wafer bonding process, a seed method process, or other suitable process. In the wafer bonding process, the oxidized germanium is directly bonded to the semiconductor layer 105 to form the oxide layer 103 under the semiconductor layer 105, and then the semiconductor layer 105 is thinned before the oxide layer 103 and the semiconductor layer 105 are bonded to the substrate 101. . In the seeding process, the semiconductor layer 105 is epitaxially grown on the oxide layer 103 which has been formed on the substrate 101.

In some embodiments, the oxide layer 103 is made of hafnium oxide, and the thickness of the oxide layer 103 is in the range of about 0.3 μm to about 10 μm. In some embodiments, the semiconductor layer 105 is made of tantalum and may be doped with an N-type dopant or a P-type dopant. The thickness of the semiconductor layer 105 is in the range of about 1 μm to about 15 μm.

According to some embodiments, as shown in FIG. 1B, a first buried layer 107 is formed in the semiconductor layer 105, and a second buried layer 109 is formed in the semiconductor layer 105 and on the first buried layer 107. Once the second buried layer 109 is formed, the formation of the semiconductor base structure 100a is completed, and the first buried layer 107 and the second buried layer 109 are separated by a distance. In some embodiments, the first buried layer 107 has a conductivity type opposite to the substrate 101, and the second buried layer 109 has the same conductivity type as the substrate 101.

In some embodiments, the conductivity type of the substrate 101 is N-type, the conductivity type of the semiconductor layer 105 is P-type, and the first buried layer 107 is formed by a first ion implantation process using a P-type dopant, and the first The second buried layer 109 is formed by a second ion implantation process using an N-type dopant. In other embodiments, the conductivity type of the substrate 101 is P-type, the conductivity type of the semiconductor layer 105 is P-type, and the first buried layer 107 is formed by a first ion implantation process using an N-type dopant. The second buried layer 109 is formed by a second ion implantation process using a P-type dopant. In some embodiments, a mask is used to implement the first ion implantation process and the second ion implantation process. In other embodiments, the implementation of the first ion implantation process and the second ion implantation process may form a continuous first buried layer 107 and a second buried layer 109 in the substrate 101 without using a mask.

In some embodiments, the dopant concentration of the first buried layer 107 and the dopant concentration of the second buried layer 109 are between about 10 ¹⁵ atoms/cm ³ to about 10 ¹⁷ atoms/cm 3 (atom). Within the range of /cm ³ ). The dopant concentration of the first buried layer 107 and the second buried layer 109 may affect the thicknesses of the first buried layer 107 and the second buried layer 109, and the first buried layer 107 and the second buried layer 109 The dopant concentration may also affect the distance between the first buried layer 107 and the second buried layer 109.

Additionally, some embodiments of forming a semiconductor device are provided below. 2A-2F are cross-sectional views illustrating an exemplary continuous process for forming a semiconductor device 100b, in accordance with some embodiments of the present invention.

According to some embodiments, as shown in FIG. 2A, which is connected to FIG. 1B, an epitaxial layer 111 is formed on the semiconductor substrate structure 100a. In some embodiments, the epitaxial layer 111 is made of tantalum. In some embodiments, the epitaxial layer 111 is formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or a combination thereof.

In some embodiments, the epitaxial layer 111 can be doped with an N-type dopant or a P-type dopant. In some embodiments, the conductivity type of the substrate 101 is N-type, the conductivity type of the semiconductor layer 105 is P-type, the conductivity type of the first buried layer 107 is P-type, and the conductivity type of the second buried layer 109 is N-type. And the conductivity type of the epitaxial layer 111 is P type. In some embodiments, the thickness of the epitaxial layer 111 ranges from about 2 [mu]m to about 15 [mu]m.

According to some embodiments, as shown in FIG. 2B, isolation structures 113a and 113b are formed on the epitaxial layer 111. Specifically, one of the isolation structures 113a and 113b is partially embedded in the epitaxial layer 111, and another portion of the isolation structures 113a and 113b is formed on the epitaxial layer 111. In some embodiments, the isolation structures 113a and 113b may be formed using a local oxidation of silicon (LOCOS) isolation technique or a shallow trench isolation (STI) technique. In some embodiments, the isolation structures 113a and 113b are formed of hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable dielectric materials.

According to some embodiments, as shown in FIG. 2C, a first well region 115 is formed within the epitaxial layer 111, and a second well region 117 adjacent to the first well region 115 is formed within the epitaxial layer 111. In addition, a portion of the first well region 115 is formed under the isolation structure 113a, and a second well region 117 is disposed between the isolation structures 113a and 113b.

In some embodiments, the first well region 115 and the second well region 117 are separately formed by two separate ion implantation processes. In the case of an N-type metal-oxide-semiconductor field effect transistor (NMOS), the first well region 115 is a high-voltage n-well (HVNW), and the second well region 117 is a P-type. well. In the case of a P-type metal-oxide-semiconductor field effect transistor (PMOS), the first well region 115 is a high-voltage p-well (HVPW), and the second well region 117 is an N-type. well.

In the embodiment of the NMOS, as shown in FIG. 2C, since the conductivity type of the first well region 115 is the same as the conductivity type of the second buried layer 109, the first well region 115 and the second buried layer 109 as the HVNW. Contact, and the second well region 117 is separated from the second buried layer 109 by the epitaxial layer 111.

According to some embodiments, as shown in FIG. 2D, a gate structure 119 is formed over the epitaxial layer 111 and a portion of the isolation structure 113a. The gate structure 119 covers a portion of the first well region 115 and a portion of the second well region 117. . In some embodiments, the gate structure 119 can comprise a single or multiple layers of gate dielectric layers, as well as single or multiple layers of gate electrode layers.

The gate dielectric layer can be made of tantalum oxide, tantalum nitride, hafnium oxynitride, a dielectric material having a low dielectric constant (low-k), or a combination thereof. In some embodiments, the gate dielectric layer is formed by a plasma enhanced chemical vapor deposition (PECVD) process or a spin coating process.

The gate electrode layer is made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable material. In some embodiments, the gate electrode layer is formed by a deposition process and a patterning process. The deposition process can be a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a high-density plasma chemical vapor deposition process. (high density plasma chemical vapor deposition (HDPCVD) process, metal organic chemical vapor deposition (MOCVD) process, plasma enhanced chemical vapor deposition (PECVD) process or a combination of the foregoing.

According to some embodiments, as shown in FIG. 2E, a first doped region 121 is formed in the first well region 115, and a second doped region 123 and a third doped region 125 are formed in the second well region 117. Further, the third doping region 125 is adjacent to the second doping region 123. In some embodiments, the first doping region 121 has the same conductivity type as the first well region 115, the second doping region 123 has a different conductivity type than the second well region 117, and the third doping region 125 has a conductivity type and The second well zone 117 is the same.

According to some embodiments, as shown in FIG. 2F, an inter-layer dielectric (ILD) layer 127 is formed on the epitaxial layer 111, the isolation structures 113a and 113b, and the gate structure 119. In some embodiments, the interlayer dielectric layer 127 is made of yttrium oxide, tantalum nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other suitable media. Formed by electrical materials. The interlayer dielectric layer 127 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable process.

According to some embodiments, as shown in FIG. 2F, after the interlayer dielectric layer 127 is formed, the source electrode 131 and the drain electrode 129 are formed on the interlayer dielectric layer 127. Further, vias 129a, 131a, and 131b are formed in the interlayer dielectric layer 127. The drain electrode 129 is electrically connected to the first doped region 121 through the via 129a, and the source electrode 131 is electrically connected to the second doped region 123 and the third doped region 125 through the vias 131a and 131b. In some embodiments, source electrode 131, drain electrode 129, and vias 129a, 131a, and 131b can comprise polysilicon, metal, or other suitable electrically conductive material.

In some embodiments, the first doping region 121 is electrically connected to the drain electrode 129, and the second doping region 123 and the third doping region 125 are electrically connected to the source electrode 131. In some embodiments, the gate structure 119 is disposed between the source electrode 131 and the drain electrode 129 and is closer to the source electrode 131 than the gate electrode 119 of the gate electrode 129. After the source electrode 131 and the drain electrode 129 are formed, the formation of the semiconductor device 100b is completed.

Further, the semiconductor device 100c of the other embodiment is provided below. FIG. 3 is a cross-sectional view showing a PMOS semiconductor device 100c according to another embodiment of the present invention.

In this embodiment of the PMOS, the conductivity type of the substrate 101 is N-type, the conductivity type of the first buried layer 107 is P-type, and the conductivity type of the second buried layer 109 is N-type. The first well region 115 is a high pressure P-type well (HVPW) and the second well region 117 is an N-type well. The conductivity type of the first doping region 121 is P-type, the conductivity type of the second doping region 123 is P-type, and the conductivity type of the third doping region 125 is N-type.

Furthermore, as shown in FIG. 3, the first well region 115 and the second well region 117 are separated from the second buried layer 109 by the epitaxial layer 111. Since the conductivity type of the first well region 115 is P-type, which is different from the conductivity type of the second buried layer 109, the first well region 115 is separated from the second buried layer 109 by the epitaxial layer 111.

Conventionally, when a bias voltage is applied, the charge may collect on the top surface of the oxide layer of the SOI substrate on the insulating layer, so that the device cannot be fully depleted, which will reduce the breakdown voltage and generate backside bias. Pressure effect. In order to overcome the aforementioned problems of a semiconductor device having a silicon-on-insulator (SOI) substrate, some embodiments of the present invention implant an N-type buried layer and a P-type buried in a semiconductor layer overlying the underlying insulating substrate. The layer can be used to improve the breakdown voltage and eliminate the backside bias effect in the overall process of the semiconductor device without using additional implants or additional masks to form other circuits.

Furthermore, some embodiments of the present invention may use an N-type substrate 101 or a P-type substrate 101. The conductivity type of the first buried layer 107 needs to be opposite to that of the substrate 101, and the conductivity type of the second buried layer 109 is required. The same type of conductivity as the substrate 101.

The components of the several embodiments are outlined above so that those skilled in the art can understand the embodiments of the invention. It will be appreciated by those of ordinary skill in the art that the present invention can be practiced or modified in other embodiments and/or structures in accordance with the embodiments of the present invention. It is also to be understood by those of ordinary skill in the art that the present invention is not to be construed as Various changes, substitutions and substitutions.

Claims (15)

 A semiconductor substrate structure comprising: a substrate having a first conductivity type; an oxide layer disposed on the substrate; a semiconductor layer disposed on the oxide layer; and a first buried layer disposed on the semiconductor layer a second conductivity type opposite to the first conductivity type; and a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the The first buried layer is spaced apart from the second buried layer by a distance.    The semiconductor substrate structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.    The semiconductor substrate structure of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.    A semiconductor device comprising: a substrate having a first conductivity type; an oxide layer disposed on the substrate; a semiconductor layer disposed on the oxide layer; and a first buried layer disposed in the semiconductor layer Having a second conductivity type opposite to the first conductivity type; a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first The buried layer is spaced apart from the second buried layer; a source electrode and a drain electrode are disposed on the semiconductor layer; and a gate structure is disposed on the semiconductor layer and located at the source Between the electrode and the drain electrode.    The semiconductor device of claim 4, wherein the first conductivity type is n-type and the second conductivity type is p-type.    The semiconductor device of claim 4, wherein the first conductivity type is p-type and the second conductivity type is n-type.    The semiconductor device of claim 4, wherein the gate structure is closer to the source electrode than to the drain electrode.    The semiconductor device of claim 4, further comprising: an epitaxial layer disposed on the semiconductor layer; a first well region disposed in the epitaxial layer; and a second well region disposed on In the epitaxial layer, adjacent to the first well region; and an isolation structure covering a portion of the first well region; wherein the gate structure is disposed on a portion of the isolation structure and covers a portion of the first The well area and a portion of the second well area.    The semiconductor device of claim 8, wherein the first well region has the first conductivity type and contacts the second buried layer, and the second well region has the second conductivity type and The epitaxial layer is spaced apart from the second buried layer.    The semiconductor device of claim 9, further comprising: a first doped region disposed in the first well region and having the first conductivity type; and a second doped region disposed on the first In the second well region, having the first conductivity type; and a third doping region disposed in the second well region, having the second conductivity type and adjacent to the second doping region; wherein the first doping region The impurity region is electrically connected to the drain electrode, and the second doped region and the third doped region are electrically connected to the source electrode.    The semiconductor device of claim 10, wherein a dopant concentration of the first doped region is greater than a dopant concentration of the first well region, and a dopant concentration of the second doped region and the third The doping concentration of the doped region is greater than the doping concentration of the second well region.    The semiconductor device of claim 8, wherein the first well region has the second conductivity type, the second well region has the first conductivity type, and the first well region and the second well region The epitaxial layer is separated from the second buried layer.    The semiconductor device of claim 12, further comprising: a first doped region disposed in the first well region and having the second conductivity type; and a second doped region disposed on the first a second conductivity type in the second well region; and a third doping region disposed in the second well region, having the first conductivity type and adjacent to the second doping region; wherein the first doping region The impurity region is electrically connected to the drain electrode, and the second doped region and the third doped region are electrically connected to the source electrode.    A method for forming a semiconductor substrate structure, comprising: providing a substrate having a first conductivity type; forming an oxide layer on the substrate; forming a semiconductor layer on the oxide layer; forming a first buried layer thereon In the semiconductor layer, wherein the first buried layer has a second conductivity type opposite to the first conductivity type; and a second buried layer is formed in the semiconductor layer and above the first buried layer, wherein The second buried layer has the first conductivity type, and the first buried layer and the second buried layer are separated by a distance.    The method for forming a semiconductor substrate structure according to claim 14, wherein the first buried layer is formed by a first ion implantation process, and the second buried layer is formed by a second ion implantation process. .