TWI624002B - Semiconductor devices and methods for forming the same - Google Patents

Abstract

The semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed within the semiconductor substrate, wherein the first well region has a second conductivity type opposite the first conductivity type. The semiconductor device also includes a buried layer disposed within the semiconductor substrate and under the first well region, wherein the buried layer has a first conductivity type and contacts the first well region. The semiconductor device further includes a source electrode, a drain electrode, and a gate structure disposed on the semiconductor substrate, wherein the gate structure is between the source electrode and the drain electrode.

Description

Semiconductor device and method of forming same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a buried layer and a method of forming the same.

In the semiconductor industry, ultra high voltage (UHV) components are typically provided by well regions and top layers having two opposite conductivity types in a drift region, such as deep high voltage n-type wells (deep high voltage n -well, DHVNW) and a P-type top layer located in the deep high-pressure N-type well near the top surface of the component, so that the carriers of the opposite conductivity type maintain electrical balance, which makes the ultra-high voltage component easy to achieve complete depletion, and the lifting component collapses. Voltage, as well as reduced on-resistance.

However, in the non-epitaxial semiconductor process, the formation of deep high pressure wells requires diffusion and drive in (D/I) at high temperatures, so that the carrier concentration cannot be evenly distributed, and the high concentration of carriers will Focus on the top surface of the semiconductor substrate. In order to make the carrier concentration distribution uniform to easily achieve complete depletion, it is necessary to increase the carrier concentration of the top layer in the deep high pressure well, but the on-resistance of the ultrahigh voltage element will be improved. In addition, since the carrier concentration of the deep high pressure well is concentrated at the top, the carrier is easily injected into the field oxide layer due to the high electric field, so that the reliability of the element is affected.

Although currently existing semiconductor devices and their formation methods are sufficient for their intended use, they are not fully compliant in all respects, and therefore, the technology for regulating the carrier concentration of the drift region of the semiconductor device is still There are some issues that need improvement.

The present invention provides an embodiment of a semiconductor device and a method of forming the same. In order to reduce the surface electric field of the semiconductor device, so that the semiconductor device is easily completely depleted, embodiments of the present invention provide a semiconductor substrate having a first conductivity type in which a first well region, ie, a deep high pressure well, a first well region is disposed Having a second conductivity type opposite to the first conductivity type, by providing a buried layer having a first conductivity type under the first well region to reduce the first top layer having the first conductivity type in the first well region The carrier doping concentration disperses the carrier concentration of the first conductivity type at the top of the semiconductor substrate to the bottom of the semiconductor substrate, so that the carrier concentration of the first well region near the top surface of the semiconductor substrate is not limited only by A first top layer of the opposite conductivity type is balanced to reduce the on-resistance of the semiconductor device.

In addition, by providing a buried layer of opposite conductivity type in a deep high pressure well, the carrier concentration of the deep high pressure well is not concentrated at the top, which can effectively reduce the probability of the carrier implanting the field oxide layer, thereby improving the reliability of the semiconductor device. .

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed within the semiconductor substrate, wherein the first well region has a second conductivity type opposite the first conductivity type. The semiconductor device also includes a buried layer disposed within the semiconductor substrate and under the first well region, wherein the buried layer has a first conductivity type, and the buried layer contacts A well area. The semiconductor device further includes a source electrode, a drain electrode, and a gate structure disposed on the semiconductor substrate, wherein the gate structure is between the source electrode and the drain electrode.

According to some embodiments, a method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate having a first conductivity type, forming a first well region within the semiconductor substrate, wherein the first well region has a second conductivity type opposite the first conductivity type. The method also includes forming a buried layer within the semiconductor substrate and under the first well region, wherein the buried layer has a first conductivity type and the buried layer contacts the first well region. The method further includes forming a source electrode, a drain electrode, and a gate structure on the semiconductor substrate, wherein the gate structure is between the source electrode and the drain electrode.

100‧‧‧Semiconductor device

101‧‧‧Semiconductor substrate

103‧‧‧ patterned photoresist layer

105‧‧‧ buried layer

107a, 107b‧‧‧Isolation structure

109‧‧‧First Well Area

111‧‧‧Second well area

113‧‧‧ first top

115‧‧‧ second top

117‧‧‧ gate structure

119‧‧‧First doped area

121‧‧‧Second doped area

123‧‧‧ Third doped area

125‧‧‧Interlayer dielectric layer

127‧‧‧ source electrode

127a, 127b, 129a‧‧ ‧ guide holes

129‧‧‧汲electrode

D‧‧‧Deep

The views of the embodiments of the present invention can be more fully understood from the following detailed description. It is worth noting that various features in the drawings may not be drawn to scale according to standard practice in the industry. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1-7 are schematic cross-sectional views showing different stages of forming a semiconductor device, in accordance with some embodiments of the present invention.

The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, a reference to a first element formed above the second element in the description may include direct contact between the first and second elements. Embodiments may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, embodiments of the invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to refer to the It will be appreciated that additional operations may be provided before, during and after the methods described below, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Some embodiments of the present invention provide methods of forming a semiconductor device. 1-7 are schematic cross-sectional views showing different stages of forming a semiconductor device 100, in accordance with some embodiments of the present invention.

According to some embodiments, as shown in FIG. 1, a semiconductor substrate 101 having a first conductivity type is provided. The semiconductor substrate 101 may be made of germanium or other semiconductor material, or the semiconductor substrate 101 may comprise other elemental semiconductor materials such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. The first conductivity type of this embodiment is a P-type, and thus the semiconductor substrate 101 is a lightly doped P-type substrate. In other embodiments, the first conductivity type can be N-type, and thus the semiconductor substrate 101 is a lightly doped N-type substrate.

Following the foregoing, as shown in FIG. 1, the patterned photoresist layer 103 is selectively formed on the semiconductor substrate 101. Not covering the patterned photoresist layer 103 The region is a region where the buried layer and the first well region are subsequently formed, and the region covering the patterned photoresist layer 103 is a region where the second well region is subsequently formed. In other embodiments, the patterned photoresist layer 103 may not be formed, and in a subsequent process, the buried layer is formed entirely within the semiconductor substrate 101.

According to some embodiments, as shown in FIG. 2, the patterned photoresist layer 103 is used as a mask, and the buried layer 105 having the first conductivity type is formed in the semiconductor substrate 101 by the ion implantation process and the high temperature diffusion process. . In the present embodiment, the semiconductor substrate 101 is a P-type substrate, and the buried layer 105 is formed by implanting a P-type dopant such as boron (B) in the semiconductor substrate 101. In other embodiments, the semiconductor substrate 101 is an N-type substrate, and the buried layer 105 is formed by implanting an N-type dopant such as phosphorus (P) or arsenic (As) into the semiconductor substrate 101. Moreover, in some embodiments, the dopant concentration of the buried layer 105 ranges from about 1 x 10 ¹⁴ atoms/cm ³ to about 1 x 10 ¹⁵ atoms/cm ³ and is embedded. The depth D of layer 105 is in the range of from about 5 [mu]m to about 15 [mu]m.

Next, as shown in FIG. 3, the patterned photoresist layer 103 is removed, and isolation structures 107a and 107b are formed on the semiconductor substrate 101. In some embodiments, one of the isolation structures 107a and 107b is partially embedded in the semiconductor substrate 101, and another portion of the isolation structures 107a and 107b is formed over the semiconductor substrate 101.

In some embodiments, the isolation structures 107a and 107b can be formed using a local oxidation of silicon (LOCOS) isolation technique. In other embodiments, the isolation structures 107a and 107b can be shallow trench isolation (STI) structures. In some embodiments, the isolation junction The structures 107a and 107b are formed of hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable dielectric materials.

According to some embodiments, as shown in FIG. 4, a first well region 109 is formed in the semiconductor substrate 101 and on the buried layer 105, the first well region 109 having a second conductivity type opposite to the first conductivity type. Following the foregoing, in the present embodiment, the first well region 109 is a deep high pressure N-type well, and the dopant concentration of the first well region 109 is between about 1 x 10 ¹⁵ atoms/cm ³ to about 5 x ^{10 15} atoms. /Cubic centimeters (atom/cm ³ ). It is worth noting that the first well region 109 is in contact with the buried layer 105. Since the first well region 109 and the buried layer 105 have opposite conductivity types, the interface between the first well region 109 and the buried layer 105 generates a PN. PN junction.

The first well region 109 can be formed by ion implantation. In the present embodiment, the first well region 109 and the buried layer 105 are separately formed by two independent ion implantation processes. In other embodiments, the first well region 109 and the buried layer 105 may be simultaneously formed by an ion implantation process of the same energy. For example, the buried layer 105 is formed by implanting boron (B), and the first well The region 109 is formed by implanting phosphorus (P) or arsenic (As). Since the boron (B) ions are small, boron (B) can be implanted into the semiconductor at a faster rate under the same ion implantation energy. Within the substrate 101, therefore, a P-type buried layer 105 can be formed under the N-type first well region 109.

Then, as shown in FIG. 4, a second well region 111 is formed in the semiconductor substrate 101 having the first conductivity type, the second well region 111 has a first conductivity type, and is adjacent to the first well region 109, the first well The depth of the zone 109 is deeper than the second well zone 111, so the first well zone 109 may be referred to as a deep high pressure well. Following the foregoing, in the present embodiment, the second well region 111 is a P-type well region, and the doping concentration of the second well region 111 is about 1×10 ¹⁶ atoms/cm ³ to about 9× ^{10 16} atoms/ Within the range of cubic centimeters (atom/cm ³ ). In some embodiments, the isolation structure 107a is on the first well region 109 and covers a portion of the first well region 109. The isolation structure 107b is on the second well region 111 and covers a portion of the second well region 111. In the present embodiment, the length of the buried layer 105 is at least approximately the same as the length of the first well region 109. In other embodiments in which the patterned photoresist layer 103 is not formed, the buried layer 105 extends below the second well region 111.

According to some embodiments, as shown in FIG. 5, a first top layer 113 and a second top layer 115 are formed in the first well region 109 near the top of the first well region 109. The first top layer 113 has a first conductivity type, the second top layer 115 is on the first top layer 113 and contacts the first top layer 113, and the second top layer 115 has a second conductivity type. In this embodiment, the first top layer 113 is P-type, the second top layer 115 is N-type, and the first top layer 113 and the second top layer 115 are completely disposed under the isolation structure 107a, that is, the isolation structure 107a is on the semiconductor substrate. The projection range on 101 completely covers the projection range of the first top layer 113 and the second top layer 115 on the semiconductor substrate 101.

It is noted that since the first top layer 113 and the first well region 109 have opposite conductivity types, the interface between the first top layer 113 and the first well region 109 creates a PN junction. Likewise, since the second top layer 115 and the first top layer 113 have opposite conductivity types, the interface between the second top layer 115 and the first top layer 113 also produces a PN junction. In some embodiments, a first doping concentration and a second top layer 113 of the top 115 are in the range of from about 1x10 ¹⁶ atoms / cm ^ (atom / cm ³⁾ to about 9x10 ¹⁶ atoms / cm ^ (atom / cm ³⁾ of And the dopant concentrations of the first top layer 113 and the second top layer 115 are about the same.

In general, the doping concentrations of the first top layer 113 and the second top layer 115 are greater than the dopant concentration of the first well region 109, and the dopant concentration of the first well region 109 is greater than the dopant concentration of the buried layer 105.

Moreover, in accordance with some embodiments of the present invention, the interface of the buried layer 105 and the first well region 109, the interface of the first well region 109 and the first top layer 113, and the interfaces of the first top layer 113 and the second top layer 115 are By uniformly disposing a plurality of PN junctions in the semiconductor substrate 101, the PN junction can reduce the reduced surface field (RESURF) multiple times, so that the semiconductor device can withstand higher voltages and easily achieve complete depletion. In turn, the on-resistance is lowered and the breakdown voltage is increased.

Following the foregoing, as shown in FIG. 5, a gate structure 117 is formed on the semiconductor substrate 101 and a portion of the isolation structure 107a, and the gate structure 117 covers a portion of the first well region 109 and a portion of the second well region 111. In some embodiments, the gate structure 117 may include a single or multiple gate dielectric layers (not shown), and a single or multiple gate electrode layer is disposed on the gate dielectric layer (not shown).

The gate dielectric layer can be made of tantalum oxide, tantalum nitride, hafnium oxynitride, a dielectric material having a high dielectric constant (low-k), or a combination thereof. In some embodiments, the gate dielectric layer is formed by a plasma enhanced chemical vapor deposition (PECVD) process or a spin coating process.

The gate electrode layer is made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), polysilicon or other suitable material. In some embodiments, the gate electrode layer is formed by a deposition process and a patterning process. to make. The deposition process can be a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a high-density plasma chemical vapor deposition process. (high density plasma CVD, HDPCVD) process, metal-organic CVD (MOCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, or a combination thereof.

According to some embodiments, as shown in FIG. 6, a first doped region 119 is formed in the first well region 109, and a second doped region 121 and a third doped region 123 are formed in the second well region 111. Further, the third doping region 123 is adjacent to the second doping region 121. In some embodiments, the first doping region 119 has the same conductivity type as the first well region 109, the second doping region 121 has a conductivity type opposite to the second well region 111, and the third doping region 123 has a conductivity type and The second well region 111 is the same. In this embodiment, the first doping region 119 is N-type, the second doping region 121 is N-type, the third doping region 123 is P-type, and the first doping region 119 and the second doping region 121 are The doping concentration of the third doping region 123 is in the range of about 1 x 10 ¹⁸ atoms/cm ³ to about 1 x 10 ¹⁹ atoms/cm ³ .

According to some embodiments, as shown in FIG. 7, an inter-layer dielectric (ILD) layer 125 is formed over the semiconductor substrate 101, the isolation structures 107a and 107b, and the gate structure 117. In some embodiments, the interlayer dielectric layer 125 is made of yttrium oxide, tantalum nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other suitable media. Formed by electrical materials. The interlayer dielectric layer 125 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable process.

According to some embodiments, as shown in FIG. 7, after forming the interlayer dielectric layer 125, a source electrode 127 and a drain electrode 129 are formed on the interlayer dielectric layer 125. Further, vias 127a, 127b, and 129a are formed in the interlayer dielectric layer 125. The gate electrode 129 is electrically connected to the first doping region 119 through the via hole 129a, and the source electrode 127 is electrically connected to the third doping region 123 and the second doping region 121 through the via holes 127a and 127b, respectively. In some embodiments, source electrode 127, drain electrode 129, and vias 127a, 127b, and 129a can comprise a metal or other suitable electrically conductive material.

In some embodiments, the gate structure 117 is disposed between the source electrode 127 and the drain electrode 129, and the gate structure 117 is closer to the source electrode 127 than the gate electrode 129. After the source electrode 127 and the drain electrode 129 are formed, the semiconductor device 100 is completed.

In order to reduce the surface electric field of the semiconductor device, so that the semiconductor device is easily completely depleted, embodiments of the present invention provide a semiconductor substrate having a first conductivity type in which a first well region, ie, a deep high pressure well, a first well region is disposed Having a second conductivity type opposite to the first conductivity type, by providing a buried layer having a first conductivity type under the first well region to reduce the first top layer having the first conductivity type in the first well region The carrier doping concentration disperses the carrier concentration of the first conductivity type at the top of the semiconductor substrate to the bottom of the semiconductor substrate, so that the carrier concentration of the first well region near the top surface of the semiconductor substrate is not limited only by A first top layer of the opposite conductivity type is balanced to reduce the on-resistance of the semiconductor device.

In addition, by providing a buried layer having an opposite conductivity type under the first well region, the carrier concentration of the first well region is not concentrated at the top, which can be effectively reduced. The probability of the carrier being implanted into the field oxide layer further increases the reliability of the semiconductor device.

The components of the several embodiments are outlined above so that those skilled in the art can understand the embodiments of the invention. It will be appreciated by those of ordinary skill in the art that the present invention can be practiced or modified in other embodiments and/or structures in accordance with the embodiments of the present invention. It is also to be understood by those of ordinary skill in the art that the present invention may be practiced without departing from the spirit and scope of the invention. Such changes, substitutions and substitutions.

Claims (12)

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type a first top layer disposed in the first well region and having the first conductivity type; a second top layer disposed in the first well region and completely on the first top layer, wherein the second layer The top layer has the second conductivity type and contacts the first top layer; a buried layer is disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type, and the buried layer a layer contacting the first well region; and a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is between the source electrode and the drain electrode; The doping concentration of the first top layer and the second top layer is greater than the dopant concentration of the first well region, and the dopant concentration of the first well region is greater than the dopant concentration of the buried layer. The semiconductor device of claim 1, wherein the gate structure is closer to the source electrode than to the drain electrode. The semiconductor device of claim 1, further comprising: a second well region disposed in the semiconductor substrate adjacent to the first well region, wherein the second well region has the first conductivity type ;as well as An isolation structure covering a portion of the first well region; wherein the gate structure is disposed on a portion of the isolation structure and covers a portion of the first well region and a portion of the second well region. The semiconductor device of claim 3, further comprising: a first doped region disposed in the first well region and having the second conductivity type; a second doped region disposed on the first a second conductivity type in the second well region; and a third doping region disposed in the second well region, having the first conductivity type and adjacent to the second doping region; wherein the first doping region The impurity region is electrically connected to the drain electrode, and the second doped region and the third doped region are electrically connected to the source electrode. The semiconductor device of claim 3, wherein the buried layer extends below the second well region. The semiconductor device of claim 3, wherein the first top layer and the second top layer are completely disposed under the isolation structure. A method of forming a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a first well region in the semiconductor substrate, wherein the first well region has a first opposite to the first conductivity type a second conductivity type; forming a first top layer in the first well region, the first top layer having the first conductivity type; forming a second top layer in the first well region and completely on the first top layer The second top layer has the second conductivity type, wherein the second top layer is connected Touching the first top layer; forming a buried layer in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type, and the buried layer contacts the first well region; Forming a source electrode and a gate electrode and a gate structure on the semiconductor substrate, wherein the gate structure is between the source electrode and the gate electrode; wherein the first top layer and the second top layer The dopant concentration is greater than the dopant concentration of the first well region, and the dopant concentration of the first well region is greater than the dopant concentration of the buried layer. The method of forming a semiconductor device according to claim 7, wherein the gate structure is closer to the source electrode than the distance from the gate electrode. The method for forming a semiconductor device according to claim 7, further comprising: forming a second well region in the semiconductor substrate, wherein the second well region is adjacent to the first well region, and the second well a region having the first conductivity type; and forming an isolation structure covering a portion of the first well region; wherein the gate structure is formed on a portion of the isolation structure and covering a portion of the first well region and a portion of the first Erjing District. The method for forming a semiconductor device according to claim 9 , further comprising: forming a first doped region in the first well region, the first doped region having the second conductivity type; Forming a second doped region in the second well region, the second doped region having the second conductivity type; and forming a third doped region in the second well region, the third doped region Having the first conductivity type, and the third doped region is adjacent to the second doped region; wherein the first doped region is electrically connected to the drain electrode, and the second doped region and the third doped region The impurity region is electrically connected to the source electrode. The method of forming a semiconductor device according to claim 9, wherein the buried layer extends below the second well region. The method of forming a semiconductor device according to claim 9, wherein the first top layer and the second top layer are completely formed under the isolation structure.