TW201730971A - High voltage semiconductor device and method for manufacturing the same - Google Patents

Abstract

A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type. A first doping region having a second conductivity type is in the semiconductor substrate. An epitaxial layer is formed on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer above the first doping region. Second and third doping regions having the second conductivity type and the same doping concentration are in the epitaxial layer on both opposite sides of the body region, respectively, so as to adjoin to the body region. Source and drain regions are in the body region and the second doping regions, respectively. A gate structure is on the epitaxial layer and covers a portion of a filed insulating layer between the source and drain regions. A method for manufacturing the high voltage semiconductor device is also disclosed.

Description

High voltage semiconductor device and method of manufacturing same

The present disclosure relates to a semiconductor technology, and more particularly to a high voltage semiconductor device that reduces or eliminates the body effect.

The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high voltage semiconductor devices, such as laterally diffused MOSFETs, are primarily used in component applications above or about 18V. The advantages of high-voltage semiconductor device technology are cost-effective and easy to be compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

FIG. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor (LDMOSFET). The N-type horizontal diffusion gold-oxygen field effect transistor 10 includes a P-type semiconductor substrate 100 and a P-type epitaxial layer 102 thereon. The P-type epitaxial layer 102 has a gate structure 116 and a field insulating layer 114 thereon. Furthermore, the P-type epitaxial layer 102 on both sides of the gate structure 116 is a P-type body region 106 and an N-type drift region 104, wherein the drift region 104 further extends to the underlying P-type semiconductor substrate 100. Inside. The base region 106 has a P-type contact region 108 and an adjacent N-type contact region 110 (both referred to as a source region), and the drift region 104 has an N-type contact region 112 (also referred to as a drain region). Furthermore, a source electrode 117 is electrically The gate electrode 119 is electrically connected to the N-type contact region 112; and the gate electrode 121 is electrically connected to the gate structure 116.

However, in the above-described N-type horizontal diffusion MOS field oxide 10, the source region is electrically connected to the underlying P-type semiconductor substrate 100 via the base region 106. Therefore, when the source region is coupled to an internal circuit or a resistor, a matrix effect is induced to change the threshold voltage of the transistor 10. As a result, the driving current of the transistor 10 decreases as the voltage applied to the source region increases, thereby lowering the performance of the transistor 10.

Therefore, it is necessary to find a high voltage semiconductor device and a method of fabricating the same that can solve or ameliorate the above problems.

An embodiment of the present disclosure provides a high voltage semiconductor device including: a semiconductor substrate having a first conductivity type; a first doped region having a second conductivity type, located in the semiconductor substrate; and an epitaxial layer formed on On the semiconductor substrate; a substrate region having a first conductivity type, located in the epitaxial layer on the first doped region; a second doped region having a second conductivity type and the same doping concentration and a third doping region The regions are respectively located in the epitaxial layers on opposite sides of the substrate region adjacent to the substrate region; a source region and a drain region are respectively located in the base region and the second doping region; and an insulating layer is located in the source region and the germanium region a second doping region between the polar regions; and a gate structure on the epitaxial layer and covering a portion of the field insulating layer.

Another embodiment of the present disclosure provides a method of fabricating a high voltage semiconductor device, including: providing a semiconductor substrate having a first conductivity type; forming a first doped region having a second conductivity type in the semiconductor substrate; Forming an epitaxial layer on the substrate; forming a substrate region having a first conductivity type and a second doping region and a third doping region having a second conductivity type and a same doping concentration in the epitaxial layer, wherein The base region is located on the first doped region, and the second doped region and the third doped region are respectively located on opposite sides of the base region and adjacent to the base region; a field insulating layer is formed in the second doped region; Forming a gate structure on the layer, wherein the gate structure covers a portion of the field insulating layer; and forming a source region in the substrate region and forming a drain region in the second doping region.

10‧‧‧Optoelectronics

20, 30, 40, 50, 60‧‧‧ high voltage semiconductor devices

100‧‧‧P type semiconductor substrate

102‧‧‧P type epitaxial layer

104‧‧‧N type drift zone

106‧‧‧basal area

108‧‧‧P type contact area

110, 112‧‧‧N type contact area

114, 220‧‧ ‧ field insulation

116, 233‧‧ ‧ gate structure

117‧‧‧ source electrode

119‧‧‧汲electrode

121‧‧‧gate electrode

200‧‧‧Semiconductor substrate

202‧‧‧First doped area

204‧‧‧buried layer

210‧‧‧ epitaxial layer

212‧‧‧High-pressure well area

212a‧‧‧Second doped area

212b‧‧‧ third doped area

216‧‧‧Field drop zone

222‧‧‧basal area

224, 226‧‧‧Doped area

227‧‧‧ source area

228‧‧‧Bungee Area

230‧‧‧ gate dielectric layer

232‧‧ ‧ gate layer

240, 242, 244‧‧‧ interconnected structures

250‧‧‧ Inner dielectric layer

E1, E2‧‧‧ outer edge

W‧‧‧Width

Fig. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor.

2A to 2F are cross-sectional views showing a method of manufacturing a high voltage semiconductor device according to an embodiment of the present disclosure.

3A to 3D are cross-sectional views showing a high voltage semiconductor device according to an embodiment of the present disclosure, respectively.

Hereinafter, a high voltage semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure will be described. However, the present invention is to be understood as being limited to the details of the invention and is not intended to limit the scope of the invention.

Embodiments of the present disclosure provide a high voltage semiconductor device, such as a laterally diffused gold oxide half field effect transistor, which utilizes a doped region of a conductivity type different from a base region to isolate a substrate region and a substrate having the same conductivity type in a high voltage semiconductor device, In turn, the matrix effect is reduced or eliminated.

Please refer to FIG. 2E, which illustrates an embodiment according to the present disclosure. A schematic cross-sectional view of the high voltage semiconductor device 20. In the present embodiment, the semiconductor device 20 can be a horizontal diffusion MOS field effect transistor. The high voltage semiconductor device 20 includes a semiconductor substrate 200, such as a germanium substrate, a germanium telluride (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, and a silicon on insulator. A SOI) substrate or other conventional semiconductor substrate having a first conductivity type.

Furthermore, the semiconductor substrate 200 has a first doped region 202 therein, such as a high voltage well region adjacent to the upper surface of the semiconductor substrate 200. The first doping region 202 has a second conductivity type different from the first conductivity type. For example, the first conductivity type is a P type, and the second conductivity type is an N type. In other embodiments, the first conductivity type may be an N type and the second conductivity type is a P type.

In the present embodiment, the high voltage semiconductor device 20 further includes an epitaxial layer 210 formed on the semiconductor substrate 200 and having a first conductivity type. The epitaxial layer 210 has a plurality of field insulating layers 220 as isolation structures. In an embodiment, the field insulating layer 220 can be a field oxide. In one example, the field insulating layer 220 is a local oxidation of silicon (LOCOS). In other embodiments, the field insulating layer 220 can be a shallow trench isolation (STI) structure.

In the present embodiment, the high voltage semiconductor device 20 further includes a base region 222 having a first conductivity type and a second doping region 212a and a third doping region 212b having a second conductivity type and the same doping concentration. The base region 222 is located in the epitaxial layer 210 on the first doped region 202, and the base region 222 extends from the upper surface of the epitaxial layer 210 to the lower surface thereof, so that the bottom of the base region 222 can be adjacent to the first doped region. 202. Furthermore, the second doping region 212a and the third doping region 212b are respectively located on the substrate The regions 222 are in opposite layers of the epitaxial layer 210 adjacent to the substrate region 222. In this embodiment, the second doping region 212a and the third doping region 212b are located above the first doping region 202, and extend from the upper surface of the epitaxial layer 210 to the lower surface thereof, so that the second doping region 212a The bottom of the third doping region 212b may be adjacent to the first doping region 202. In an embodiment, an outer edge E2 of the third doped region 212b is aligned with a corresponding outer edge E1 of the first doped region 202. Further, the third doping region 212b has a width W in the range of 1 to 8 μm.

In an embodiment, the first doping region 202 has the same doping concentration as the second doping region 212a and the third doping region 212b. In this case, the first doping region 202 and the second doping region 212a and the third doping region 212b are high voltage well regions. Furthermore, the second doping region 212a and the third doping region 212b are the same high-voltage well region 212 separated by the base region 222 or a high-voltage well region formed in the epitaxial layer 210. In one example, the doping concentration of the high pressure well region is in the range of about 1.0 x 10 ¹⁵ to 1.0 x 10 ¹⁶ ions/cm ³ . In other embodiments, the doping concentration of the first doping region 202 is different from the second doping region 212a and the third doping region 212b. In this case, the first doping region 202 is a high voltage well region, and the second doping region 212a and the third doping region 212b are well regions, and the well region (ie, the second doping region 212a and the third doping region) The impurity concentration of the impurity region 212b) is higher than that of the high voltage well region (ie, the first doping region 202). Furthermore, the second doping region 212a and the third doping region 212b are the same well regions separated by the base region 222 or well regions each formed in the epitaxial layer 210. In one example, the doping concentration of well region of a high pressure of about 1.0 × 10 ¹⁵ to 1.0 × 10 ¹⁶ ions / cm ³ and, while the doping concentration in the well region is approximately 1.0 × 10 ¹⁶ to 1.0 × 10 ¹⁷ ions / The range of cm ³ . In this embodiment, the first doping region 202, the second doping region 212a, and the third doping region 212b are used as a drift region of the horizontal diffusion MOS field effect transistor.

In the present embodiment, the high voltage semiconductor device 20 further includes a source region 227, a drain region 228, and a gate structure 233. The source region 227 and the drain region 228 are respectively located in the base region 222 and the second doping region 212a. The source region 227 is composed of a doped region 226 having a second conductivity type and a doped region 224 having a first conductivity type as a substrate contact region. Furthermore, the drain region 228 is composed only of doped regions having a second conductivity type. Moreover, the gate structure 233 is located on the epitaxial layer 210 and covers a portion of the field insulating layer 220. The field insulating layer 220 is formed in the second doping region 212a between the source region 227 and the drain region 228. . The gate structure 233 generally includes a gate dielectric layer 230 and a gate layer 232 over the gate dielectric layer 230.

In the present embodiment, the high voltage semiconductor device 20 may include a field reduction region 216 having a first conductivity type, which is located in the second doping region 212a and corresponds to the field insulating layer 220 under the gate structure 233. Below, to reduce the surface electric field. In one embodiment, the field drop region 216 has a doping concentration of about 1.0 x 10 ¹⁷ ions/cm ³ .

In the present embodiment, the high voltage semiconductor device 20 further includes an inner layer dielectric (ILD) layer 250 and a plurality of interconnect structures 240, 242 and 244 located therein. In this embodiment, the interconnect structure 240 is electrically connected to the source region 227 as a source electrode; the interconnect structure 242 is electrically connected to the drain region 216 as a drain electrode; and the interconnect structure 244 is electrically connected to the gate structure 233 to serve as a gate electrode.

Referring to FIGS. 3A and 3B, there are shown schematic cross-sectional views of high voltage semiconductor devices 30 and 40 according to other embodiments of the present invention, wherein components that are the same as those of FIG. 2F are given the same reference numerals and their description is omitted. In Figure 3A, high The piezoelectric semiconductor device 30 has a structure similar to that of the high voltage semiconductor device 20 (as shown in Fig. 2F). The difference is that the outer edge E2 of the third doping region 212b in the high voltage semiconductor device 30 is not aligned with the corresponding outer edge E1 of the first doping region 212a. For example, the outer edge E2 extends laterally beyond the outer edge E1.

In Fig. 3B, the high voltage semiconductor device 40 has a structure similar to that of the high voltage semiconductor device 20 (as shown in Fig. 2F). The difference is that the outer edge E2 of the third doped region 212b in the high voltage semiconductor device 40 is not aligned with the corresponding outer edge E1 of the first doped region 212a. For example, the outer edge E1 extends laterally beyond the outer edge E2.

Referring to FIG. 3C, a cross-sectional view of a high voltage semiconductor device 50 according to another embodiment of the present invention is illustrated, wherein components identical to those of FIG. 2F are given the same reference numerals and their description is omitted. In the present embodiment, the high voltage semiconductor device 50 has a structure similar to that of the high voltage semiconductor device 20 (as shown in Fig. 2F). The difference is that the high voltage semiconductor device 50 further includes a buried layer 204 having a second conductivity type, located in the first doping region 202 below the base region 222, so that the bottom of the base region 222 is adjacently buried. The upper surface of layer 204. Furthermore, the doping concentration of the buried layer 204 is about 1.0×10 ¹⁸ . In this embodiment, the second doping region 212a and the third doping region 212b may be a well region or a high voltage well region. In one example, the second conductivity type is N-type, and the buried layer 204 is an N type buried layer ^{(N + buried layer, NBL)} .

Referring to FIG. 3D, there is shown a cross-sectional view of a high voltage semiconductor device 60 according to another embodiment of the present invention, wherein components identical to those of FIG. 2F are given the same reference numerals and the description thereof is omitted. In the present embodiment, the high voltage semiconductor device 60 has a structure similar to that of the high voltage semiconductor device 20 (as shown in Fig. 2F). Do not The same applies to the use of a buried layer 204 having a second conductivity type in the high voltage semiconductor device 60 instead of the first doped region 202 in the high voltage semiconductor device 20 disposed under the base region 222, so that the bottom portion of the base region 222 is buried adjacently. The upper surface of layer 204. In this embodiment, the second doping region 212a and the third doping region 212b may be a well region or a high voltage well region.

Next, please refer to FIGS. 2A to 2F, which are schematic cross-sectional views showing a method of manufacturing the high voltage semiconductor device 20 according to an embodiment of the present disclosure. Referring to FIG. 2A, a semiconductor substrate 200 having a first conductivity type is provided. In the present embodiment, the semiconductor substrate 200 may be a germanium substrate, a germanium germanium germanium substrate, a bulk semiconductor substrate, a compound semiconductor substrate, an insulating layer overlying germanium substrate, or other conventional semiconductor substrates.

Next, a first doping region 202, such as a high voltage well region, adjacent to the upper surface of the semiconductor substrate 200 may be formed in the semiconductor substrate 200 by an ion implantation process and a thermal process. The first doping region 202 has a second conductivity type different from the first conductivity type. For example, the first conductivity type is a P type, and the second conductivity type is an N type. In other embodiments, the first conductivity type may be an N type and the second conductivity type is a P type.

Next, referring to FIG. 2B, an epitaxial layer 210 having a first conductivity type can be formed by epitaxial growth on the semiconductor substrate 200. Then, a doped region having a second conductivity type, such as a high voltage well region 212, is formed in the epitaxial layer 210 by an ion implantation process and a thermal process. In the present embodiment, the doping concentration of the high voltage well region 212 may be the same as the first doping region 202. For example, the doping concentration of the high voltage well region 212 and the first doping region 202 is in the range of about 1.0×10 ¹⁵ to 1.0×10 ¹⁶ ions/cm ³ . In other embodiments, the doped region having the second conductivity type may be a well region having a different doping concentration than the first doping region 202. For example, the doping concentration of the well region is in the range of about 1.0×10 ¹⁶ to 1.0×10 ¹⁷ ions/cm ³ , and the doping concentration of the first doping region 202 is about 1.0×10 ¹⁵ to 1.0×10 ^{16 .} The range of ions/cm ³ . That is, the doping concentration of the well region is higher than the doping concentration of the first doping region 202.

Next, referring to FIG. 2C, a plurality of field insulating layers 220 as isolation structures are formed in the epitaxial layer 210, wherein at least one field of the insulating layer is formed in the high voltage well region 212. In an embodiment, the field insulating layer 220 can be a field oxide. In one example, the field insulating layer 220 is a local tantalum oxide layer (LOCOS). In other embodiments, the field insulating layer 220 can be a shallow trench isolation (STI) structure. It should be noted that in other embodiments, a high-voltage well region 212 or a well region having a second conductivity type may be formed in the epitaxial layer 210 after the field insulating layer 220 is formed.

Next, referring to FIG. 2D, a substrate region 222 having a first conductivity type may be formed in the high-voltage well region 212 or the well region of the epitaxial layer 210 by an ion implantation process and a thermal process to place the high-voltage well region. The 212 or well region is divided into a second doped region 212a and a third doped region 212b having a second conductivity type and the same doping concentration. As shown in FIG. 2D, the base region 222 is located in the epitaxial layer 210 on the first doped region 202, and the base region 222 extends from the upper surface of the epitaxial layer 210 to the lower surface thereof, so that the bottom of the base region 222 can be Adjacent to the first doping region 202. Furthermore, the second doped region 212a and the third doped region 212b are respectively located in the epitaxial layer 210 on opposite sides of the base region 222 adjacent to the base region 222. In this embodiment, the second doping region 212a and the third doping region 212b are located above the first doping region 202, and extend from the upper surface of the epitaxial layer 210 to the lower surface thereof, so that the second doping region 212a The bottom of the third doping region 212b may be adjacent to the first doping region 202. In an embodiment, an outer edge E2 of the third doping region 212b is aligned with a corresponding one of the first doping regions 202. Outer edge E1. Further, the third doping region 212b has a width W in the range of 1 to 8 μm. In other embodiments, the second doped region 212a and the third doped region 212b may be formed by a respective ion implantation process before or after the formation of the base region 222.

Next, referring again to FIG. 2D, a field drop region 216 having a first conductivity type may be selectively formed in the second doping region 212a under the field insulating layer 220 to reduce the surface electric field. In one embodiment, the field drop region 216 has a doping concentration of about 1.0 x 10 ¹⁷ ions/cm ³ . Next, a gate structure 233 can be formed on the epitaxial layer 210 by using a conventional MOS process, wherein the gate structure 233 partially covers the field insulating layer 220 above the field drop region 216. The gate structure 233 generally includes a gate dielectric layer 230 and a gate layer 232 over the gate dielectric layer 230.

Next, referring to FIG. 2E, a source region 227 is formed in the base region 222 by the ion implantation process, and a drain region 228 is formed in the second doped region 212a. The source region 227 is composed of a doped region 226 having a second conductivity type and a doped region 224 having a first conductivity type as a substrate contact region. Furthermore, the drain region 228 is composed only of doped regions having a second conductivity type.

Next, referring to FIG. 2F, a metallization layer can be formed on the epitaxial layer 210 by using a conventional metallization process, and the gate structure 233 can be covered. As a result, the high voltage semiconductor device 20 is formed. In this embodiment, the metallization layer can include an inner dielectric (ILD) layer 250 and a plurality of interconnect structures 240, 242, and 244 located therein. In this embodiment, the interconnect structure 240 is electrically connected to the source region 227 as a source electrode; the interconnect structure 242 is electrically connected to the drain region 216 as a drain electrode; and the interconnect structure 244 is electrically connected to the gate structure 233 to serve as a gate electrode.

It is to be understood that the high voltage semiconductor devices 30, 40, 50, and 60 shown in Figs. 3A to 3D, respectively, can be fabricated by the same or similar methods as those shown in Figs. 2A to 2F.

According to the above embodiment, the opposite sides and the bottom of the base region form doped regions having a conductivity type different from the base region, and the doped regions constitute a continuous isolation structure to isolate the substrate having the same conductivity type in the high voltage semiconductor device. Area and base. Therefore, when the source region is coupled to an internal circuit or a resistor, the substrate effect can be reduced or eliminated to prevent the driving current from decreasing as the voltage applied to the source region increases, thereby improving or maintaining the performance of the high voltage semiconductor device. Furthermore, these doped regions can have the same doping concentration, thus enabling the high voltage semiconductor device to have a stable peak electric field. In addition, since a high-voltage well region in a high-voltage semiconductor device can be used to form a continuous isolation structure, no additional manufacturing cost is required.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

20‧‧‧High voltage semiconductor device

200‧‧‧Semiconductor substrate

202‧‧‧First doped area

210‧‧‧ epitaxial layer

212‧‧‧High-pressure well area

212a‧‧‧Second doped area

212b‧‧‧ third doped area

216‧‧‧Field drop zone

220‧‧ ‧ field insulation

222‧‧‧basal area

224, 226‧‧‧Doped area

227‧‧‧ source area

228‧‧‧Bungee Area

230‧‧‧ gate dielectric layer

232‧‧ ‧ gate layer

233‧‧ ‧ gate structure

240, 242, 244‧‧‧ interconnected structures

250‧‧‧ Inner dielectric layer

E1, E2‧‧‧ outer edge

W‧‧‧Width

Claims (26)

A high voltage semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first doped region having a second conductivity type, located in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a substrate region having the first conductivity type, located in the epitaxial layer on the first doped region; a second doped region having the second conductivity type and the same doping concentration and a third doping The regions are respectively located in the epitaxial layer on opposite sides of the substrate region adjacent to the substrate region; a source region and a drain region are respectively located in the substrate region and the second doping region; an insulating layer, The second doped region between the source region and the drain region; and a gate structure on the epitaxial layer and covering a portion of the field insulating layer. The high voltage semiconductor device according to claim 1, further comprising a field drop region having the first conductivity type, located in the second doping region below the field insulating layer. The high voltage semiconductor device of claim 1, wherein the first doped region has the same doping concentration as the second doped region or the third doped region. The high voltage semiconductor device of claim 3, wherein the first doped region, the second doped region, and the third doped region are high voltage well regions. The high voltage semiconductor device of claim 4, wherein the second doped region and the third doped region are the same high voltage well region separated by the base region. The high voltage semiconductor device of claim 1, wherein a doping concentration of the first doping region is different from a doping concentration of the second doping region or the third doping region. The high voltage semiconductor device according to claim 6, wherein the first doped region is a high voltage well region, and the second doped region and the third doped region are well regions, and the well region is doped The impurity concentration is higher than the high pressure well region. The high voltage semiconductor device according to claim 7, further comprising a buried layer having the second conductivity type, located in the first doping region below the substrate region. The high voltage semiconductor device of claim 6, wherein the first doped region is a buried layer having the second conductivity type, and the second doped region and the third doped region are wells Area. The high voltage semiconductor device of claim 6, wherein the first doped region is a buried layer having the second conductivity type, and the second doped region and the third doped region are high voltage Well area. The high voltage semiconductor device of claim 1, wherein the second doped region and the third doped region are located above the first doped region, and an outer edge of the third doped region is aligned And a corresponding outer edge of the first doped region. The high voltage semiconductor device of claim 1, wherein the second doped region and the third doped region are located above the first doped region, and the third An outer edge of the doped region is not aligned with a corresponding outer edge of the first doped region. The high voltage semiconductor device of claim 1, wherein the third doped region has a width in the range of 1 to 8 micrometers. A method of fabricating a high voltage semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a first doped region having a second conductivity type in the semiconductor substrate; forming a Lei on the semiconductor substrate a seed layer having a first conductive type and a second doped region and a third doped region having the second conductivity type and the same doping concentration, wherein the substrate is formed in the epitaxial layer a region is located on the first doped region, and the second doped region and the third doped region are respectively located on opposite sides of the base region and adjacent to the base region; forming a field insulation layer in the second doped region Forming a gate structure on the epitaxial layer, wherein the gate structure covers a portion of the field insulating layer; and forming a source region in the substrate region and forming a drain in the second doped region Polar zone. The method for manufacturing a high voltage semiconductor device according to claim 14, further comprising forming a field drop region having the first conductivity type in the second doping region below the field insulating layer. The method for manufacturing a high voltage semiconductor device according to claim 14, wherein the first doped region and the second doped region or the third doped region have Have the same doping concentration. The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the first doping region, the second doping region, and the third doping region are high voltage well regions. The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the second doped region and the third doped region are the same high voltage well region separated by the base region. The method of fabricating a high voltage semiconductor device according to claim 14, wherein a doping concentration of the first doping region is different from a doping concentration of the second doping region or the third doping region. The method of manufacturing a high voltage semiconductor device according to claim 19, wherein the first doped region is a high voltage well region, and the second doped region and the third doped region are well regions, and the well is The doping concentration of the zone is higher than the high pressure well zone. The method for manufacturing a high voltage semiconductor device according to claim 20, further comprising forming a buried layer having the second conductivity type in the first doping region, wherein the buried layer is located under the substrate region . The method of manufacturing a high voltage semiconductor device according to claim 19, wherein the first doped region is a buried layer having the second conductivity type, and the second doped region and the third doping region The area is a well area. The method of manufacturing a high voltage semiconductor device according to claim 19, wherein the first doped region is a buried layer having the second conductivity type, and the second doped region and the third doping region The area is a high pressure well area. The method of manufacturing a high voltage semiconductor device according to claim 14, wherein the second doped region and the third doped region are located in the first doped region Upper, and an outer edge of the third doped region is aligned with a corresponding outer edge of the first doped region. The method of manufacturing a high voltage semiconductor device according to claim 14, wherein the second doped region and the third doped region are located above the first doped region, and an outer side of the third doped region The edge is not aligned with a corresponding outer edge of the first doped region. The method of fabricating a high voltage semiconductor device according to claim 14, wherein the third doped region has a width in the range of 1 to 8 μm.