TWI575741B - High voltage semiconductor device and method for manufacturing the same - Google Patents

Description

High voltage semiconductor device and method of manufacturing same

The present disclosure relates to a semiconductor technology, and more particularly to a high voltage semiconductor device having good isolation capabilities.

The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high-voltage semiconductor devices, such as Double Diffused Drain MOSFET (DDDMOS) and Lateral diffused MOSFET (LDMOS), are mainly used for higher or higher than 18V. The field of component applications. The advantages of high-voltage semiconductor device technology are cost-effective and easy to be compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

The double-diffused bungee MOSFET has its small size and large output current and is widely used in source driver ICs with operating voltages less than 30V. The double diffused drain is formed by a two-valued region for a source or a drain of a high voltage MOS field effect transistor. The term "high-voltage gold-oxygen half-effect transistor" as used herein refers to a transistor having a high breakdown voltage.

Adjacent DDDMOS typically provides isolation through field oxides, such as trench isolation structures. Trench isolation structure and above The metallization layer (eg, the inner dielectric (ILD) layer and the interconnect wiring layer) and the well region below it form a parasitic MOS transistor. When the DDDMOS is operated, the voltage applied to the interconnected wiring layer easily turns on the parasitic MOS transistor, causing the trench isolation structure to lose the isolation failure and causing the circuit function to fail. Therefore, the trench isolation structure must increase the width and/or depth to prevent the parasitic MOS transistor from being turned on when the DDDMOS is operating.

However, increasing the width of the trench isolation structure increases the size of the device and increases the wafer area. In addition, increasing the depth of the trench isolation structure increases the difficulty of the process and the manufacturing cost. Therefore, it is necessary to find a high voltage semiconductor device and a method of fabricating the same that can solve or ameliorate the above problems.

An embodiment of the present disclosure provides a high voltage semiconductor device including: a semiconductor substrate having a well region of a first conductivity type and an isolation structure disposed within the well region, wherein a first surface is defined on each side of the isolation structure a first gate structure and a second gate structure are respectively disposed on the first zone and the second zone; a first planting zone and a second planting zone are respectively located at the first zone a zone and a second zone adjacent to the isolation structure, wherein the first planting zone and the second planting zone have a second conductivity type different from the first conductivity type; and a reverse planting zone located below the isolation structure The well region extends laterally below the first implant region and the second implant region, wherein the reverse implant region has a first conductivity type and has a doping concentration greater than a doping concentration of the well region.

Another embodiment of the present invention provides a method of fabricating a high voltage semiconductor device, comprising: providing a semiconductor substrate having a well region of a first conductivity type and an isolation structure disposed within the well region, wherein set Forming a first zone and a second zone; forming a reverse planting zone having a first conductivity type in the well zone below the isolation structure, wherein the reverse planting zone extends laterally in the first zone and the second zone, And having a doping concentration greater than a doping concentration of the well region; forming a first implanting region and a second implanting region adjacent to the isolation structure on the anti-planting regions of the first region and the second region, respectively The first implanting zone and the second implanting zone have a second conductivity type different from the first conductivity type; and forming a first gate structure and a second gate on the first zone and the second zone respectively structure.

10‧‧‧ implant mask

20‧‧‧First ion implantation

30‧‧‧Second ion implantation

100‧‧‧Semiconductor substrate

102‧‧‧ Well Area

102a‧‧‧First District

102b‧‧‧Second District

104‧‧‧Isolation structure

106‧‧‧Replanting area

Edges 106a, 106b, 108a, 110a‧‧

108‧‧‧First planting area

110‧‧‧Second planting area

112‧‧‧First gate structure

114‧‧‧Second gate structure

115‧‧‧ Inner dielectric layer

116‧‧‧ Third planting area

117, 119‧‧‧ source/drain electrodes

118‧‧‧The fourth planting area

121‧‧‧Internal conductor layer

200‧‧‧High voltage semiconductor device

W‧‧‧ surface width

1A to 1E are schematic cross-sectional views showing a method of manufacturing a high voltage semiconductor device according to an embodiment of the present disclosure.

Hereinafter, a high voltage semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure will be described. However, the present invention is to be understood as being limited to the details of the invention and is not intended to limit the scope of the invention.

Embodiments of the present disclosure provide a high voltage semiconductor device, such as a laterally diffused MOS field effect transistor, which utilizes a counter implant region to enhance isolation between adjacent high voltage semiconductor devices, thereby shortening The distance between the high voltage semiconductor devices reduces the device size or wafer area.

Referring to FIG. 1E, a cross-sectional view of a high voltage semiconductor device 200 in accordance with an embodiment of the present disclosure is shown. In the present embodiment, the high voltage semiconductor device 200 includes a semiconductor substrate 100 having a well region 102 and at least one isolation structure 104, wherein a first region 102a defined in the well region 102 on both sides of the isolation structure 104 and A second zone 102b. In the present embodiment, the well region 102 acts as a high voltage well region of the high voltage semiconductor device 200 and has a first conductivity type, such as a P-type or an N-type. In one example, well region 102 is P-type and has a doping concentration of 1.0 x 10 ¹⁶ ions/cm ³ . In another example, well region 102 is N-type and has a doping concentration of 9.0 x 10 ¹⁵ ions/cm ³ .

In an embodiment, the isolation structure 104 can be a field oxide, such as a trench isolation structure. In one example, the trench isolation structure has a depth greater than 4000 angstroms and no more than 8000 angstroms. That is, the trench isolation structure has a depth greater than that of a typical shallow trench isolation structure, but less than a typical deep trench isolation structure. In other embodiments, the isolation structure 104 is a local oxidation of silicon (LOCOS).

In the embodiment, the high voltage semiconductor device 200 further includes a first gate structure 112 and a second gate structure 114. The first gate structure 112 is disposed on the first region 102a of the semiconductor substrate 100, and the second gate structure 114 is disposed on the second region 102b of the semiconductor substrate 100. Each gate structure includes a gate dielectric layer in contact with the well region 102 of the semiconductor substrate 100, a gate electrode on the gate dielectric layer, and a gate spacer on the sidewall of the gate electrode.

In the embodiment, the high voltage semiconductor device 200 further includes a first implant region 108 and a second implant region 110. The first implant region 108 and the second implant region 110 serve as double diffusion drain regions of the high voltage semiconductor device 200. In the present embodiment, the first implant region 108 is located within the first region 102a and extends below the first gate structure 112 and adjacent to the isolation structure 104. Moreover, the second implant region 110 is located in the second region 102b and extends below the second gate structure 112 and adjacent to the isolation structure 104. In this embodiment, the first planting area 108 and the second planting area 110 are The depth is less than the depth of the isolation structure 104. Furthermore, the first implant region 108 and the second implant region 110 have a second conductivity type different from the first conductivity type. In one example, the first conductivity type may be a P type and the second conductivity type is an N type. In another example, the first conductivity type may be an N type and the second conductivity type is a P type.

In this embodiment, the high voltage semiconductor device 200 further includes a third implant region 116 and a fourth implant region 118 having a second conductivity type. The third planting zone 116 is located within the first planting zone 108 and the fourth planting zone 118 is located within the second planting zone 110. The third implanting area 116 and the fourth implanting area 118 serve as a source/drainage implanting region having a doping concentration greater than the first implanted region 108 and the second implanted region 110 that are double diffused drain regions.

In the present embodiment, the high voltage semiconductor device 200 further includes a reverse implant region 106 located in the well region 102 below the isolation structure 104 and extending laterally below the first implant region 108 and the second implant region 110. In one embodiment, the reverse implant region 106 has two opposing edges 106a and 106b (shown in Figure 1C). The edges 106a and 106b are generally aligned with an edge 108a of the first implant region 108 (labeled in FIG. 1C) and an edge 110a of the second implant region 110 (labeled in FIG. 1C). In the present embodiment, the reverse implant region 106 has a first conductivity type and has a doping concentration greater than the doping concentration of the well region 102. In one example, the anti-planting region 106 is P-type and has a doping concentration of 5.0 x 10 ¹⁶ ions/cm ³ . In another example, the anti-planting region 106 is N-type and has a doping concentration of 6.0 x 10 ¹⁶ ions/cm ³ .

In the present embodiment, the high voltage semiconductor device 200 further includes a metallization layer on the semiconductor substrate 100 and covers the first gate structure 112 and the second gate structure 114. The metallization layer can include an inner dielectric (ILD) layer 115 and an inner connection structure. The inner connecting structure at least includes a coupling to the third implanting area 116 and the first The source/drain electrodes 117 and 119 of the four implant regions 118 and the interconnect trace layer 121 on the ILD layer 115 above the isolation structure 104.

Next, please refer to FIGS. 1A to 1E , which are schematic cross-sectional views showing a method of manufacturing the high voltage semiconductor device 200 according to an embodiment of the present disclosure. Referring to FIG. 1A, a semiconductor substrate 100 having a well region 102 and at least one isolation structure 104 is provided, wherein a first region 102a and a second region are defined in the well region 102 on both sides of the isolation structure 104. 102b. In this embodiment, the semiconductor substrate 100 can be a germanium substrate, a germanium telluride (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, a silicon on insulator (SOI). A substrate or other conventional semiconductor substrate.

The well region 102 acts as a high voltage well region of the high voltage semiconductor device 200 and has a first conductivity type, such as a P-type or an N-type. In one example, well region 102 is P-type and has a doping concentration of 1.0 x 10 ¹⁶ ions/cm ³ . In another example, well region 102 is N-type and has a doping concentration of 9.0 x 10 ¹⁵ ions/cm ³ .

The isolation structure 104 can be a field oxide, such as a trench isolation structure. In one example, the trench isolation structure has a depth greater than 4000 angstroms and no more than 8000 angstroms.

Referring to FIG. 1B, a first ion implant 20 is performed using a implant mask 10 to form a reverse implant region 106 having a first conductivity type in the well region 102 below the bottom of the isolation structure 104. There is a doping concentration that is greater than the doping concentration of the well region 102. In one example, the anti-planting region 106 is P-type and has a doping concentration of 5.0 x 10 ¹⁶ ions/cm ³ . In another example, the anti-planting region 106 is N-type and has a doping concentration of 6.0 x 10 ¹⁶ ions/cm ³ . In the present embodiment, since the implant mask 10 has an opening exposing the isolation structure 104 and the first region 102a adjacent to a portion of the isolation structure 104 and a portion of the second region 102b, the formed reverse implant region 106 extends laterally. In the first zone 102a and the second zone 102b.

Referring to FIG. 1C, a second ion implant 30 is performed using the same implant mask 10 to form a first implant region 108 adjacent to the isolation structure 104 in the first region 102a and the second region 102b, respectively. And a second planting area 110. In this embodiment, the depths of the first implanting area 108 and the second planting area 110 are smaller than the depth of the isolation structure 104 and are respectively located on the reverse planting areas 106 extending from the first area 102a and the second area 102b. Furthermore, the first implant region 108 and the second implant region 110 have a second conductivity type different from the first conductivity type. In one example, the first conductivity type may be a P type and the second conductivity type is an N type. In another example, the first conductivity type may be an N type and the second conductivity type is a P type. In this embodiment, since the first planting area 108 and the second planting area 110 are formed by the same planting mask 106, the two opposite edges 106a of the backing area 106 and 106b is generally aligned with an edge 108a of the first implant region 108 and an edge 110a of the second implant region 110, respectively.

Referring to FIG. 1D, a first gate structure 112 and a second gate structure 114 are formed on the first region 102a and the second region 102b, respectively, by using a conventional MOS process. Furthermore, a third implanting region 116 and a fourth implanting region 118 having a second conductivity type are formed in the first implanting region 108 and the second implanting region 110, respectively. The third implanting area 116 and the fourth implanting area 118 serve as a source/drainage implanting region having a doping concentration greater than the first implanted region 108 and the second implanted region 110 that are double diffused drain regions.

Referring to FIG. 1E, a metallization layer is formed on the semiconductor substrate 100 by using a conventional metallization process, and covers the first gate structure 112 and the second gate. Pole structure 114. As a result, the high voltage semiconductor device 200 is formed. In an embodiment, the metallization layer can include an inner dielectric (ILD) layer 115 and an inner connection structure. In one embodiment, the interconnect structure includes at least source/drain electrodes 117 and 119 coupled to the third implant region 116 and the fourth implant region 118, respectively, and the ILD layer 115 above the isolation structure 104. The interconnecting wire layer 121.

In the high voltage semiconductor device 200, the interconnect wiring layer 121, the ILD layer 115, the isolation structure 104, and the well region 102 constitute a parasitic gold oxide semiconductor. When the high voltage semiconductor device 200 is operated, the high voltage conduction parasitic MOS transistor applied to the interconnect wiring layer 121 can be prevented by the reverse implant region 106, thereby helping the isolation structure 104 maintain its isolation. Furthermore, since the first implanting area 108 and the second planting area 110 have a back implanting area 106, the reduced surface electric field (RESURF) can be improved.

Please refer to Table 1, which shows the parasitic MOS transistor in the N-type high voltage MOS transistor without the anti-implantation region and the parasitic MOS device of the N-type high voltage MOS transistor with the anti-implantation region (as shown in Fig. 1E). The gate current (A) corresponding to the surface width (μm) of the different isolation structures at a working voltage of 40 volts (V).

As shown in Table 1, when the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.2 μm, the drain current (A) of the parasitic MOS transistor in the N-type high voltage MOS transistor without the anti-implantation region is 4.2. ×10 ^-6 A is rapidly increased to 2.2 × 10 ^-3 A. However, when the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.0 μm, the drain current (A) of the parasitic MOS transistor in the N-type high voltage MOS transistor having the reverse implant region is maintained at 2.7 × 10 The range of ^-12 to 2.8 x 10 ^-12 is much smaller than 4.2 x 10 ^-6 A. That is, even if the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.0 μm, the anti-implantation region in the N-type high voltage MOS transistor can effectively prevent the parasitic MOS transistor from being turned on.

Please refer to Table 2, which shows the parasitic MOS transistor in the P-type high voltage MOS transistor without the anti-implantation region and the parasitic MOS device of the P-type high voltage MOS transistor with the anti-implantation region (as shown in Fig. 1E). The gate current (A) corresponding to the surface width (μm) of the different isolation structures when the operating voltage is -40 volts (V).

As shown in Table 2, when the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.0 μm, the drain current (A) of the parasitic MOS transistor in the P-type high voltage MOS transistor without the anti-planting region is caused by - 3.7 × 10 ^-8 A quickly increased to -4.1 × 10 ^-4 A. However, when the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.0 μm, the drain current (A) of the parasitic MOS transistor in the P-type high voltage MOS transistor having the reverse implant region is maintained at -7.4 × The range of 10 ^-13 to -1.3 × 10 ^-12 is much smaller than -3.7 × 10 ^-8 A. That is, even if the surface width (μm) of the isolation structure is reduced from 2.0 μm to 1.0 μm, the anti-implantation region in the P-type high voltage MOS transistor can also effectively prevent the parasitic MOS transistor from being turned on.

According to the above embodiment, since the high voltage semiconductor device 200 has the reverse implant region 106, the surface width W of the isolation structure 104 can be reduced by at least 50% compared to the P-type or N-type high voltage semiconductor device without the reverse implant region. . In this way, the wafer area can be effectively reduced by reducing the planar size of the isolation structure 104, thereby increasing the number of wafers in each wafer. Furthermore, the trench isolation structure having a depth of more than 4000 angstroms and not more than 8000 angstroms in the high voltage semiconductor device 200 having the reverse implant region 106 can relatively reduce the difficulty of the process and the high voltage semiconductor device using the deep trench isolation structure. manufacturing cost. In addition, since the reverse planting zone 106 and the first and second planting zones 108 and 110 are formed using the same implant mask, there is no need to use an additional implant mask.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor substrate

102‧‧‧ Well Area

102a‧‧‧First District

102b‧‧‧Second District

104‧‧‧Isolation structure

106‧‧‧Replanting area

108‧‧‧First planting area

110‧‧‧Second planting area

112‧‧‧First gate structure

114‧‧‧Second gate structure

115‧‧‧ Inner dielectric layer

116‧‧‧ Third planting area

117, 119‧‧‧ source/drain electrodes

118‧‧‧The fourth planting area

121‧‧‧Internal conductor layer

200‧‧‧High voltage semiconductor device

W‧‧‧ surface width

Claims (19)

A high voltage semiconductor device comprising: a semiconductor substrate having a well region of a first conductivity type and an isolation structure located in the well region, wherein a first region and a second region are respectively defined on two sides of the isolation structure a first gate structure and a second gate structure are respectively disposed on the first zone and the second zone; a first planting zone and a second planting zone are respectively located in the first zone And the second region and adjacent to the isolation structure, wherein the first implant region and the second implant region have a second conductivity type different from the first conductivity type; and a reverse implant region, located at The well region below the isolation structure and extending laterally below the first implant region and the second implant region, wherein the reverse implant region has the first conductivity type and has a doping concentration greater than the well A doping concentration of the zone. The high voltage semiconductor device of claim 1, wherein the reverse implant region has two opposite edges, and the edges are substantially aligned with an edge of the first implant region and the second An edge of the planting area. The high voltage semiconductor device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The high voltage semiconductor device according to claim 3, wherein the doping concentration of the well region is 1.0×10 ¹⁶ ions/cm ³ , and the doping concentration of the reverse implant region is 5.0×10 ¹⁶ ions. /cm ³ . The high voltage semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The high voltage semiconductor device according to claim 5, wherein the doping concentration of the well region is 9.0×10 ¹⁵ ions/cm ³ , and the doping concentration of the anti-implantation region is 6.0×10 ¹⁶ ions. /cm ³ . The high voltage semiconductor device of claim 1, wherein the isolation structure is a trench isolation structure, and the trench isolation structure has a depth greater than 4000 angstroms and no more than 8000 angstroms. The high voltage semiconductor device of claim 1, further comprising a third implanting area and a fourth implanting area, having the second conductive type and respectively located in the first implanting area and the second cloth In the planting area. The high voltage semiconductor device according to claim 8, wherein the third implanting region and the fourth implanting region have a doping concentration greater than that of the first implanting region and the second implanting region. Miscellaneous concentration. A method of manufacturing a high voltage semiconductor device, comprising: providing a semiconductor substrate having a well region of a first conductivity type and an isolation structure located in the well region, wherein a first surface is defined on each side of the isolation structure a region and a second region; forming a reverse implanting region having the first conductivity type in the well region below the isolation structure, wherein the reverse implant region extends laterally in the first region and the second region And having a doping concentration greater than a doping concentration of the well region; forming a first implant region adjacent to the isolation structure on the anti-planting region of the first region and the second region, respectively a second planting zone, wherein the first planting zone and the second planting zone have a second conductivity type different from the first conductivity type; and respectively formed on the first zone and the second zone a first gate structure and a first Two gate structure. The manufacturing method of the high voltage semiconductor device according to claim 10, wherein the anti-planting area is formed by using an implant mask, and the first implanting area and the second are simultaneously formed by using the implant mask Planting area. The method of manufacturing a high voltage semiconductor device according to claim 10, wherein the reverse implanting region has two opposite edges, and the edges are substantially aligned with an edge of the first implanting region, respectively. An edge of the second planting area. The method of manufacturing a high voltage semiconductor device according to claim 10, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The method of manufacturing a high voltage semiconductor device according to claim 13, wherein the doping concentration of the well region is 1.0×10 ¹⁶ ions/cm ³ , and the doping concentration of the reverse implant region is 5.0×. 10 ¹⁶ ions/cm ³ . The method of manufacturing a high voltage semiconductor device according to claim 10, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The method of manufacturing a high voltage semiconductor device according to claim 15, wherein the doping concentration of the well region is 9.0×10 ¹⁵ ions/cm ³ , and the doping concentration of the reverse implant region is 6.0×. 10 ¹⁶ ions/cm ³ . The method of fabricating a high voltage semiconductor device according to claim 10, wherein the isolation structure is a trench isolation structure, and the trench isolation structure has a depth greater than 4000 angstroms and no more than 8000 angstroms. The method for manufacturing a high voltage semiconductor device according to claim 10, further comprising forming a third implant region having the second conductivity type in the first implant region and the second implant region, respectively A fourth planting area. The method for manufacturing a high voltage semiconductor device according to claim 18, wherein the third implanting region and the fourth implanting region have a doping concentration greater than the first implanting region and the second implanting region a doping concentration.