TW201312747A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a transistor and a method of fabricating the same.

In semiconductor technology, for example, a semiconductor device such as a power device uses a lateral double-diffused metal oxide semiconductor (LDMOS). In order to increase the breakdown voltage (BVdss) of a semiconductor device, one method reduces the doping concentration of the drain region and increases the drift length. However, this method increases the turn-on resistance of the semiconductor device. In addition, a large design area is required.

Insulated Gate Bipolar Transistors (IGBTs) in semiconductor technology have the advantages of both a transistor (MOS) and a bipolar junction transistor (BJT). Insulated gate bipolar transistors can be used in switching applications.

The present invention relates to a semiconductor device and a method of fabricating the same. The semiconductor device has excellent performance and is low in manufacturing cost.

A semiconductor device is provided. The semiconductor device includes a first doped region, a second doped region, a dielectric structure, and a gate structure. The first doped region has a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type and is adjacent to the first doped region. The dielectric structure includes a first dielectric portion and a second dielectric portion that are separated from each other. A dielectric structure is formed on the first doped region. The gate structure is located on the first doped region or the second doped region adjacent to a portion of the first dielectric portion.

A method of fabricating a semiconductor device is provided. The method includes the following steps. A second doped region is formed in the first doped region. The first doped region has a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. A dielectric structure is formed on the first doped region. The dielectric structure includes a first dielectric portion and a second dielectric portion that are separated from each other. Forming a gate structure on the first doped region or the second doped region adjacent to a portion of the first dielectric portion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a semiconductor device in an embodiment. Referring to FIG. 1 , the first doping region 12 is adjacent to the second doping region 14 . The first doped region 12 includes a doped portion 28 having a first conductivity type such as an N conductivity type. The second doped region 14 may include a doped portion 30 and a doped portion 32 having a second conductivity type opposite to the first conductivity type, such as a P conductivity type. In an embodiment, the doped portion 30 is formed by doping the first doped region 12 with a patterned mask layer (not shown). The doped portion 32 is formed by doping the doped portion 30 by a patterned mask layer (not shown). The doped portion 32 can be a heavily doped region.

In one embodiment, a third doped region 34 having a first conductivity type, such as an N conductivity type, is formed by doping the doped portion 30 with a patterned mask layer (not shown). The fourth doped region 36 is formed by doping the first doped region 12 by a patterned mask layer (not shown). The third doping region 34 and the fourth doping region 36 may be heavily doped regions.

Referring to FIG. 1 , a dielectric structure 16 is formed on the first doping region 12 . The dielectric structure 16 includes a first dielectric portion 18 and a second dielectric portion 20 that are separated from one another. The first dielectric portion 18 and the second dielectric portion 20 are not limited to the field oxide shown in FIG. 1, but may be shallow trench isolation structures or other suitable insulators.

The gate structure 22 is formed on the first doped region 12 or the second doped region 14 adjacent to a portion of the first dielectric portion 18. The gate structure 22 may include a dielectric layer 24 formed on the first doped region 12 or the second doped region 14, and an electrode layer 26 formed on the dielectric layer 24. Electrode layer 26 can comprise a metal, polysilicon or metal halide.

Referring to FIG. 1 , the fourth doping region 36 and the second doping region 14 are respectively located on opposite sides 46 , 48 of the dielectric structure 16 . In one embodiment, the first doped layer 50 is formed on the doped portion 28 between the first dielectric portion 18 and the second dielectric portion 20. The first doping layer 50 has a second conductivity type such as a P conductivity type. The first doped region 12 may include a second doped layer 52 having a first conductivity type such as an N conductivity type and under the first doping layer 50. The second doped layer 52 can be formed by doping the doped portion 28 by a patterned mask layer (not shown). The first doped layer 50 can be formed by doping the second doped layer 52 by a patterned mask layer (not shown).

Referring to FIG. 1 , the bottom layer 54 may be located below the first doping region 12 . The bottom layer 54 may have a second conductivity type such as a P conductivity type. The bottom layer 54 can be a substrate or an epitaxial layer. In one embodiment, the bottom layer 54 is a silicon-on-insulator (SOI). The doped portion 28 of the first doped region 12 can be formed by doping the underlayer 54 with a patterned mask layer (not shown). The doped portion 28 can also be formed on the underlayer 54 in an epitaxial manner. The doped well region 56 is adjacent to the doped portion 28 and is located on the bottom layer 54. The doped well region 56 includes a doped portion 58 and a doped portion 60 having a second conductivity type such as a P conductivity type. The doped portion 58 can be formed by doping the underlayer 54 with a patterned mask layer (not shown). The doped portion 58 can also be formed on the underlayer 54 in an epitaxial manner. The doped portion 60 can be formed by doping the doped portion 58 with a patterned mask layer (not shown). Doped portion 60 can be a heavily doped region.

In one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) such as a Lateral Double Diffusion Metal Oxide Semiconductor (LDMOS). In this example, the first doped region 12 includes a fourth doped region 36 having a first conductivity type such as an N conductivity type. The gate structure 22 is located on the doped portion 30 between the doped portion 28 and the third doped region 34. The electrode 40 is electrically connected to the fourth doping region 36, for example, a drain electrode. The electrode 42 such as a source electrode is electrically connected to the third doping region 34. Electrode 44, such as a gate electrode, is electrically coupled to gate structure 22. Electrode 38, such as a base electrode, is electrically coupled to doped portion 32. The electrode 38 and the electrode 42 can be electrically connected to each other.

In another embodiment, the semiconductor device is an insulated gate bipolar transistor (IGBT), and in detail, a lateral insulated gate bipolar transistor (LIGBT). In this example, the fourth doping region 36 has a second conductivity type such as a P conductivity type. The gate structure 22 is located on the doped portion 28 between the first dielectric portion 18 and the doped portion 30. The electrode 40, for example, the collector electrode is electrically connected to the fourth doping region 36. Electrode 38, such as an emitter electrode, is electrically coupled to doped portion 32. Electrode 44, such as a gate electrode, is electrically coupled to gate structure 22. The electrode 42 is electrically connected to the third doping region 34, for example, the base electrode. The electrode 38 and the electrode 42 can be electrically connected to each other.

The semiconductor device can simply control the conductivity type of the fourth doping region 36 to be a first conductivity type such as an N conductivity type to fabricate a (800V) lateral double diffusion transistor, or a second conductivity type such as a P conductivity type to fabricate (700V) insulation. Gate bipolar transistor. The semiconductor device can be fabricated by a CMOS process such as a 700V power CMOS process, so the fabrication of the semiconductor device does not require the addition of additional masks or steps, and is also advantageous for integration with other devices in the same wafer. In an embodiment, the dielectric structure 16 and the first doped layer 50 and the second applied to the concept of reduced surface field (RESURF) (more specifically, double RESURF) are used. The doping layer 52 helps to increase the drain breakdown voltage of the semiconductor device such as LDMOS and lowers the turn-on resistance (Rdson). In one embodiment, the semiconductor device is a 700V or 820V lateral double diffused transistor.

For example, when the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type, the semiconductor device is an N-channel LIGBT (N-channel LIGBT) or an LDNMOS. Conversely, when the first conductivity type is a P conductivity type and the second conductivity type is an N conductivity type, the semiconductor device is a P channel LIGBT (P-channel LIGBT) or LD PMOS.

2 is a cross-sectional view showing a semiconductor device in an embodiment. The difference between the semiconductor device shown in FIG. 2 and the semiconductor device shown in FIG. 1 is that the first doping region 112 includes a doping portion 162 having a first conductivity type such as an N conductivity type. The doped portion 162 can be formed by doping the doped portion 128 by a patterned mask layer (not shown). In this example, the fourth doped region 136 can be formed by doping the doped portion 162 with a patterned mask layer (not shown).

3 is a cross-sectional view showing a semiconductor device in an embodiment. The difference between the semiconductor device shown in FIG. 3 and the semiconductor device shown in FIG. 1 is that the isolation structure 264 surrounds the doped portion 228 of the first doping region 212. The isolation structure 264 can include an isolation portion 266, an isolation portion 268, and an isolation portion 270. For example, the isolation portion 266 formed on the bottom layer 254 is a buried layer such as a dielectric oxide. Isolation portion 268 can be deep trench isolation, including dielectric oxide. The isolation portion 270 formed on the isolation portion 268 is not limited to the field oxide, but may also be shallow trench isolation.

4 is a cross-sectional view showing a semiconductor device in an embodiment. The difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in FIG. 3 is that the first doped region 312 includes a doped portion 362 having a first conductivity type such as an N conductivity type. The doped portion 362 can be formed by doping the doped portion 328 by a patterned mask layer (not shown). In this example, the fourth doped region 336 can be formed by doping the doped portion 362 with a patterned mask layer (not shown).

Fig. 5 is a cross-sectional view showing a semiconductor device in an embodiment. The difference between the semiconductor device shown in FIG. 5 and the semiconductor device shown in FIG. 1 is that the dielectric structure 416 includes at least a third dielectric portion 472 located in the first dielectric portion 418 and the second dielectric portion 420. between. The doped portion of the first doped region 412 having the first doped layer 452 of the first conductivity type, such as the N conductivity type, between the first dielectric portion 418, the second dielectric portion 420, and the third dielectric portion 472 On 428. A first doping layer 450 having a second conductivity type such as a P conductivity type is located on the second doping layer 452.

Figure 6 is a cross-sectional view showing a semiconductor device in an embodiment. The difference between the semiconductor device shown in FIG. 6 and the semiconductor device shown in FIG. 5 is that the first doped region 512 includes a doped portion 562 having a first conductivity type such as an N conductivity type. Doped portion 562 can be formed by doping dopant portion 528 with a patterned mask layer (not shown). In this example, the fourth doped region 536 can be formed by doping the doped portion 562 with a patterned mask layer (not shown).

Fig. 7 shows an embodiment in which the semiconductor device is an off-BV curve of the LIGBT in a closed state, and the BV is 820V. Fig. 8 shows an ID-VD curve of the semiconductor device in an embodiment in which the IGBT is 5V. Fig. 9 compares the linear region current (idline) between the LIGBT and the double RESURF LDNMOS in the semiconductor device of the embodiment, wherein the IGBT of the LIGBT is 5V and the LDNMOS is 10V.

According to the embodiments disclosed above, the semiconductor device can simply control the conductivity type of the fourth doped region to determine the fabrication of the lateral double-diffused transistor or the insulating gate bipolar transistor, and can be fabricated by a CMOS process, so that the fabrication of the semiconductor device is advantageous. Integration of different devices at no additional cost. The dielectric structure and the first doped layer and the second doped layer applied to the concept of reduced surface field (RESURF) help to improve the operational efficiency of the semiconductor device.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

12, 112, 212, 312, 412, 512. . . First doped region

14. . . Second doped region

16,416. . . Dielectric structure

18,418. . . First dielectric part

20, 420. . . First dielectric part

twenty two. . . Gate structure

twenty four. . . Dielectric layer

26. . . Conductive layer

28, 30, 32, 128, 228, 328, 428, 528, 58, 60, 162, 362, 562. . . Doped part

34. . . Third doped region

36, 136, 336, 536. . . Fourth doped region

38, 40, 42, 44. . . electrode

46, 48. . . Side

50, 450. . . First doped layer

52, 452. . . Second doped layer

54,254. . . Bottom layer

56. . . Doped well zone

264. . . Isolation structure

266, 268, 270. . . Isolated part

472. . . Third dielectric part

1 is a cross-sectional view showing a semiconductor device in an embodiment.

2 is a cross-sectional view showing a semiconductor device in an embodiment.

3 is a cross-sectional view showing a semiconductor device in an embodiment.

4 is a cross-sectional view showing a semiconductor device in an embodiment.

Fig. 5 is a cross-sectional view showing a semiconductor device in an embodiment.

Figure 6 is a cross-sectional view showing a semiconductor device in an embodiment.

Fig. 7 is a view showing a breakdown voltage curve of the semiconductor device in a closed state in an embodiment.

Fig. 8 shows an ID-VD curve of a semiconductor device in an embodiment.

Fig. 9 shows the linear region current of the semiconductor device in the embodiment.

12. . . First doped region

14. . . Second doped region

16. . . Dielectric structure

18. . . First dielectric part

20. . . First dielectric part

twenty two. . . Gate structure

twenty four. . . Dielectric layer

26. . . Conductive layer

28, 30, 32. . . Doped part

34. . . Third doped region

36. . . Fourth doped region

38, 40, 42, 44. . . electrode

46, 48. . . Side

50. . . First doped layer

52. . . Second doped layer

54. . . Bottom layer

56. . . Doped well zone

Claims (10)

A semiconductor device comprising: a first doped region having a first conductivity type; a second doped region having a second conductivity type opposite to the first conductivity type and adjacent to the first doped region; a dielectric structure comprising a first dielectric portion and a second dielectric portion separated from each other, wherein the dielectric structure is formed on the first doped region; and a gate structure is located in the first doped region The impurity region or the second doped region is adjacent to a portion of the first dielectric portion. The semiconductor device of claim 1, further comprising a first doped layer having the second conductivity type, wherein the first doped layer is located in the first dielectric portion and the second dielectric portion The first doped region between the first doped region includes a second doped layer having the first conductivity type and under the first doped layer. The semiconductor device of claim 1, wherein the dielectric structure further comprises at least a third dielectric portion between the first dielectric portion and the second dielectric portion. The semiconductor device of claim 1, further comprising a third doped region having the first conductivity type, wherein the gate structure is located in the first doped region and the third doped region A first electrode is electrically connected to the first doped region, and a second electrode is electrically connected to the third doped region. The semiconductor device according to claim 4, wherein the first electrode is a drain electrode, the second electrode is a source electrode, and the semiconductor device is an LDMOS. The semiconductor device of claim 1, further comprising a fourth doped region having the second conductivity type, wherein the second doped region and the fourth doped region are respectively located at a relative of the dielectric structure On the side. The semiconductor device of claim 6, wherein a first electrode is electrically connected to the second doped region, and a second electrode is electrically connected to the fourth doped region. The semiconductor device according to claim 7, wherein the first electrode is an emitter electrode and the second electrode is a collector electrode, and the semiconductor device is a laterally insulated gate bipolar transistor. The semiconductor device according to claim 1, wherein the semiconductor device is a lateral double-diffused metal oxide semiconductor or an insulating gate bipolar transistor. A method of fabricating a semiconductor device includes: forming a second doped region in a first doped region, the first doped region having a first conductivity type, the second doped region having a first opposite a second conductivity type of a conductive type; forming a dielectric structure on the first doped region, wherein the dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other; and forming a gate The pole structure is adjacent to the first doped region or the second doped region adjacent to a portion of the first dielectric portion.