TW201526203A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

The focus of the latest technological developments is the high-voltage power integrated circuit. Such a high voltage power integrated circuit can be applied to fields such as switching mode power supply (SMPS), lighting, motor control or plasma display drivers to increase product efficiency, reliability and flexibility, and Ultimately reduce system costs.

In general, high-voltage power integrated circuits are mainly used in power switching components, such as power switching devices to provide power switching. There are currently two parameters that influence the market for power switching: the breakdown voltage and the on-state resistance, which can vary with different needs. The high voltage power integrated circuit is designed to reduce the on-state resistance while maintaining a high breakdown voltage. In fact, if the product is to meet the specifications for the breakdown voltage, the on-state resistance is usually sacrificed. In other words, the breakdown voltage is in a trade-off relationship with the on-state resistance.

The present invention provides a method of manufacturing a semiconductor element and a semiconductor element, which can reduce the on-state resistance and increase the breakdown voltage of the element.

The present invention provides a semiconductor device including a deep doped region having a first conductivity type, a first well region having a second conductivity type, a base region having a first conductivity type, an insulating gate bipolar transistor, and a MOS transistor Crystal. The deep doped region includes a first buried layer and two high-doped regions, and is located in the substrate. The first well zone is located in the deep doped zone. The base region is located in the first well region and is not connected to the deep doped region. An insulating gate bipolar transistor is located on the first well region on the first side of the base region and includes a first doped region having a second conductivity type in the base region. The gold oxide semiconductor is located on the first well region and the deep doped region on the second side of the base region, and includes a second doped region having a second conductivity type in the base region.

In an embodiment of the invention, the semiconductor device further includes a second buried layer having a second conductivity type between the first buried layer and the substrate.

In an embodiment of the invention, the semiconductor component further includes a second well region having a second conductivity type, located in the first well region, wherein the substrate region is located in the second well region.

In an embodiment of the invention, the insulated gate bipolar transistor further includes: an isolation structure located in the first well region; and a gate structure located on the first well region on the first side of the isolation structure, covering part of the isolation a structure and a portion of the base region adjacent to the first doped region; a third doped region having a first conductivity type, located in the first well region on the second side of the isolation structure; and a fourth conductivity type having a second conductivity type a doped region, located in the first well region between the third doped region and the isolation structure, and in contact with the third doped region; and a top doped region having the first conductivity type, located under the isolation structure.

In an embodiment of the invention, the top doped region extends from below the isolation structure to below the fourth doped region and is in contact with the fourth doped region.

In an embodiment of the invention, the top doped region extends from below the isolation structure to below the third doped region and is in contact with the third doped region and the fourth doped region.

The present invention further provides a method of fabricating a semiconductor device. Forming a deep doped region deep doped region having a first conductivity type in the substrate includes a first buried layer and a second high voltage doped region. A first well region having a second conductivity type is formed in the deep doped region. A base region having a first conductivity type is formed in the first well region, and the base region is not connected to the deep doped region. An insulating gate bipolar transistor is formed on the first well region on the first side of the base region, and forming the insulating gate bipolar transistor includes forming a first doped region having a second conductivity type in the base region. A gold oxide semi-transistor is formed on the first well region and the deep doped region on the second side of the base region, and forming the metal oxide semi-electrode includes forming a second doped region having the second conductivity type in the base region.

In an embodiment of the invention, the method further includes forming a second buried layer having a second conductivity type between the first buried layer and the substrate.

In an embodiment of the invention, the method further includes forming a second well region having a second conductivity type in the first well region, wherein the base region is located in the second well region.

In an embodiment of the invention, forming the insulating gate bipolar transistor further comprises: forming an isolation structure in the first well region; forming a gate structure on the first well region on the first side of the isolation structure to cover a portion of the isolation structure and a portion of the substrate region adjacent to the first doped region; forming a third doped region having a first conductivity type in the first well region on the second side of the isolation structure; Forming a fourth doped region having a second conductivity type in the first well region with the isolation structure, the fourth doped region is in contact with the third doped region; and forming a first conductivity type under the isolation structure Top doped region.

Based on the above, the semiconductor device of the present invention utilizes a structure in which a base region is formed and is not connected to a deep doped region, so that the MOS transistor has a channel, allowing the MOS transistor to generate more electron current to reduce conduction. State resistance, and the use of well, buried layer and top doped regions to generate multiple reduction surface electric field (Multi-RESURF) structure to enhance the breakdown voltage.

The above described features and advantages of the invention will be apparent from the following description.

In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. In the present embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, the present invention is not limited thereto. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a substrate 100, an insulating gate bipolar transistor 200, a MOS transistor 300, a deep doped region 120 having a first conductivity type, and a second conductive layer. A first well region 110 of the type, and a base region 130 having a first conductivity type. The insulated gate bipolar transistor 200 is located on the first well region 110 on the first side of the base region 130. The gold oxide semi-crystal 300 is located on the first well region 110 on the second side of the base region 130. The base region 130 is located in the first well region 110 and is not connected to the deep doped region 120 below, so that the electron flow generated by the MOS transistor 300 can be directly formed between the base region 130 and the deep doped region 120. The second conductivity type of channel, therefore, can reduce the on-resistance and increase the conduction of electron flow.

The material of the substrate 100 is, for example, a semiconductor substrate having a first conductivity type, such as a P-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 100 can also be a blanket insulating (SOI) substrate.

The deep doped region 120 having the first conductivity type includes a first buried layer 122 (eg, a P-type buried layer, PBL) and two high-voltage doped regions 124, 126 (eg, a high-voltage P-type drift region), and is located on the substrate 100.

A first well region 110 having a second conductivity type (eg, a high pressure N-type well region) is located in the substrate 100. The first well region 110 can be formed by a lithography process and an ion implantation process. In an embodiment, the doping implanted in the first well region 110 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ^{́10 12} /cm ² to ^{2 ́10 12} /cm ² , the implanted energy. For example, 140 eV to 160 eV.

The first well region 110 is located in the deep doped region 120. More specifically, the first buried layer 122 is located below the first well region 110 and adjacent to the first well region 110; and the two high voltage doped regions 124, 126 are on both sides of the first well region 110 and The first well zone 110 is adjacent.

In one embodiment, the doping concentration of the first buried layer 122 and the two high voltage doped regions 124, 126 are the same. The first buried layer 122 and the two high voltage doped regions 124, 126 can be formed by forming the same lithography process and the same ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ́10 ¹³ /cm ² to ^{2 ́10 13} /cm ² , and the implanted energy is, for example, 50 eV to 70 eV.

In another embodiment, the doping concentration of the first buried layer 122 and the two high voltage doped regions 124, 126 are different. The first buried layer 122 and the two high voltage doped regions 124, 126 can be formed by different lithography and different ion implantation processes, respectively. The doping concentration of the two high voltage doping regions 124, 126 may be lower than the doping concentration of the first buried layer 122. In an embodiment, the doping implanted in the first buried layer 122 is, for example, boron, and the doping dose is, for example, ^{2 ́10 13} /cm ² to ^{3 ́10 13} /cm ² , and the implanted energy is, for example, 60 eV to 80 eV. The doping of the two high-voltage doping regions 124, 126 is, for example, boron, and the doping dose is, for example, 1 ́10 ¹³ /cm ² to ^{2 ́10 13} /cm ² , and the implanted energy is, for example, 50 eV to 60 eV.

A base region 130 having a first conductivity type (e.g., a P-type base region) is located in the first well region 110, and a bottom portion of the base region 130 is not connected to the deep doped region 120. The base region 130 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, ^{2 ́10 12} /cm ² to 3 ^{́10 12} /cm ² , and the implanted energy is, for example, 100 eV to 120 eV.

The above semiconductor element may further include a second buried layer 128 having a second conductivity type (for example, an N-type buried layer, NBL). The second buried layer 128 is located between the first buried layer 122 and the substrate 100. The second buried layer 128 can be formed by a lithography process and an ion implantation process. In one embodiment, the second buried layer 128 doped with implanted arsenic or phosphorus, for example, doping dose is, for example, 1'10 ¹² / cm ² to 3'10 ¹² / cm ^2, the implanted The energy is, for example, 240 eV to 260 eV.

The insulated gate bipolar transistor 200 is located on the first well region 110 on the first side of the base region 130. The insulating gate bipolar transistor 200 includes a gate structure 20, a first doping region 140 having a second conductivity type, a fifth doping region 142 having a second conductivity type, and a third doping region having a first conductivity type 170 and a top doped region 190 having a first conductivity type and an isolation structure 10.

The isolation structure 10 is located in the substrate 100. The material of the isolation structure 10 is, for example, doped or undoped cerium oxide, low-stress cerium nitride, cerium oxynitride or a combination thereof, and the method of forming the method can be performed by field oxidation isolation method, shallow trench isolation method or deep trench isolation method. (deep trench isolation process). The thickness of the isolation structure 10 is, for example, 600 nm to 700 nm.

The gate structure 20 is located on the first well region 110 on the first side of the isolation structure 10 and extends over a portion of the isolation structure 10 and a portion of the substrate region 130. The gate structure 20 includes a gate dielectric layer 21 and a gate electrode 22. The material of the gate dielectric layer 21 is, for example, hafnium oxide, tantalum nitride or a high dielectric constant material having a dielectric constant of more than 4. The formation method is, for example, a thermal oxidation method or a chemical vapor deposition method. Gate 22 includes polysilicon, a metal, a metal halide, or a combination thereof. The method of formation is, for example, a chemical vapor deposition method.

A first doped region 140 having a second conductivity type (eg, an N-type heavily doped region, n+) is located in the body region 130 adjacent to the gate structure 20. A fifth doped region 142 having a second conductivity type (eg, an N-type heavily doped region, n+) is located in the substrate 100 on one side of the high voltage doped region 126. The first doping region 140 and the fifth doping region 142 may be formed by a lithography process and an ion implantation process. The doping implanted in the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 3 ^{́10 15} /cm ² to 4 ^{́10 15} /cm ² , and the implanted energy is, for example, 70 eV to 90 eV. .

A third doped region 170 having a first conductivity type (eg, a P-type heavily doped region, p+) is located in the first well region 110 between the second side of the isolation structure 10 and the other side of the high voltage doped region 126 . The third doping region 170 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ^{́10 15} /cm ² to 3 ^{́10 15} /cm ² , and the implanted energy is, for example, 50 eV to 70 eV.

A top doped region 190 having a first conductivity type (eg, a P-type top doped region, p-top) is located below the isolation structure 10. The top doping region 190 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 5 ^{́10 12} /cm ² to 6 ^{́10 12} /cm ² , and the implanted energy is, for example, 160 eV to 180 eV.

The insulated gate bipolar transistor 200 may further include a well region 172 having a second conductivity type, a well region 168 having a second conductivity type, and a well region 174 having a second conductivity type. Well zone 172 is located in first well zone 110 and third doped zone 170 is located in well zone 172. The well region 168 is peripheral to the deep doped region 120. Well zone 174 is in well zone 168 and fifth doped zone 142 is located in well zone 174. Well zone 168 may be formed simultaneously with first well zone 110. The well region 172 and the well region 174 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ́10 ¹³ /cm ² to ^{2 ́10 13} /cm ² , and the implanted energy is, for example, 100 eV to 120 eV. The well region 172 and the well region 174 have a pressure-raising effect, which helps the flow of the hole to flow to the cathode via the first buried layer 122, thereby suppressing the generation of the substrate current.

In addition, the insulated gate bipolar transistor 200 may further include an isolation structure 11. The isolation structure 11 may be located above the high voltage doping region 126, separating the third doping region 170 and the fifth doping region 142.

The gold oxide semi-crystal 300 is located on the first well region 110 and the deep doped region 120 on the second side of the base region 130. More specifically, the MOS semiconductor 300 includes a gate structure 30, a second doping region 150 having a second conductivity type (eg, an N-type heavily doped region, n+), and a sixth doping having a second conductivity type. Miscellaneous region 152 (eg, N-type heavily doped region, n+).

The gate structure 30 is located on the first well region 110 and extends over the other portion of the base region 130 and the high voltage doped region 124. The gate structure 30 includes a gate dielectric layer 31 and a gate 32. The material of the gate dielectric layer 31 is, for example, hafnium oxide, tantalum nitride or a high dielectric constant material having a dielectric constant of more than 4. The formation method is, for example, a thermal oxidation method or a chemical vapor deposition method. Gate 32 includes polysilicon, metal, metal telluride or a combination thereof. The method of formation is, for example, a chemical vapor deposition method.

The second doped region 150 is located in the body region 130 on the first side of the gate structure 30. The sixth doped region 152 is located in the high voltage doped region 124 on the second side of the gate structure 30. The second doping region 150 and the sixth doping region 152 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 3 ^{́10 15} /cm ² to 4 ^{́10 15} /cm ² , and the implanted energy is, for example, 70 eV to 90 eV.

The gold oxide semiconductor 300 may further include a doping region 154 having a first conductivity type. The doped region 154 is located in the high voltage doped region 124 and the sixth doped region 152 is located in the doped region 154. The doping region 154 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, ^{2 ́10 12} /cm ² to 4 ^{́10 12} /cm ² , and the implanted energy is, for example, 100 eV to 140 eV.

Further, the semiconductor element may further include a doping region 132 having a first conductivity type and a doping region 156 having a first conductivity type. The doped region 132 is located in the base region 130 between the second doped region 150 and the first doped region 140. Doped region 156 is located in doped region 154 adjacent to sixth doped region 152. The doped region 132 and the doped region 156 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ^{́10 12} /cm ² to ^{2 ́10 12} /cm ² , and the implanted energy is, for example, 50 eV to 70 eV.

The doped region 156 and the sixth doped region 152 are electrically connected by a metal interconnect 52 as a base. The second doping region 150, the doping region 132, and the first doping region 140 are electrically connected by a metal interconnect 54 as a cathode. The third doping region 170 and the fifth doping region 142 are electrically connected by a metal interconnect 56 as an anode.

The shape of the semiconductor element of the embodiment of the present invention can be designed according to actual needs. The shape may be a circle, an ellipse, a hexagon, an octagon, a polygon, a racetrack, or a combination thereof.

In the embodiment of the present invention, the first buried layer 122 and the second buried layer 128 are disposed under the first well region 110. Therefore, the second buried layer 128 can be used as isolation when the semiconductor element is turned off. When the semiconductor element is turned on, the hole current can flow to the cathode through the first buried layer 122 to suppress the generation of the substrate current; and the electron flow can flow to the anode via the second buried layer 128.

Furthermore, in the embodiment of the present invention, by providing the MOS transistor 300 in the semiconductor device, the DMOS channel can be formed under the gate structure 30 when the semiconductor device is turned on, and the cathode (on) current is increased to Reduce or eliminate substrate current.

In addition, since the base region 130 of the semiconductor device of the present invention is not connected to the deep doped region 120, when the semiconductor device is turned on, the first well region between the base region 130 and the deep doped region 120 under the cathode can be A channel of the second conductivity type is formed in the 110, so that the electron flow generated by the MOS transistor 300 can be directly conducted by the channel before flowing through the second buried layer 128 under the bottom, thereby reducing the path of the electron flow. The on-resistance of the MOS transistor 300 is lowered to increase the amount of current that is turned on. In other words, the semiconductor device of the present invention can increase the channel of the second conductivity type between the base region 130 and the deep doped region 120. Accordingly, the present invention is a high electron injection high voltage multi-channel semiconductor device.

In addition, when the semiconductor device of the embodiment of the present invention is in a closed state, the first buried layer 122, the second buried layer 128, the first well region 110, and the top doped region 190 can be utilized to generate multiple reduced surface electric fields (Multi- RESURF) structure to increase the breakdown voltage.

2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2, the second embodiment is similar to the first embodiment except that the semiconductor component of the second embodiment further includes a second well region 160 (eg, an N-type well region) having a second conductivity type. In the first well region 110, the base region 130 is located in the second well region 160. The second well region 160 can be formed by a lithography process and an ion implantation process. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ́10 ¹³ /cm ² to ^{2 ́10 13} /cm ² , and the implanted energy is, for example, 100 eV to 120 eV. . The doping concentration of the second well region 160 is higher than the doping concentration of the first well region 110, so the resistance value of the region can be effectively reduced to increase the amount of conduction current.

Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention.

Referring to FIG. 3, the third embodiment is similar to the first embodiment except that the insulating gate bipolar transistor 200 of the semiconductor device of the third embodiment further includes a fourth doping region 180 having a second conductivity type. (eg, N-type heavily doped region, n+), located in well region 172 between third doped region 170 and isolation structure 10, and adjacent to third doped region 170. Moreover, the fourth doping region 180 is electrically connected to the third doping region 170 and the fifth doping region 142 by a metal interconnect 56a as an anode. In addition, the top doping region 190a extends from below the isolation structure 10 to below the fourth doping region 180 and is in contact with the fourth doping region 180. The fourth doping region 180 can be formed by a lithography process and an ion implantation process. An ion implantation process, for example, implanted dopant is phosphorus or arsenic, for example, doping dose 3'10 ¹⁵ / cm ² to 4'10 ¹⁵ / cm ^2, for example, implantation energy is 70 eV to 90 eV .

In the third embodiment of the present invention, the top doping region 190a extends from below the isolation structure 10 to below the fourth doping region 180 and is in contact with the fourth doping region 180. Therefore, when the semiconductor device is in an on state, the hole current may flow through the first buried layer 122 (eg, P-type buried layer, PBL) and/or the top doped region 190a to increase the amount of current conducted. In addition, the fourth doping region 180 (for example, the N-type heavily doped region, n+) and the well region 172 also have a pressure-raising effect, which can generate a multiple-reducing surface electric field (Multi-RESURF) structure, thereby avoiding breakdown. ) and the problem of serious leakage current.

Figure 4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

Referring to FIG. 4, the fourth embodiment is similar to the third embodiment except that the top doping region 190b of the semiconductor device of the fourth embodiment extends from below the isolation structure 10 to below the third doping region 170. Contact with the third doping region 170 and the fourth doping region 180. In the fourth embodiment of the present invention, by such a configuration of the top doping region 190b, when the semiconductor device is in an on state, the hole current can flow through the first buried layer 122 (for example, a P-type buried layer, PBL). And/or top doped region 190b to increase the amount of current that is turned on.

Figure 5 is a cross-sectional view showing a fifth embodiment of the present invention.

Referring to FIG. 5, the fifth embodiment is similar to the first embodiment except that the semiconductor component of the fifth embodiment further includes at least one field plate 40 above the isolation structure 10. The field plate 40 material includes polycrystalline germanium, metal, metal halide or a combination thereof. The field plate 40 may be formed by chemical vapor deposition or physical vapor deposition to deposit a field plate material layer, which is then patterned by lithography and etching. The chemical vapor deposition is, for example, plasma-assisted chemical vapor deposition or low-pressure chemical vapor deposition, etc.; physical vapor deposition is, for example, evaporation, sputtering, or ion beam deposition. After the field plate 40 is added, the electric field in the above semiconductor element can be evenly distributed to increase the breakdown voltage. In other words, while maintaining the same breakdown voltage, the size of the isolation structure 10 can be reduced to meet the demand for component miniaturization.

Fig. 6 is a graph showing an anode current voltage of the semiconductor device of the present invention when it is turned off. Fig. 7 is a graph showing anode current voltages of the semiconductor device of the present invention and the conventional IGBT when turned on.

Referring to FIG. 6 and FIG. 7, at the same anode voltage, the semiconductor device of the present invention generates more anode current than conventional insulated gate bipolar transistors, and the semiconductor device of the embodiment of the present invention can withstand high voltage up to 700 volts. .

In summary, the semiconductor device of the present invention not only reduces the on-state resistance, but also improves the on-current, and also provides a stable high breakdown voltage, which reduces the power consumption of the semiconductor component and has better product reliability, and has both gold and gold. Advantages of oxygen semi-transistors and insulated gate bipolar transistors. Furthermore, the semiconductor device of the embodiment of the present invention can be fabricated using an existing 700 volt complementary MOS process. Moreover, it can be applied to today's smart energy-saving products, such as a motor diver that can be applied to a motor, a driver of a light-emitting diode (LED driver), or a current driver.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 11‧‧ ‧ isolation structure

20, 30‧‧ ‧ gate structure
21, 31‧‧‧ gate dielectric layer
22, 32‧‧‧ gate
40‧‧‧ field board
52, 54, 56, 56a‧‧‧Metal interconnection
100‧‧‧Base
110‧‧‧First Well Area
120‧‧‧Deeply doped area
122‧‧‧First buried layer
124, 126‧‧‧High-pressure doped area
128‧‧‧Second buried layer
130‧‧‧Base area
132‧‧‧Doped area
140‧‧‧First doped area
142‧‧‧ fifth doping area
150‧‧‧Second doped area
152‧‧‧ sixth doping area
154, 156‧‧‧Doped area
160‧‧‧Second well area
168, 172, 174‧‧ ‧ well area
170‧‧‧ Third doped area
180‧‧‧fourth doping zone
190, 190a, 190b‧‧‧ top doped area
200‧‧‧Insulated gate bipolar transistor
300‧‧‧Gold oxygen semi-transistor

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention. 4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. Fig. 6 is a graph showing an anode current voltage of the semiconductor device of the present invention when it is turned off. Fig. 7 is a graph showing anode current voltages of the semiconductor device of the present invention and a conventional IGBT when turned on.

10, 11‧‧ ‧ isolation structure

20, 30‧‧ ‧ gate structure

21, 31‧‧‧ gate dielectric layer

22, 32‧‧‧ gate

52, 54, 56‧‧‧Metal interconnection

100‧‧‧Base

110‧‧‧First Well Area

120‧‧‧Deeply doped area

122‧‧‧First buried layer

124, 126‧‧‧High-pressure doped area

128‧‧‧Second buried layer

130‧‧‧Base area

132‧‧‧Doped area

140‧‧‧First doped area

142‧‧‧ fifth doping area

150‧‧‧Second doped area

152‧‧‧ sixth doping area

154, 156‧‧‧Doped area

168, 172, 174‧‧ ‧ well area

170‧‧‧ Third doped area

190‧‧‧Top doped area

200‧‧‧Insulated gate bipolar transistor

300‧‧‧Gold oxygen semi-transistor

Claims (10)

A semiconductor device comprising: a deep doped region having a first conductivity type, comprising a first buried layer and a second high voltage doped region, and located in a substrate; a first well having a second conductivity type a region, located in the deep doped region; a substrate region having the first conductivity type, located in the first well region, not connected to the deep doped region; an insulating gate bipolar transistor located in the substrate region On the first well region of a first side, and including a first doped region having the second conductivity type in the base region; and a MOS transistor, located in the base region The first well region and the deep doped region on the two sides, and a second doped region having the second conductivity type located in the base region. The semiconductor device according to claim 1, further comprising a second buried layer having the second conductivity type between the first buried layer and the substrate. The semiconductor device of claim 1, further comprising a second well region having the second conductivity type, located in the first well region, wherein the base region is located in the second well region. The semiconductor device of claim 1, wherein the insulating gate bipolar transistor further comprises: an isolation structure located in the first well region; and a gate structure located at a first portion of the isolation structure The first well region on the side covers a portion of the isolation structure and a portion of the substrate region adjacent to the first doped region; a third doped region having the first conductivity type is located in the isolation structure a first doping region having a second conductivity type; a fourth doping region having the second conductivity type, located in the first well region between the third doping region and the isolation structure, and a third doped region is in contact; and a top doped region having the first conductivity type is located below the isolation structure. The semiconductor device of claim 4, wherein the top doped region extends from below the isolation structure to below the fourth doped region and is in contact with the fourth doped region. The semiconductor device of claim 4, wherein the top doped region extends from below the isolation structure to below the third doped region and is in contact with the third doped region and the fourth doped region. . A method of fabricating a semiconductor device, comprising: forming a deep doped region having a first conductivity type in a substrate, the deep doped region comprising a first buried layer and a second high voltage doped region; Forming a first well region having a second conductivity type in the impurity region; forming a base region having the first conductivity type in the first well region, the substrate region not being connected to the deep doped region; Forming an insulating gate bipolar transistor on the first well region on a first side of the base region, and forming the insulating gate bipolar transistor includes forming a first doping having the second conductivity type in the base region And forming a MOS semi-transistor on the first well region and the deep doped region on a second side of the base region, and forming the MOS semi-transistor comprises forming the same in the matrix region A second doped region of the second conductivity type. The method of manufacturing a semiconductor device according to claim 7, further comprising forming a second buried layer having the second conductivity type between the first buried layer and the substrate. The method for manufacturing a semiconductor device according to claim 7, further comprising forming a second well region having the second conductivity type in the first well region, wherein the base region is located in the second well region . The method of manufacturing the semiconductor device of claim 7, wherein the forming the insulating gate bipolar transistor further comprises: forming an isolation structure in the first well region; on a first side of the isolation structure Forming a gate structure on the first well region to cover a portion of the isolation structure and a portion of the substrate region adjacent to the first doped region; the first well region on a second side of the isolation structure Forming a third doped region having the first conductivity type; forming a fourth doped region having the second conductivity type in the first well region between the third doped region and the isolation structure The fourth doped region is in contact with the third doped region; and a top doped region having the first conductivity type is formed under the isolation structure.