TWI531064B - Lateral diffusion metal oxide semiconductor transistor structure - Google Patents

Description

Laterally diffused metal oxide semiconductor transistor structure

The present invention relates to a semiconductor device, and more particularly to a Lateral Diffusion Metal Oxide Semiconductor (LDMOS) transistor structure.

The laterally diffused metal oxide semiconductor device has low impedance and high breakdown voltage and has been widely used, for example, in display panels, telecommunication systems, motor controllers, switch lock power supplies, or inverters, etc. Among products that require high pressure operation.

A typical laterally diffused metal oxide semiconductor transistor component is essentially an asymmetric power metal-oxide-semiconductor field effect transistor (MOSFET) constructed in an epitaxial (or implant) layer within a substrate. It has a gate and a drain and source region that are separated by the channel region and are coplanar with each other. The drain is formed in a drift region formed by a Lightly Doped Drain (LDD) process, and the drain region is separated from the channel region by a drift region. Between the gate and the drain, it is laterally isolated by Field Oxide (FOX). When the component is operated at high voltage, the drift region with the longer lateral depletion region and the thick field oxide layer can be utilized to reduce the electric field strength near the drain and increase the breakdown voltage, thereby achieving the withstand voltage effect.

However, as the critical dimensions of components shrink, it is prone to parasitic bipolar effects, which causes parasitic transistor breakdown. Therefore, there is a need to provide an advanced laterally diffused metal oxide semiconductor transistor structure to solve the problems faced by the prior art. Problem to improve the performance of semiconductor components.

One aspect of the present invention is to provide a laterally diffused metal oxide semiconductor transistor structure comprising: a buried layer, a second electrical semiconductor layer, a source, a first drain, and an isolation ring. The buried layer has a first electrical property and is located in the substrate. The second electrically conductive semiconductor layer is located above the buried layer. The source has a first electrical region and a second electrical region formed in the second electrical semiconductor layer. The first drain is formed in the second electrical semiconductor layer and has a second electrical drift region. The spacer ring has a first electrical property, and extends downward from the upper surface of the second electrical semiconductor layer to contact the buried layer, and surrounds the source and the first drain, and is in electrical contact with the source.

In an embodiment of the invention, the first electrical property is an N-type and the second electrical property is a P-type.

In an embodiment of the invention, the buried layer comprises a phosphorus/germanium/phosphorus (P/Sb/P) three-layer doped structure.

In an embodiment of the invention, the first electrical region and the second electrical region are located in an N-well located in the second electrical semiconductor layer and in contact with the buried layer.

In an embodiment of the invention, the N well comprises an N-type body and a high-pressure N-type well region; the first electrical region and the second electrical region are located in the N-type body; and the N-type body is located at the high voltage N In the well area.

In an embodiment of the invention, the doping concentration of the second electrical drift region is substantially higher than the doping concentration of the second electrical semiconductor layer.

In an embodiment of the invention, the laterally diffused metal oxide semiconductor transistor structure further includes a first gate over the second electrical semiconductor layer. its The first gate is partially disposed over the first field oxide layer and separated from the first drain by a first field oxide layer (Field Oxide, FOX).

In an embodiment of the invention, the laterally diffused metal oxide semiconductor transistor structure further includes a second drain formed in the second electrical semiconductor layer, and a second gate over the second electrical semiconductor layer pole. The second gate is partially disposed over the second field oxide layer and separated from the second drain by the second field oxide layer.

In an embodiment of the invention, the source is a common source of the first drain and the second drain, and the first drain and the second drain are symmetric with each other.

In an embodiment of the invention, the first electrical region divides the second electrical region into two.

In an embodiment of the invention, the spacer ring has a decreasing doping concentration from the upper surface of the second electrical semiconductor layer to the buried layer.

In an embodiment of the invention, the isolation ring is in electrical contact with the source by an interconnect or wire.

In an embodiment of the invention, the first electrical property is a P-type and the second electrical property is an N-type. In an embodiment of the invention, the buried layer comprises a boron/indium/boron (B/In/B) three-layer doped structure.

According to the above embodiments, the present invention provides a laterally diffused metal oxide semiconductor transistor structure which is formed in a semiconductor substrate, forms an isolation ring surrounding the source and the drain, and forms the spacer ring and the substrate. The buried layer is in contact. Wherein, the isolation ring and the buried layer have the same electrical property and are in electrical contact with the source. The isolation ring and the buried layer can be formed to form an isolation structure with the source equipotential to surround the laterally diffused metal oxide semiconductor transistor to prevent parasitic bipolar transistors in the device from being latched with other integrated circuit components ( Latch up) phenomenon. The conventional technology is solved, and the critical size is reduced, which is prone to parasitic transistor breakdown. At the same time, the breakdown voltage of the laterally diffused metal oxide semiconductor transistor structure is increased, the on-resistance (Ron) is lowered, and the performance of the semiconductor device is improved.

The present invention is to provide a laterally diffused metal oxide semiconductor transistor structure, which solves the problem that the prior art is prone to parasitic transistor breakdown due to the critical size reduction. The above and other objects, features and advantages of the present invention will become more apparent and understood. A detailed description is as follows.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing the structure of a laterally diffused metal oxide semiconductor transistor structure 100 according to an embodiment of the invention. The laterally diffused metal oxide semiconductor transistor structure 100 includes a substrate 101, a buried layer 102, a P-type semiconductor layer 103, a gate 104, a source 105, a drain 106, a field oxide layer 107, an isolation ring 108, and a gate dielectric. Electrical layer 109.

The substrate 101 is a semiconductor substrate, preferably a tantalum substrate. The buried layer 102 is an N-type doped layer formed in the substrate 101. In some embodiments of the invention, the buried layer 102 extends downwardly from the surface 101a of the substrate 101 into the substrate 101, and the buried layer 102 includes at least two dopants, phosphorus and germanium. In the present embodiment, the buried layer 102 is composed of a phosphorus/germanium/phosphorus three-layer doped structure. The doping concentration of the germanium doped layer 102a is substantially higher than the doping concentration of the other two phosphorus doped layers 102b and 102c.

In some embodiments of the present invention, the thickness of the buried layer 102 is substantially about 3 μm, and the phosphorus/germanium/phosphorus three-layer doping structure is sequentially deposited by at least three independent dopant implantation processes. /锑/phosphorus dopant is implanted in the substrate 101. But in another In some embodiments, a phosphorus doped layer is first formed in the substrate 101, and then the germanium dopant is implanted into the phosphorus doped layer to form the germanium doped layer 102a. The impurity layer is divided into two (i.e., differentiated into phosphorus doped layers 102b and 102c).

The P-type semiconductor layer 103 is an epitaxial layer formed over the substrate 101. The epitaxial layer is above the buried layer 102 and is in contact with the buried layer 102. In an embodiment of the invention, the P-type semiconductor layer 103 is doped with a P-type dopant, such as boron (B+) doped ions, and has a thickness of substantially 7 μm.

The source 105 has a P-type region 105a and an N-type region 105b, which are located in an N-type well 110 in the P-type semiconductor layer 103. In some embodiments of the invention, the N-type well 110 includes an N-type body region 110a (denoted by N-Body) and a high pressure N-type well region 110b (represented by HVDNW). The N-type body 110a is located in the high-pressure N-type well region 110b; and the P-type region 105a and the N-type region 105b are located in the N-type body 110a. In this embodiment, the N-type region 105b is an N-type highly doped region (represented by N+), the P-type region 105a is a P-type highly doped region (indicated by P+); the N-type region 105b has a substantially higher The doping concentration of the N-type body 110a; and the N-type body 110a has a doping concentration substantially higher than the high-pressure N-type well region 110b.

The drain 106 is also formed in the P-type semiconductor layer 103 and has a P-type highly doped region 106a (indicated by P+) and a P-type drift region 106b (indicated by P-Drift). Among them, the P-type highly doped region 106a is located in the P-type drift region 106b. In addition, the doping concentration of the P-type highly doped region 106a is substantially higher than the doping concentration of the P-type drift region 106b; and the doping concentration of the P-type drift region 106b is substantially higher than the doping concentration of the P-type semiconductor layer 103. .

The gate dielectric layer 109 covers the source 105 and a portion of the P-type semiconductor layer 103. The field oxide layer 107 is formed in the P-type semiconductor layer 103 and partially protrudes from the surface 103a of the P-type semiconductor layer 103. Gate 104 is located in the gate Above the electrical layer 109, and partially over the field oxide layer 107, and separated from the drain 106 by the field oxide layer 107.

The isolation ring 108 is a doped region having an N-type electrical conductivity, extending from the surface 103a of the P-type semiconductor layer 103 into the P-type semiconductor layer 103, and in contact with the buried layer 102, and surrounding the source 105 and the drain 106, and is in electrical contact with the source 106 through, for example, an interconnect, a wire 111, or other conductive structure. In some embodiments of the invention, the isolation ring 108 includes an N-type highly doped region 108a (denoted by N+), an N-type well region 108b (denoted by NW), and an N-type drift region 108c (with N- Drift) and a high pressure N-well zone 108d (represented by HVDNW).

Wherein, the N-type highly doped region 108a extends downward from the surface 103a of the P-type semiconductor layer 103 into the N-type well region 108b; the N-type well region 108b is located in the N-type drift region 108c; and the N-type drift region 108c is located at the high-voltage N In the well area 108d. The doping concentration of the N-type highly doped region 108a is greater than the doping concentration of the N-type well region 108b; the doping concentration of the N-type well region 108b is greater than the doping concentration of the N-type drift region 108c; and the N-type drift region 108c The doping concentration is greater than the doping concentration of the high pressure N-type well region 108d. That is, the spacer ring 108 has a doping concentration which is decreased by the surface 103a of the P-type semiconductor layer 103 toward the buried layer 102.

Because the isolation ring 108 and the buried layer 102 both have the same N-type electrical property, and are in electrical contact with the N-type region 105b of the source. Therefore, by the isolation ring 108 and the buried layer 102, an isoelectric isolation structure with the source 105 can be formed in the P-type semiconductor layer 103 to prevent parasitic bipolar transistors in the P-type semiconductor layer 103, and Other integrated circuit components (not shown) create a latch-up phenomenon. The breakdown voltage of the laterally diffused metal oxide semiconductor transistor structure 100 can be further improved, and at the same time, the on-resistance thereof is lowered, and the performance of the semiconductor element is improved.

Please refer to FIG. 2, which illustrates a lateral view according to another embodiment of the present invention. A cross-sectional view of the structure of the diffusion metal oxide semiconductor transistor structure 200. The structure of the laterally diffused metal oxide semiconductor transistor structure 200 is substantially similar to the laterally diffused metal oxide semiconductor transistor structure 100. The difference is that the laterally diffused metal oxide semiconductor transistor structure 200 further includes another gate 204 and drain 206. For the sake of convenience of explanation, elements similar to those in FIG. 1 in FIG. 2 will be denoted by the same reference numerals.

In the present embodiment, the drain 106 and the drain 206 share the source 205, and the drain 106 and the drain 206 are symmetric with each other. The source 205 includes two P-type regions 205a and 205c and an N-type region 205b, all of which are located in the N-type well 110 in the P-type semiconductor layer 103; and the N-type region 205b will have two P-type regions 205a and 205c. Separated by. N-type region 205b is an N-type highly doped region (represented by N+), P-type regions 205a and 205c are P-type highly doped regions (represented by P+); and N-type region 205b has substantially higher than N-type body 110a Doping concentration.

The drain electrode 206 is formed in the P-type semiconductor layer 103, and has a P-type highly doped region 206a (indicated by P+) and a P-type drift region 206b (indicated by P-Drift), and the P-type highly doped region 206a is located. In the P-type drift zone 206b. In addition, the doping concentration of the P-type highly doped region 206a of the drain 206 is substantially higher than the doping concentration of the P-type drift region 206b; and the doping concentration of the P-type drift region 206b is substantially higher than that of the P-type semiconductor layer 103. Doping concentration. The gate 204 is over the gate dielectric layer 109 and partially overlying the field oxide layer 107 and is separated from the drain 206 by the field oxide layer 107.

Similarly, since the isolation ring 108 and the buried layer 102 both have the same N-type electrical property and are in electrical contact with the N-type region 205b of the source electrode 205, the isolation ring 108 and the buried layer 102 can be used in the P-type semiconductor layer. In 103, an isolation structure having the same potential as the source electrode 205 is formed to prevent the parasitic bipolar transistor in the P-type semiconductor layer 103 from being latched, and the breakdown voltage of the laterally diffused metal oxide semiconductor transistor structure 200 can be improved. And at the same time reduce its on-resistance, increase half The effectiveness of the conductor elements.

It is to be noted that the above embodiment illustrates the technical features of the present invention only by a plurality of laterally diffused metal oxide semiconductor transistor structures having P-type channels. However, the scope of application of the present invention is not limited thereto. The technical features of the present invention can also be applied to a laterally diffused metal oxide semiconductor transistor structure having an N-type channel.

For example, please refer to FIG. 3. FIG. 3 is a cross-sectional view showing the structure of a laterally diffused metal oxide semiconductor transistor structure 300 according to still another embodiment of the present invention. The structure of the laterally diffused metal oxide semiconductor transistor structure 300 is substantially similar to the laterally diffused metal oxide semiconductor transistor structure 200. The difference is that the laterally diffused metal oxide semiconductor transistor structure 300 has an N-type channel.

The laterally diffused metal oxide semiconductor transistor structure 300 includes a substrate 301, a P-type buried layer 302, an N-type semiconductor layer 303, gates 304 and 314, a source 305, drains 306 and 316, and a field oxide layer. 307, isolation ring 308 and gate dielectric layer 309.

The buried layer 302 is a P-type doped layer located in the substrate 301. The buried layer 302 includes at least two dopants of boron and indium (In). Although in the present embodiment, the buried layer 302 is illustrated as a single layer structure, in some embodiments of the present invention, the buried layer 302 may be composed of a boron/indium/boron three-layer doped structure. The doping concentration of the indium doped layer (not shown) is substantially higher than the doping concentration of the other two boron doped layers (not shown).

The N-type semiconductor layer 303 is an epitaxial layer formed over the substrate 301. The epitaxial layer is above the buried layer 302 and is in contact with the buried layer 302.

Source 305 includes two N-type regions 305a and 305c and a P-type region 305b located in P-well 310 in N-type semiconductor layer 303. P-well 310, including a P-type The body 310a (indicated by P-Body) and a high pressure P-type well zone 310b (indicated by HVDPW). P-type body 310a is located in high-pressure P-type well region 310b; N-type regions 305a and 305c and P-type region 305b are located in P-type body 310a; and P-type region 305b, two N-type regions 305a and The 305c is separated. P-type region 305b is a P-type highly doped region (represented by P+), N-type regions 305a and 305 are N-type highly doped regions (represented by N+, respectively); P-type region 305b has substantially higher P-type The doping concentration of the body 310a; and the doping concentration of the body 310a is substantially higher than the doping concentration of the high pressure P-type well region 310b.

The drain 306 is formed in the N-type semiconductor layer 303 and has an N-type highly doped region 306a (indicated by N+) and an N-type drift region 306b (indicated by N-Drift). The N-type highly doped region 306a is located in the N-type drift region 306b. The doping concentration of the N-type highly doped region 306a is substantially higher than the doping concentration of the N-type drift region 306b; and the doping concentration of the N-type drift region 306b is substantially higher than the doping concentration of the N-type semiconductor layer 303.

The drain 316 is formed in the N-type semiconductor layer 303 and has an N-type highly doped region (represented by N+) 316a and an N-type drift region 316b (indicated by N-Drift). The N-type highly doped region 316a is located in the N-type drift region 316b. The doping concentration of the N-type highly doped region 316a is substantially higher than the doping concentration of the N-type drift region 316b; and the doping concentration of the N-type drift region 316b is substantially higher than the doping concentration of the N-type semiconductor layer 303.

A gate dielectric layer 309 overlies the source 305 and a portion of the N-type semiconductor layer 303. A field oxide layer 307 is formed in the N-type semiconductor layer 303 and partially protrudes from the surface 303a of the N-type semiconductor layer 303. Gates 304 and 314 are respectively disposed over gate dielectric layer 309 and partially overlying field oxide layer 307, respectively, and are separated from drain electrodes 306 and 316 by field oxide layer 307, respectively.

The isolation ring 308 is a doped region having a P-type electrical property, and is made of an N-type semiconductor. The surface 303a of the layer 303 extends downward into the N-type semiconductor layer 303, contacts the buried layer 302, and surrounds the source 305 and the drain 306, and is transmitted through, for example, an interconnect, a wire or other conductive structure 311, and a source. The pole 306 is in electrical contact. In some embodiments of the invention, the isolation ring 308 includes a P-type highly doped region 308a (denoted by P+), a P-type well region 308b (denoted by PW), and a P-type drift region 308c (with P-). Drift) and a high pressure P-well 308d (represented by HVDPW).

Wherein, the P-type highly doped region 308a extends from the surface 303a of the N-type semiconductor layer 303 to the P-type well region 308b; the P-type well region 308b is located in the P-type drift region 308c; and the P-type drift region 308c is located at the high voltage P In the well area 308d. The doping concentration of the P-type highly doped region 308a is greater than the doping concentration of the P-type well region 308b; the doping concentration of the P-type well region 308b is greater than the doping concentration of the P-type drift region 308c; and the P-type drift region 308c The doping concentration is greater than the doping concentration of the high pressure P-type well region 308d.

Since the isolation ring 308 and the buried layer 302 both have the same P-type electrical property and are in electrical contact with the P-type region 305b of the source, the isolation ring 308 and the buried layer 302 may be in the N-type semiconductor layer 303. Forming an isolating structure equal to the source 305 for preventing the parasitic bipolar transistor in the N-type semiconductor layer 303 from being latched, which can increase the breakdown voltage of the laterally diffused metal oxide semiconductor transistor structure 300 while reducing its conduction. Resistance to improve the performance of semiconductor components.

According to the above embodiments, the present invention provides a laterally diffused metal oxide semiconductor transistor structure which is formed in a semiconductor substrate, forms an isolation ring surrounding the source and the drain, and forms the spacer ring and the substrate. The buried layer is in contact. Wherein, the isolation ring and the buried layer have the same electrical property and are in electrical contact with the source. The isolation ring and the buried layer can be formed to form an isolation structure with the source equipotential to surround the lateral diffusion metal oxide semiconductor transistor to prevent parasitic bipolar in the device. The transistor generates a latch up phenomenon with other integrated circuit components. The conventional technology is solved, and the critical size is reduced, which is prone to parasitic transistor breakdown. At the same time, the breakdown voltage of the laterally diffused metal oxide semiconductor transistor structure is increased, the on-resistance (Ron) is lowered, and the performance of the semiconductor device is improved.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. For example, the material for forming the epitaxial structure of the compound semiconductor is not limited to the germanium epitaxial material; and the application range of the epitaxial structure of the compound semiconductor is not limited to the metal oxide semiconductor field effect transistor element. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Transversely diffused metal oxide semiconductor crystal structure

101‧‧‧Substrate

101a‧‧‧Substrate surface

102‧‧‧buried layer

102a‧‧‧锑Doped layer

102b‧‧‧phosphorus doped layer

102c‧‧‧phosphorus doped layer

103‧‧‧P type semiconductor layer

103a‧‧‧ Surface of P-type semiconductor layer

104‧‧‧ gate

105‧‧‧ source

105a‧‧‧P type area

105b‧‧‧N-zone

106‧‧‧汲polar

106a‧‧‧P type highly doped area

106b‧‧‧P type drift zone

107‧‧‧Field oxide layer

108‧‧‧Isolation ring

108a‧‧‧N type highly doped area

108b‧‧‧N type well area

108c‧‧‧N type drift zone

108d‧‧‧High pressure N-type well area

109‧‧‧gate dielectric layer

110‧‧‧N type well

110a‧‧‧N-type subject

110b‧‧‧High pressure N-well area

111‧‧‧Line

200‧‧‧Transversely diffused metal oxide semiconductor crystal structure

204‧‧‧ gate

205‧‧‧ source

205a‧‧‧P type area

205b‧‧‧N-zone

205c‧‧‧P type area

206‧‧‧汲polar

206a‧‧‧P type highly doped area

206b‧‧‧P type drift zone

300‧‧‧Transversely diffused metal oxide semiconductor crystal structure

301‧‧‧Substrate

302‧‧‧buried layer

303‧‧‧N type semiconductor layer

303a‧‧‧N type semiconductor layer surface

304‧‧‧ gate

305‧‧‧ source

305a‧‧‧N-zone

305b‧‧‧P type area

305c‧‧‧N-zone

306‧‧‧汲polar

306a‧‧‧N type highly doped area

306b‧‧‧N type drift zone

307‧‧ ‧ field oxide layer

308‧‧‧Isolation ring

308a‧‧‧P type highly doped area

308b‧‧‧P type well area

308c‧‧‧P type drift zone

308d‧‧‧High pressure P-well area

309‧‧‧gate dielectric layer

310‧‧‧P type well

310a‧‧‧P-type subject

310b‧‧‧High pressure P-well area

311‧‧‧Electrical structure

314‧‧‧ gate

316‧‧‧汲polar

316a‧‧‧N type highly doped area

316b‧‧‧N type drift zone

1 is a cross-sectional view showing the structure of a laterally diffused metal oxide semiconductor transistor structure according to an embodiment of the present invention.

2 is a cross-sectional view showing the structure of a laterally diffused metal oxide semiconductor transistor structure according to another embodiment of the present invention.

3 is a cross-sectional view showing the structure of a laterally diffused metal oxide semiconductor transistor structure according to still another embodiment of the present invention.

100‧‧‧Transversely diffused metal oxide semiconductor crystal structure

101‧‧‧Substrate

101a‧‧‧Substrate surface

102‧‧‧buried layer

102a‧‧‧锑Doped layer

102b‧‧‧phosphorus doped layer

102c‧‧‧phosphorus doped layer

103‧‧‧P type semiconductor layer

103a‧‧‧ Surface of P-type semiconductor layer

104‧‧‧ gate

105‧‧‧ source

105a‧‧‧P type area

105b‧‧‧N-zone

106‧‧‧汲polar

106a‧‧‧P type highly doped area

106b‧‧‧P type drift zone

107‧‧‧Field oxide layer

108‧‧‧Isolation ring

108a‧‧‧N type highly doped area

108b‧‧‧N type well area

108c‧‧‧N type drift zone

108d‧‧‧High pressure N-type well area

109‧‧‧gate dielectric layer

110‧‧‧N type well

110a‧‧‧N-type subject

110b‧‧‧High pressure N-well area

111‧‧‧Electrical structure

Claims (14)

A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) transistor structure includes: a buried layer having a first electrical property, located in a substrate, wherein the buried layer is three-layer doped Constructed by a structure, and the three-layer doped structure is composed of two first doped layers and a second doped layer, the second doped layer is located between the two first doped layers, the second The doping layer has a doping concentration greater than a doping concentration of the first doping layer; a second electrically conductive semiconductor layer is located above the buried layer; and a source having a first electrical region and a second electrical property a region formed in the second electrical semiconductor layer; a first drain formed in the second electrical semiconductor layer and having a second electrical drift region; and an isolation ring having a first electrical And extending from an upper surface of the second electrical semiconductor layer to contact the buried layer and surrounding the source and the first drain and electrically contacting the source. The laterally diffused metal oxide semiconductor transistor structure of claim 1, wherein the first electrical property is an N-type and the second electrical property is a P-type. The laterally diffused metal oxide semiconductor transistor structure of claim 2, wherein the buried layer comprises a phosphorus/germanium/phosphorus (P/Sb/P) three-layer doped structure. The lateral diffusion metal oxide half as described in claim 2 a conductor transistor structure, wherein the first electrical region and the second electrical region are located in an N-well; the N-well is located in the second electrical semiconductor layer and is in contact with the buried layer. The laterally diffused metal oxide semiconductor transistor structure of claim 4, wherein the N well comprises an N-type body and a high-pressure N-type well region; the first electrical region and the second electrical region Located in the N-type body; and the N-type body is located in the high-pressure N-type well region. The laterally diffused metal oxide semiconductor transistor structure of claim 1, wherein the doping concentration of the second electrical drift region is substantially higher than the doping concentration of the second electrical semiconductor layer. The laterally diffused metal oxide semiconductor transistor structure of claim 1, further comprising a first gate on the second electrical semiconductor layer and partially immersed in a first field oxide Above the layer (Field Oxide, FOX), and separated from the first drain by the first field oxide layer. The laterally diffused metal oxide semiconductor transistor structure of claim 7, further comprising: a second drain formed in the second electrical semiconductor layer; and a second gate located at the first The second electrical semiconductor layer is partially disposed over a second field oxide layer and separated from the second drain by the second field oxide layer. The lateral diffusion metal oxide half as described in claim 8 The conductor transistor structure, wherein the source is a common source of the first drain and the second drain, and the first drain and the second drain are symmetric with each other. The laterally diffused metal oxide semiconductor transistor structure of claim 9, wherein the first electrical region divides the second electrical region into two. The laterally diffused metal oxide semiconductor transistor structure of claim 1, wherein the spacer ring has a doping concentration that decreases from the upper surface of the second electrical semiconductor layer toward the buried layer. The laterally diffused metal oxide semiconductor transistor structure of claim 1, wherein the spacer ring is in electrical contact with the source via an interconnect or a wire. The laterally diffused metal oxide semiconductor transistor structure of claim 1, wherein the first electrical property is a P-type and the second electrical property is an N-type. The laterally diffused metal oxide semiconductor transistor structure of claim 13, wherein the buried layer comprises a boron/indium/boron (B/In/B) three-layer doping structure.