TWI646653B - Laterally diffused metal oxide semiconductor field effect transistor - Google Patents

Abstract

An embodiment of the present invention provides a laterally diffused metal oxide semiconductor field effect transistor including: a body region, which is located above the substrate, and has a first conductivity type; a drift region, which is located above the substrate, and has a second conductivity type; the body region and drift A first isolation region is provided between the regions; a gate electrode is located on the substrate; a source region is located in the body region; a drain region is located in the drift region, and the first drain region and the second drain region are arranged adjacent to each other. A first drain region having a second conductivity type and a second drain region having a first conductivity type; a second isolation region provided in a drift region between the first isolation region and the drain region; and a first The doped region is located in the substrate between the first isolation region and the second isolation region and has a first conductivity type; the first doped region and the drift region form a first diode.

Description

Laterally diffused metal oxide semiconductor field effect transistor

Embodiments of the present invention relate to a semiconductor technology, and particularly to a laterally diffused metal oxide semiconductor field effect transistor.

The high-voltage semiconductor element is suitable for the field of integrated circuits of high voltage and high power. A conventional high-voltage semiconductor device includes a lateral diffused metal oxide semiconductor (LDMOS). The advantage of high-voltage semiconductor components is that they are easily compatible with other processes and are cost-effective. Therefore, they are widely used in power supply, power management, display drive IC components, communications, automotive electronics, industrial control and other fields.

When a laterally diffused metal oxide semiconductor field effect transistor is connected to an AC power source, a large amount of electrostatic charges may accumulate, and these electrostatic charges may flow at any two ends, resulting in electrostatic discharge (ESD). Current. If the electrostatic discharge current is not properly controlled, it may burn the integrated circuit and cause damage to the components. For example, if the electrostatic discharge current flows from the drain to the source of the element, it may also flow to the gate of the element, causing damage to the gate.

In summary, although the existing laterally diffused metal oxide semiconductor field effect transistors are generally in line with the requirements, they are not satisfactory in all aspects. The electrostatic discharge current of a laterally diffused metal oxide semiconductor field effect transistor still needs to be further improved.

An embodiment of the present invention provides a laterally diffused metal oxide semiconductor field effect transistor, which includes a substrate having a first conductivity type; a body region located above the substrate; the body region having the first conductivity type; and a drift region ( drift region), located on the upper part of the substrate, a first isolation region is provided between the body region and the drift region, and the drift region has a second conductivity type opposite to the first conductivity type; the gate electrode is located on the substrate and partially covers the body Source region, located in the body region, the source region has a second conductivity type; drain region, located in the drift region, includes a first drain region and a second drain region adjacent to each other, the first drain region Region has a second conductivity type, and the second drain region has a first conductivity type; a second isolation region is provided in the drift region between the first isolation region and the drain region; a first doped region is located at the first In the substrate between the isolation region and the second isolation region, the first doped region has a first conductivity type; wherein the first doped region and the drift region form a first diode.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.

100, 200, 300, 400, 500, 600‧‧‧ laterally diffused metal oxide semiconductor field effect transistors

102‧‧‧ substrate

104‧‧‧Body area

106‧‧‧ Drifting Zone

106E‧‧‧Edge

108‧‧‧Source area

110‧‧‧first drain region

112‧‧‧Second Drain Region

114, 114A, 114B ‧‧‧ doped regions

116‧‧‧base region

118, 118A, 118B, 118C

120‧‧‧Gate

122‧‧‧ Interlayer dielectric layer

124‧‧‧contact

126‧‧‧ Metal

228‧‧‧well area

330, 530‧‧‧Top doped regions

DA, DB‧‧‧ Distance

D, D1, D2‧‧‧‧diodes

TH, TH1, TH2‧‧‧Horizontal Bipolar Transistors

TV‧‧‧Vertical Bipolar Transistor

AA ’, BB’‧‧‧ line segments

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

FIG. 1 is a top view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 2A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 2B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 3A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to other embodiments.

FIG. 3B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to other embodiments.

FIG. 4A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 4B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 5A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 5B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 6A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 6B is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor according to still other embodiments.

FIG. 7 is a top view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 8A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 8B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, as well as in the drawings. The described orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used in it will also be interpreted in terms of the orientation after turning.

Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, In the case of "about", "approximately" and "probably", the meanings of "approximately", "approximately" and "probably" may still be implied.

An embodiment of the present invention provides a lateral diffused metal oxide semiconductor (LDMOS) field effect transistor, which is used to form a horizontal bipolar junction transistor (BJT), a vertical bipolar transistor, and a bipolar transistor. Diode, which can release electrostatic discharge (ESD) current without damaging the gate, and does not change its DC performance.

FIG. 1 illustrates a top view of a laterally diffused metal oxide semiconductor field effect transistor 100 according to some embodiments of the present invention, and FIGS. 2A and 2B illustrate a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments of the present invention. A cross-sectional view of the crystal 100. Figure 2A is a cross-sectional view along line AA 'in Figure 1 and Figure 2B is a cross-sectional view along line BB' in Figure 1.

As shown in FIG. 1, the lateral diffusion metal oxide semiconductor field effect transistor 100 includes a source 108, a first drain region 110, and a gate 120. In the embodiment shown in FIG. 1, the source region 108 and the first drain region 110 interdigitate fingers. The laterally diffused metal oxide semiconductor field effect transistor 100 further includes a doped region 114 and a second drain region 112. The doped region 114 is adjacent to the tip of the source region 108, and the second drain region 112 is located on the first drain. The recess of the region 110. The doped region 114 and the second drain region 112 help to discharge the electrostatic discharge current without damaging the gate 120 (to be described in detail later).

According to some embodiments, as shown in FIGS. 2A and 2B, the laterally diffused metal oxide semiconductor field effect transistor 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate, which may include an element semiconductor such as silicon (Si), germanium (Ge) Etc .; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc .; alloy semiconductors, such as silicon germanium alloy (SiGe), gallium arsenide (GaAsP), aluminum arsenide (AlInAs), aluminum arsenic (AlGaAs), arsenic (GaInAs), indium phosphide Gallium alloy (GaInP), GaAsAs, or a combination of the above materials. In addition, the substrate 102 may be a semiconductor on insulator substrate. In some embodiments, the substrate 102 has a first conductivity type.

According to some embodiments, as shown in FIGS. 2A and 2B, the laterally diffused metal oxide semiconductor field effect transistor 100 includes a body region 104 and a drift region 106 disposed on an upper portion of the substrate 102. In some embodiments, the body region 104 and the drift region 106 are formed by ion implanting the substrate 102 through a patterned mask. In some embodiments, the body region 104 has a first conductivity type, and the drift region 106 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type. In other embodiments, when the first conductivity type is N-type, the second conductivity type is P-type. In some embodiments, the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ion (BF ₃ ⁺ ), or a combination thereof, and the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, Or a combination of the foregoing. In some embodiments, the doping concentration of the body region 104 is between 1e16 / cm ³ and 5e18 / cm ³ , and the doping concentration of the drift region 106 is between 1e15 / cm ³ and 5e17 / cm ³ . In some embodiments, the substrate 102 shown in the top view of FIG. 1 is a substrate between the body region 104 and the drift region 106.

According to some embodiments, as shown in FIGS. 2A and 2B, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a source region 108, a first drain region 110, a second drain region 112, and a doped region. 114 and the base region 116. The first drain region 110 and the second drain region 112 are adjacently disposed in the drift region 106 adjacent to the upper surface of the substrate 102, and the first drain region 110 adjoins the second drain region 112. The source region 108 and the base region 116 are disposed in the body region 104 adjacent to the upper surface of the substrate 102, and the source region 108 adjoins the base region 116. The doped region 114 is disposed between the drift region 106 and the body region 104 adjacent to the upper surface of the substrate 102. In some embodiments, the source region 108, the first drain region 110, the second drain region 112, the doped region 114, and the base region 116 are formed by ion implanting the substrate 102 through a patterned mask. In some embodiments, the base region 116 has a first conductivity type, and its doping concentration is higher than the first conductivity type doping concentration of the body region 104. The second drain region 112 and the doped region 114 also have a first conductivity. The source region 108 and the first drain region 110 both have a second conductivity type, and their doping concentrations are higher than the second conductivity type doping concentration of the drift region 106. In some embodiments, the doping concentration of the source region 108 is between 5e19 / cm ³ and 1e21 / cm ³ , and the doping concentration of the first drain region 110 is between 5e19 / cm ³ and 1e21 / cm ³ . Meanwhile, the doping concentration of the second drain region 112 is between 1e19 / cm ³ and 1e21 / cm ³ , and the doping concentration of the base region 116 is between 5e19 / cm ³ and 1e21 / cm ³ . The doping concentration of the impurity region 114 is between 5e19 / cm ³ and 1e21 / cm ³ .

From the top view of the laterally diffused metal oxide semiconductor field effect transistor 100 in FIG. 1, the source region 108 and the first drain region 110 interdigitated fingers, and the doped region 114 is adjacent to the source electrode. The tip of the region 108 and the second drain region 112 are located in the recess of the first drain region 110. It is worth noting that the second drain region 112 and the doped region 114 are only disposed at the tip of the source region 108 (for example, at the line BB ′ cross section in FIG. 1), and are not disposed at the tip of the source region 108. Outside Ministry (For example, at the line AA 'section in Figure 1). In addition, as shown in FIGS. 2A and 2B, the distance DA between the drift region 106 and the body region 104 outside the tip of the source region 108 is smaller than the distance between the drift region 106 and the body region 104 in the source region 108. Tip distance DB.

According to some embodiments, as shown in FIGS. 2A and 2B, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a plurality of isolation regions 118A and 118B formed on the substrate 102, wherein the isolation region 118A is located in the body region 104. Between the drift region 106 and the drift region 106, the isolation region 118B is located in the drift region 106 between the isolation region 118A and the second drain region 112. In some embodiments, the isolation regions 118A and 118B may be field oxides. In some embodiments, the isolation regions 118A and 118B may be a local oxidation of silicon (LOCOS). In other embodiments, the isolation regions 118A and 118B may be shallow trench isolation (STI) structures. It is worth noting that since the doped region 114 is only provided at the tip of the source region 108, the isolation regions 118A and 118B are connected in a region other than the tip of the source region 108 (for example, at the line AA 'section in FIG. 1). And become the isolation area 118.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a gate electrode 120 located on the body region 104 and the drift region 106 and extending to cover a part of the isolation region 118. In some embodiments, as shown in FIG. 2B, the gate electrode 120 extends to cover a part of the isolation region 118A. In some embodiments, the gate 120 may include a gate dielectric layer, and a gate electrode layer (not shown) located above the gate dielectric layer. The gate dielectric layer may include a dielectric of silicon oxide, silicon nitride, silicon oxynitride, high-k (i.e., a dielectric constant greater than 3.9). Electrical materials such as HfO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba , Sr) TiO ₃ , Al ₂ O ₃ , or a combination thereof. The gate dielectric layer may use a suitable oxidation process (such as a dry oxidation process or a wet oxidation process), a deposition process (such as a chemical vapor deposition process or an atomic layer deposition (ALD) process), Other suitable processes, or a combination thereof. In some embodiments, the gate dielectric layer may use a thermal oxidation process to thermally grow in an environment containing oxygen or nitrogen (eg, containing NO or N ₂ O) to form a gate dielectric before forming the gate electrode layer. Floor.

In some embodiments, a gate electrode layer is formed on the gate dielectric layer. The gate electrode layer may include polycrystalline silicon, a metal (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, or the like, or a combination thereof), a metal alloy, and a metal nitride (such as tungsten nitride, molybdenum nitride). , Titanium nitride, tantalum nitride, analogs thereof, or a combination thereof), metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, hafnium silicide, analogs thereof, or a combination thereof) ), Metal oxide (ruthenium oxide, indium tin oxide, analogues thereof, or a combination thereof), other suitable materials, or a combination thereof. The gate electrode layer may use a chemical vapor deposition (CVD) process (such as a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition process, PECVD), physical vapor deposition (PVD) (such as resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition (ALD) , Other suitable processes, or a combination of the above to form an electrode material on the substrate 102, and then It is patterned by a shadow and etching process to form a gate electrode.

According to some embodiments, as shown in FIG. 1, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes an interlayer dielectric (ILD) 122 covering the substrate 102. The interlayer dielectric layer 122 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG) Borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other applicable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, bis-benzocyclobutenes (BCB), or polyimide. The interlayer dielectric layer 122 may use chemical vapor deposition (CVD) (such as high-density plasma chemical vapor deposition (HDPCVD), atmospheric pressure chemical vapor deposition). (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) ), Atomic layer deposition (ALD), spin-on coating, other suitable technologies, or a combination thereof.

According to some embodiments, as shown in FIG. 1, the lateral diffusion metal The oxide semiconductor field effect transistor 100 further includes an interconnect structure. The interconnect structure includes a metal 126 disposed on the interlayer dielectric layer 122 and a contact 124 passing through the interlayer dielectric layer 122. In some embodiments, the metal 126 is electrically connected to the source region 108, the first drain region 110, the second drain region 112, the doped region 114, and the base region 116 through the contact 124, and the source region is respectively provided. 108. The first drain region 110, the second drain region 112, the doped region 114, and the base region 116 have suitable operating voltages. In some embodiments, the doped region 114 is grounded through the interconnect structure.

In some embodiments, a lithography process (e.g., covering photoresist, soft baking, exposure, post-exposure baking, development, other suitable techniques, or a combination thereof) and an etching process (e.g., wet etching) may be used Processes, dry etching processes, other suitable technologies, or combinations thereof), other suitable technologies, or combinations thereof to form openings in the interlayer dielectric layer 122 (not shown). Next, a conductive material is filled in the opening to form a contact 124. In some embodiments, the conductive material of the contact 124 includes a metal material (such as tungsten, aluminum, or copper), a metal alloy, polycrystalline silicon, other suitable materials, or a combination thereof. The contact 124 may use a physical vapor deposition (PVD) process (eg, a vapor deposition method or a sputtering method), an electroplating method, an atomic layer deposition (ALD) process, other suitable processes, or the foregoing. The conductive material is deposited in combination, and chemical mechanical polishing (CMP) or etch-back is selectively performed to remove excess conductive material to form the contact 124.

In some embodiments, before filling the conductive material of the contact 124, a barrier layer (not shown) may be formed on the sidewall and bottom of the opening to prevent the conductive material of the contact 124 from diffusing into the interlayer dielectric layer. 122. The material of the barrier layer can be titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), nitrogen Tungsten (WN), other suitable materials, or a combination thereof. The barrier layer can be deposited by a physical vapor deposition process (such as an evaporation method or a sputtering method), an atomic layer deposition process, an electroplating method, other suitable processes, or a combination thereof.

In some embodiments, the metal 126 is formed over the interlayer dielectric layer 122. In some embodiments, the metal 126 may include Cu, W, Ag, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, other suitable Metal material, the alloy described above, or a combination thereof. In some embodiments, the metal 126 may include a stacked structure of Ti / TiN / AlCu / TiN. In some embodiments, a blanket is formed on the interlayer dielectric layer 122 by a physical vapor deposition process (such as a vapor deposition method or a sputtering method), an electroplating method, an atomic layer deposition process, other suitable processes, or a combination thereof. (blanket) metal layer (not shown). Then, the blanket metal layer is patterned by a patterning process to form the metal 126. In some embodiments, the patterning process includes a lithography process (such as covering photoresist, soft baking, exposure, post-exposure baking, development, other suitable techniques, or a combination thereof), an etching process (such as Wet etching process, dry etching process, other suitable technologies, or a combination thereof), other suitable technologies, or a combination thereof.

In the embodiments shown in FIGS. 1 and 2A to 2B, a doped region 114 and a second drain region 112 are provided at the tip of the source region 108, and a second drain region can be formed in the semiconductor substrate 102, respectively. 112. A horizontal bipolar transistor TH composed of the drift region 106 and the doped region 114, a vertical bipolar transistor TV composed of the second drain region 112, the drift region 106, and the substrate 102, and doped with Diode D formed by region 114 and drift region 106.

In some embodiments, the doped region 114 is grounded. Therefore, when an electrostatic discharge occurs, the electrostatic discharge current may pass through the horizontal bipolar transistor TH, vertical The straight bipolar transistor TV and the diode D are released without flowing to the gate 120 to avoid causing damage to the gate 120. In addition, in some embodiments, as shown in FIG. 2B, at the tip of the source region 108, the distance DB between the edge 106E of the drift region 106 and the body region is greater than the distance DA from the region outside the tip of the source region 108. In this way, the magnitude of the electric field can be reduced, and the breakdown voltage, high temperature reverse bias (HTRB), and the performance of electrostatic discharge can be improved.

In some embodiments, to avoid excessive current density at the tip of the source region 108, there is a large space between the source region 108 and the first drain region 110 at the tip of the source region 108 (as shown in FIG. 2B). To reduce the electric field. In this way, the tip portion of the source region 108 has enough space to set the doped region 114 and the second drain region 112 to release the electrostatic discharge current. Conversely, in the area other than the tip of the source region 108 (as shown in FIG. 2A), because the electric field is small, the space between the source region 108 and the first drain region 110 is small, so the doped region 114 and the first region are not provided. Second drain region 112.

It should be noted that the laterally diffused metal oxide semiconductor field effect transistor 100 shown in FIG. 1 is only an example, but the embodiment of the present invention is not limited thereto. In some embodiments, the source region 108 may have other suitable shapes according to design or product requirements. By adjusting the ratio of the straight portion to the curved portion in the shape of the laterally diffused metal oxide semiconductor field effect transistor, the overall electric field distribution can be adjusted, and the breakdown voltage of the device can be further adjusted.

3A and 3B are cross-sectional views illustrating a laterally diffused metal oxide semiconductor field effect transistor 200 according to some embodiments of the present invention according to some embodiments. FIG. 3A is a cross-sectional view along line AA ′ in FIG. 1, and FIG. 3B is a cross-sectional view along line BB ′ in FIG. 1. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the foregoing embodiment is that a well region 228 is provided at the tip of the source region 108. The well region 228 is located in the drift region 106 and surrounds the first drain region 110 and the second drain region 112. In some embodiments, before the first drain region 110 and the second drain region 112 are formed, the substrate 102 may be ion-implanted through a patterned mask to form a well region 228. In some embodiments, the well region 228 has a second conductivity type, and its doping concentration is higher than the second conductivity type doping concentration of the drift region 106. In some embodiments, the doping concentration of the well region 228 is between 1e17 / cm ³ and 5e18 / cm ³ .

Since the well region 228 is disposed only at the tip of the source region 108 and is not disposed at a region other than the tip of the source region 108 (as shown in FIG. 3A), in some embodiments, the laterally diffused metal oxide semiconductor The cross-sectional view of the field effect transistor 200 along the line segment AA ′ (FIG. 3A) is the same as the cross-sectional view of the laterally diffused metal oxide semiconductor field effect transistor 100 along the line segment AA ′ in the embodiment of FIG. 2A.

In the embodiment shown in FIGS. 3A and 3B, the higher doping concentration of the well region 228 can further reduce the resistance value, so that when an electrostatic discharge occurs, it is more inclined to pass the horizontal bipolar transistor TH, vertical The bipolar transistor TV and the diode D release an electrostatic discharge current without flowing to the gate electrode 120 to avoid causing damage to the gate electrode 120.

4A and 4B are cross-sectional views illustrating a laterally diffused metal oxide semiconductor field effect transistor 300 according to some embodiments of the present invention according to some embodiments. FIG. 4A is a cross-sectional view along line AA ′ in FIG. 1, and FIG. 4B is a cross-sectional view along line BB ′ in FIG. 1. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that, as shown in FIG. 4B, a top doping region 330 is provided in the substrate 102 below the isolation region 118B at the tip of the source region 108, and as shown in FIG. 4A It is shown that, in a region other than the tip of the source region 108, a top doped region 330 is also provided in the substrate 102 below the isolation region 118. In some embodiments, before forming the isolation regions 118A, 118B, and 118, the substrate 102 may be ion-implanted through the patterned mask to form the top doped region 330. In some embodiments, the top doped region 330 has a first conductivity type. In some embodiments, the doping concentration of the top doped region 330 is between 1e16 / cm ³ and 5e18 / cm ³ . In some embodiments, the area of the top doped region 330 is smaller than the area of the isolation region 118. In some embodiments, the top doped region 330 is not adjacent to the first drain region 110, the second drain region 112, and the body region 104, but is in contact with the first drain region 110, the second drain region 112, and The body regions 104 are separated by a distance. In some embodiments, some or all of the top doped region 330 is located in the drift region 106. In some embodiments, the doping depth and doping concentration of the top doped region 330 are uniformly distributed. The top doped region 330 can reduce the surface electric field, thereby improving the breakdown voltage and on-resistance (Ron) of the laterally diffused metal oxide semiconductor field effect transistor 300. In some embodiments, the top doped region 330 is floated, and therefore, setting the top doped region 330 does not directly affect the electrostatic discharge current.

In the embodiment shown in FIGS. 4A and 4B, the top doped region 330 is provided, which can provide a uniform electric field, increase the breakdown voltage and reduce the on-resistance. At the same time, when an electrostatic discharge occurs, by passing the horizontal bipolar transistor TH, The vertical bipolar transistor TV and the diode D release an electrostatic discharge current without flowing to the gate 120 to avoid causing damage to the gate 120.

5A and 5B are cross-sectional views illustrating a laterally diffused metal oxide semiconductor field effect transistor 400 according to some embodiments of the present invention according to some embodiments. Fig. 5A is a cross-sectional view along line AA 'in Fig. 1, and Fig. 5B is a cross-sectional view along line BB' in Fig. 1. Wherein the processes or components are the same as or similar to those of the previous embodiments The same component symbols will be used, and the details will not be repeated. The difference from the previous embodiment is that, as shown in FIG. 5B, the laterally diffused metal oxide semiconductor field effect transistor 400 is provided with the top doped region 330 and the well region 228 in the foregoing embodiment at the tip of the source region 108 at the same time. As shown in FIG. 5A, in a region other than the tip of the source region 108, a top doped region 330 is also provided in the substrate 102 below the isolation region 118. In some embodiments, the doping depth and doping concentration of the top doped region 330 are uniformly distributed.

In the embodiment shown in FIGS. 5A and 5B, the top doped region 330 and the well region 228 are provided at the same time, which can provide a uniform electric field, increase the breakdown voltage, reduce the on-resistance, and further reduce the resistance value, so that the electrostatic discharge When it occurs, it is more inclined to release the electrostatic discharge current through the horizontal bipolar transistor TH, the vertical bipolar transistor TV, and the diode D without flowing to the gate 120 to avoid causing damage to the gate 120.

6A and 6B are cross-sectional views illustrating a laterally diffused metal oxide semiconductor field effect transistor 500 according to some embodiments of the present invention according to some embodiments. Fig. 6A is a cross-sectional view along line AA 'in Fig. 1, and Fig. 6B is a cross-sectional view along line BB' in Fig. 1. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the doping depth of the top doping region 530 is non-uniformly distributed regardless of the tip region of the source region 108 or the region other than the tip region. The direction of a drain region 110 decreases linearly. In some embodiments, the doping concentration of the top doping region 530 also decreases linearly from the direction of the gate 120 to the first drain region 110.

In some embodiments, the isolation regions 118A, 118B and Before 118, the substrate 102 was ion-implanted through a patterned mask to form a top doped region 530. In some embodiments, the patterned mask forms non-equal-width and non-equidistant photoresist patterns (not shown) in a predetermined region of the top doped region 530. The photoresist patterns near the gate 120 are far away from each other. The width of the non-resistance region is relatively wide, and the photoresist patterns near the first drain region 110 are closer to each other, and the width of the non-resistance region is relatively narrow. In this way, when ion implantation is performed, the dopants implanted near the gate 120 are more and deeper, and the implants closer to the first drain region 110 are less and shallower. After the annealing process, the outline of the top doped region 530 is formed as shown in FIGS. 6A and 6B. In some embodiments, the doping depth and doping concentration of the top doped region 530 decrease linearly from the direction of the gate 120 to the first drain region 110. In this way, the collapse voltage and on-resistance (Ron) of the laterally diffused metal oxide semiconductor field effect transistor 500 can be further improved.

In the embodiment shown in FIGS. 6A and 6B, since the doping depth and doping concentration of the top doped region 530 decrease linearly, the breakdown voltage and on-resistance can be further improved. At the same time, when an electrostatic discharge occurs, The horizontal bipolar transistor TH, the vertical bipolar transistor TV, and the diode D release an electrostatic discharge current without flowing to the gate 120 to avoid causing damage to the gate 120.

FIG. 7 illustrates a top view of a laterally diffused metal oxide semiconductor field effect transistor 600 according to some embodiments of the present invention, and FIGS. 8A and 8B illustrate a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments of the present invention Sectional view of crystal 600. Fig. 8A is a sectional view taken along line AA 'in Fig. 7, and Fig. 8B is a sectional view taken along line BB' in Fig. 7. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that a plurality of points are provided at the tip of the source region 108 The doped regions 114A and 114B are separated by an isolation region 118C.

Since the doped regions 114A and 114B are disposed only at the tip of the source region 108 and are not disposed at a region other than the tip of the source region 108 (as shown in FIG. 8A), in some embodiments, lateral diffusion The cross-sectional view (FIG. 8A) of the metal oxide semiconductor field effect transistor 600 along the line segment AA ′ is the same as the cross-sectional view of the lateral diffusion metal oxide semiconductor field effect transistor 100 along the line segment AA ′ in the embodiment of FIG. 2A.

In the embodiments shown in FIGS. 7, 8A, and 8B, since a plurality of doped regions 114A and 114B are provided, a second drain region 112, a drift region 106, and a doped region can be formed in the semiconductor substrate 102, respectively. Horizontal bipolar transistor TH1 composed of 114B, horizontal bipolar transistor TH2 composed of second drain region 112, drift region 106, and doped region 114A, secondary drain region 112, drift region 106, A vertical bipolar transistor TV composed of the substrate 102 and the substrate 102, a diode D1 composed of the doped region 114A and the drift region 106, and a diode D2 composed of the doped region 114B and the drift region 106.

In some embodiments, the doped regions 114A and 114B are grounded. Therefore, when an electrostatic discharge occurs, the electrostatic discharge current may be released through the horizontal bipolar transistors TH1 and TH2, the vertical bipolar transistor TV, and the diodes D1 and D2. A plurality of horizontal bipolar transistors and diodes will This makes it easier for the electrostatic discharge current to flow to the gate electrode 120 to prevent damage to the gate electrode 120.

It is worth noting that although Figures 7 and 8A and 8B show two doped regions 114A and 114B, the present invention is not limited to this. Depending on product requirements, a laterally diffused metal oxide semiconductor field effect transistor may be used. There are more than two doped regions separated by isolation regions.

In summary, an embodiment of the present invention provides a lateral diffused metal oxide semiconductor (LDMOS) field effect transistor. A doped region and a second drain region are formed at a tip of a source region. A horizontal bipolar transistor, a vertical bipolar transistor, and a diode are formed inside the element to provide a path for releasing the electrostatic discharge current, so that the electrostatic discharge current does not flow through the gate and damage the gate. Miscellaneous regions and adjusting the drift region boundary while improving the breakdown voltage and high temperature reverse bias (HTRB) test can also form a well region surrounding the drain region to further reduce the resistance value. The formation of the doped region and the second drain region does not affect the DC performance of the device, nor does it increase the area of the device.

The foregoing outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the aspects of the embodiments of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims (10)

A lateral diffused metal oxide semiconductor (LDMOS) field effect transistor includes: a substrate having a first conductivity type; and a body region located above the substrate, the body region It has a first conductivity type; a drift region is located on the upper part of the substrate; a first isolation region is provided between the body region and the drift region, and the drift region has one opposite to the first conductivity type A second conductivity type; a gate electrode located on the substrate and partially covering the body region; a source region located in the body region, the source region having the second conductivity type; a drain region located at The drift region includes a first drain region and a second drain region adjacent to each other. The first drain region has the second conductivity type, and the second drain region has the first conductivity type. A second isolation region provided in the drift region between the first isolation region and the drain region; and a first doped region between the first isolation region and the second isolation region In the substrate, the first doped region It has the first conductivity type; wherein the first doped region and the drift region constitute a first diode. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of patent application, wherein the first drain region and the source region are interdigitated fingers in the top view, and the first The doped region is adjacent to a tip of the source region, and the second drain region is located in a recess of the drain region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the application, wherein the first doped region is grounded. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, wherein the second drain region, the drift region, and the substrate constitute a vertical bipolar transistor (BJT). The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, wherein the second drain region, the drift region, and the first doped region constitute a horizontal bipolar transistor. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, further comprising: a well region located in the drift region and surrounding the drain region, the well region having the second conductivity type; The doping concentration in the well region is greater than the doping concentration in the drift region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, further comprising: a top doped region in a drift region between the second isolation regions, the top doped region having The first conductivity type. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 7 in the scope of the patent application, wherein the doping depth of the top doped region is uniformly distributed. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 7 of the application, wherein the doping depth of the top doped region decreases linearly from one of the gate to the drain region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the patent application scope further includes: a third isolation region in the substrate between the first isolation region and the second isolation region; a second The doped region is located in the substrate between the second isolation region and the third isolation region; wherein the second doped region and the drift region form a second diode.