CN104518027B - LDMOS device and its manufacturing method - Google Patents
LDMOS device and its manufacturing method Download PDFInfo
- Publication number
- CN104518027B CN104518027B CN201410262236.2A CN201410262236A CN104518027B CN 104518027 B CN104518027 B CN 104518027B CN 201410262236 A CN201410262236 A CN 201410262236A CN 104518027 B CN104518027 B CN 104518027B
- Authority
- CN
- China
- Prior art keywords
- drift region
- region
- polysilicon
- drift
- ldmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 172
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims description 165
- 239000012535 impurity Substances 0.000 claims description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 26
- 229910052760 oxygen Inorganic materials 0.000 claims description 26
- 239000001301 oxygen Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 25
- 238000000926 separation method Methods 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000004088 simulation Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of LDMOS device, drift region is made of the first drift region and the second drift region, and the first drift region is made of the ion implanted region being formed in the selection area of silicon substrate；Second drift region is made of the DOPOS doped polycrystalline silicon being formed in surface of silicon, and the second drift region is superimposed upon on the first drift region, and drain region is formed in the second drift region.The setting of second drift region of the invention enables to the thickness of entire drift region to increase, smaller so as to the dead resistance that reduces entire drift region, and can effectively increase the linear current of device, reduce the conducting resistance of device；Device of the present invention is also able to maintain higher breakdown voltage and process costs are low.The invention also discloses a kind of manufacturing methods of LDMOS device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of lateral fet (LDMOS
Device；The invention further relates to a kind of manufacturing methods of LDMOS device.
Background technique
Lateral fet (LDMOS) is the semiconductor high-voltage device generally used, is widely used in power supply pipe
The fields such as reason, LCD and LED driving, ESD protection.Application mode usually has simulation application and two kinds of switch application.When LDMOS is used
When switching, device is needed to have very low conducting resistance (the device source ohmic leakage of linear zone), to reduce switching power loss.LDMOS
In, channel length is much smaller than drift region length, and the conducting resistance of device is dominated by drift zone resistance, therefore switch LDMOS is needed
Increase drift doping concentration as far as possible, reduce drift region length, increase drift region thickness, to reach the mesh for reducing conducting resistance
's.But LDMOS has to the requirement for meeting breakdown voltage, and the raising of drift doping concentration and the diminution of length are all by certain
Limitation.The increase of drift region thickness, which can only be injected by big energetic ion in non-epitaxial technique and push away trap for a long time, to be formed,
But excessive horizontal proliferation is brought in this way, causes excessive short-channel effect.The LDMOS of epitaxy can form thick drift region, but
Process costs improve.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of LDMOS device, can effectively increase device linear current,
The conducting resistance for reducing device, is able to maintain higher breakdown voltage, process costs are low.For this purpose, the present invention also provides a kind of LDMOS
The manufacturing method of device.
In order to solve the above technical problems, LDMOS device provided by the invention includes:
The silicon substrate of first conduction type doping.
First drift region, the second conductive type ion in the selection area by being formed in the silicon substrate inject district's groups
At.
Channel region, the first conductive type of trap district's groups in the selection area by being formed in the silicon substrate are at described first
First side of drift region and the channel region are horizontally in contact.
Polysilicon gate is formed in above the channel region, and isolation has gate medium between the polysilicon gate and the silicon substrate
Layer, channel region described in the polysilicon gate covering part simultaneously extends to above first drift region, is covered by the polysilicon gate
The channel region surface of lid is used to form channel.
Source region is made of the second conduction type heavily doped region being formed in the channel region, the source region and described more
First side autoregistration of crystal silicon grid.
Second drift region is made of, institute the polysilicon for the second conduction type doping being formed in the surface of silicon
It states the second drift region and is located at the top of first drift region and bottom and first drift region phase of second drift region
It contacts and is superimposed the drift region to form LDMOS device；First side of second drift region is close to the second of the polysilicon gate
Second side of the first side and the polysilicon gate of side and second drift region at a distance, second drift region
Second direction for being laterally away from second side of the polysilicon gate extends.
Drain region is made of the second conduction type heavily doped region being formed in the selection area of second drift region, described
The second side and second side of the drain region and the polysilicon gate of drain region close to second drift region are separated by a lateral distance.
Thickness by adjusting second drift region adjusts the conducting resistance of the LDMOS device, second drift
The conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of the thickness in area is smaller.
A further improvement is that the polysilicon of second drift region and the polysilicon of the polysilicon gate use identical work
Skill is formed simultaneously.
A further improvement is that being spaced between the first side bottom of second drift region and first drift region
State gate dielectric layer, second side of second drift region extend to the field oxygen on the outside of second side of first drift region every
On absciss layer, the gate dielectric layer of second drift region bottom and the field oxygen separation layer be used as the terminal of etching polysilicon from
And facilitate the etching of the polysilicon of second drift region.
A further improvement is that the first side of second drift region and second side of the polysilicon gate pass through silicon nitride
Side wall isolation.
A further improvement is that the impurity of second drift region is in place in the polycrystalline silicon deposit of second drift region
Doping is formed or is formed after deposition by ion implantation doping.
A further improvement is that the LDMOS device be N-type device, first conduction type be p-type, described second
Conduction type is N-type；Alternatively, the LDMOS device is P-type device, first conduction type is N-type, and described second is conductive
Type is p-type.
A further improvement is that the LDMOS device is symmetrical device；Or the LDMOS device is symmetrical device.
In order to solve the above technical problems, the manufacturing method of LDMOS device provided by the invention includes the following steps:
Step 1: providing the silicon substrate of one first conduction type doping；Fabricating yard oxygen separation layer on the silicon substrate.
Step 2: the ion implanting of carry out the first conduction type well region in the selection area of the silicon substrate forms ditch
Road area, the selection area for forming the channel region are defined by photoetching process.
Step 3: the first drift is formed in the selection area of the silicon substrate using the second conductive type ion injection technology
Area is moved, the selection area for forming first drift region is defined by photoetching process；First side of first drift region and described
Channel region is horizontally in contact.
Step 4: carrying out furnace anneal processing to the channel region and first drift region.
Step 5: growing gate dielectric layer in the surface of silicon.
Step 6: being removed using lithographic etch process to the gate dielectric layer part, the part the being removed gate medium
Layer is is in contact the gate dielectric layer in region positioned at first drift region and subsequent second drift region.
Step 7: the substrate face depositing polysilicon after gate dielectric layer etching；In the polycrystalline silicon deposit
It is doped or undoped that the second conductive type impurity in place is carried out in the process.
Step 8: carrying out the second conductive type impurity doping to the polysilicon using comprehensive ion implantation technology.
Step 9: being handled using impurity of the rapid thermal anneal process to the polysilicon.
Polysilicon gate and the second drift are formed simultaneously Step 10: performing etching using lithographic etch process to the polysilicon
Area.
The polysilicon gate is located at channel region described in the channel region top and the polysilicon gate covering part and extends
To above first drift region, the channel region surface covered by the polysilicon gate is used to form channel.
Second drift region is located at the top of first drift region and the bottom of second drift region and described
One drift region is in contact and is superimposed the drift region to form LDMOS device；First side of second drift region is close to the polycrystalline
Second side of the first side and the polysilicon gate of second side of Si-gate and second drift region at a distance, described
The second of the two drift regions direction for being laterally away from second side of the polysilicon gate extends；First side bottom of second drift region
There is the gate dielectric layer at interval between portion and first drift region, and second side of second drift region is extended to positioned at described
On the field oxygen separation layer on the outside of second side of first drift region, the gate dielectric layer of second drift region bottom and institute
It states an oxygen separation layer and is used as the terminal of etching polysilicon to facilitate the etching of the polysilicon of second drift region.
Thickness by adjusting second drift region adjusts the conducting resistance of the LDMOS device, second drift
The conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of the thickness in area is smaller.
Step 11: carrying out thermal oxide to the polysilicon surface of the polysilicon gate and second drift region forms a heat
Oxide layer.
Step 12: deposition silicon nitride film, to the silicon nitride film be dry-etched in the polysilicon gate and
The side of second drift region forms silicon nitride spacer.
It injects to form source region and drain region Step 13: carrying out the second conduction type heavy doping ion, the source region is formed in
In the channel region and the first side autoregistration of the source region and the polysilicon gate；The drain region is formed in second drift
Move in area's selection area, the drain region close to second drift region second side and the drain region and the polysilicon gate the
Two sides are separated by a lateral distance.
A further improvement is that the LDMOS device be N-type device, first conduction type be p-type, described second
Conduction type is N-type, and the impurity of the ion implanting of channel region described in step 2 is boron or indium, polysilicon described in step 7
The impurity adulterated in place is phosphorus, and the ion implanted impurity of polysilicon described in step 8 is phosphorus；Alternatively, the LDMOS device is P
Type device, first conduction type are N-type, and second conduction type is p-type, and the ion of channel region described in step 2 is infused
The impurity entered is phosphorus or arsenic, and the impurity of polysilicon described in step 7 adulterated in place is boron, polysilicon described in step 8
Ion implanted impurity is boron, and the silicon substrate of the n-type doping in step 1 is made of the deep N-well being formed in P-type silicon substrate.
A further improvement is that the temperature of the furnace anneal in step 4 is 900 DEG C~1200 DEG C, time 0.5
Hour~5 hours；The temperature of the rapid thermal annealing in step 9 is 1000 DEG C, the time is greater than 10 seconds；In step 11
Formed the thermal oxide layer with a thickness of 20 angstroms~100 angstroms.
Drift region of the invention is by being formed in substrate intermediate ion the first drift region for forming of injection diffusion region and by polysilicon
Second drift region of doping composition is formed by stacking and drift region in the prior art is only by being formed in the injection diffusion of substrate intermediate ion
For district's groups at comparing, the setting of the second drift region of the invention enables to the thickness of entire drift region to increase, whole so as to reduce
The dead resistance of a drift region is smaller, and can effectively increase the linear current of device, reduce the conducting resistance of device；Meanwhile this
Invention needs not move through the doping concentration of the first drift region of increase and the second drift region to reduce the dead resistance of drift region, institute
Higher breakdown voltage is also able to maintain with device of the present invention；Second drift region of the invention is made of polysilicon, can and polycrystalline
The used polysilicon of Si-gate synchronizes to be formed, so process costs of the invention are low.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of one LDMOS device of the embodiment of the present invention；
Fig. 2 is the structural schematic diagram of two LDMOS device of the embodiment of the present invention；
Fig. 3 A is the semiconductor process simulation and device simulation tool (Technology of existing LDMOS device
Computer AidedDesign, TCAD) device simulation figure；
Fig. 3 B is the TCAD device simulation figure of one LDMOS device of the embodiment of the present invention；
Fig. 3 C is the linear source-drain current of the TCAD simulation of the embodiment of the present invention one and existing LDMOS device and the pass of grid voltage
It is that curve compares figure；
Fig. 4 A- Fig. 4 I is the structural schematic diagram of LDMOS device in each step of one method of the embodiment of the present invention.
Specific embodiment
LDMOS device of the embodiment of the present invention includes:
The silicon substrate of first conduction type doping.
First drift region, the second conductive type ion in the selection area by being formed in the silicon substrate inject district's groups
At.
Channel region, the first conductive type of trap district's groups in the selection area by being formed in the silicon substrate are at described first
First side of drift region and the channel region are horizontally in contact.
Polysilicon gate is formed in above the channel region, and isolation has gate medium between the polysilicon gate and the silicon substrate
Layer, channel region described in the polysilicon gate covering part simultaneously extends to above first drift region, is covered by the polysilicon gate
The channel region surface of lid is used to form channel.
Source region is made of the second conduction type heavily doped region being formed in the channel region, the source region and described more
First side autoregistration of crystal silicon grid.
Second drift region is made of, institute the polysilicon for the second conduction type doping being formed in the surface of silicon
It states the second drift region and is located at the top of first drift region and bottom and first drift region phase of second drift region
It contacts and is superimposed the drift region to form LDMOS device；First side of second drift region is close to the second of the polysilicon gate
Second side of the first side and the polysilicon gate of side and second drift region at a distance, second drift region
Second direction for being laterally away from second side of the polysilicon gate extends.
Drain region is made of the second conduction type heavily doped region being formed in the selection area of second drift region, described
The second side and second side of the drain region and the polysilicon gate of drain region close to second drift region are separated by a lateral distance.
Thickness by adjusting second drift region adjusts the conducting resistance of the LDMOS device, second drift
The conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of the thickness in area is smaller.
The polysilicon of second drift region and the polysilicon of the polysilicon gate are formed simultaneously using same process.
There is the gate dielectric layer at interval between first side bottom of second drift region and first drift region, described
Second side of second drift region extends on the field oxygen separation layer on the outside of second side of first drift region, and described second
The gate dielectric layer of drift region bottom and the field oxygen separation layer are used as the terminal of etching polysilicon to facilitate described second
The etching of the polysilicon of drift region.
First side of second drift region and second side of the polysilicon gate are isolated by silicon nitride spacer.
The impurity of second drift region in the polycrystalline silicon deposit of second drift region in place doping formed or
It is formed after deposit by ion implantation doping.
LDMOS device of the embodiment of the present invention can be symmetrical device or symmetrical device.
LDMOS device of the embodiment of the present invention can be N-type LDMOS and p-type LDMOS device.As shown in Figure 1, being of the invention real
Apply the structural schematic diagram of one LDMOS device of example；One LDMOS device of the embodiment of the present invention is N-type LDMOS device, the first conductive-type
Type is p-type, and the second conduction type is N-type；One LDMOS device of the embodiment of the present invention includes:
The silicon substrate 101 of p-type doping.An oxygen separation layer 102 is formed on the silicon substrate 101.
First drift region 103, the N-type ion implanted region in selection area by being formed in the silicon substrate 101 form.
Channel region 104, the P type trap zone in selection area by being formed in the silicon substrate 101 form, first drift
First side in area 103 and the channel region 104 are horizontally in contact.
Polysilicon gate 106 is formed in 104 top of channel region, between the polysilicon gate 106 and the silicon substrate 101
Isolation has gate dielectric layer 105, and preferably, the gate dielectric layer 5 is gate oxide；Described in 106 covering part of polysilicon gate
Channel region 104 simultaneously extends to 103 top of the first drift region, 104 table of the channel region covered by the polysilicon gate 106
Face is used to form channel.
Source region 108 is made of the N-type heavily doped region being formed in the channel region 104, the source region 108 and described more
First side autoregistration of crystal silicon grid 106.
Second drift region 107 is made of the polysilicon for the n-type doping being formed on 101 surface of silicon substrate, and described
Two drift regions 107 are located at the top of first drift region 103 and the bottom of second drift region 107 and described first is floated
Area 103 is moved to be in contact and be superimposed the drift region to form LDMOS device；First side of second drift region 107 is close to described more
Second side of the first side and the polysilicon gate 106 of second side of crystal silicon grid 106 and second drift region 107 is separated by one section
Distance, the direction that the second of second drift region 107 is laterally away from second side of the polysilicon gate 106 extend.
The polysilicon of second drift region 107 and the polysilicon of the polysilicon gate 106 are using same process while shape
At.The N-type that is doped to of second drift region 107 is lightly doped, and the polysilicon gate 106 is doped to N-type heavy doping, full respectively
Needs of the foot as grid and drift region.Heat is all formed on the surface of second drift region 107 and the polysilicon gate 106
Oxide layer 110 is all formed with silicon nitride spacer 111 in the side of second drift region 107 and the polysilicon gate 106.Institute
Second side of the first side and the polysilicon gate 106 of stating the second drift region 107 is isolated by silicon nitride spacer 111.Described
In the polycrystalline silicon deposit of second drift region 107, doping forms or leads to after deposition the impurity of two drift regions 107 in place
Ion implantation doping is crossed to be formed.
Drain region 109 is made of, the drain region the N-type heavily doped region being formed in 107 selection area of the second drift region
109 second side and second side of the drain region 109 and the polysilicon gate 106 close to second drift region 107 is separated by one
Lateral distance.
In the embodiment of the present invention one, the thickness by adjusting second drift region 107 adjusts leading for the LDMOS device
Be powered resistance, and the dead resistance of the drift region of bigger, the described LDMOS device of the thickness of second drift region 107 is smaller, described
The conducting resistance of LDMOS device is smaller.
Preferably, described in there is interval between the first side bottom of second drift region 107 and first drift region 103
Gate dielectric layer 105, second side of second drift region 107 extend on the outside of second side of first drift region 103
Field oxygen separation layer 102 on, the gate dielectric layer 105 of 107 bottom of the second drift region and the field oxygen separation layer 102 are used
Make the terminal of etching polysilicon to facilitate the etching of the polysilicon of second drift region 107.
As shown in Fig. 2, being the structural schematic diagram of two LDMOS device of the embodiment of the present invention；Two LDMOS device of the embodiment of the present invention
Part is p-type LDMOS device, and first conduction type is N-type, and second conduction type is p-type.By implementing to the present invention
Two LDMOS device structure of the embodiment of the present invention can be obtained in the exchange that the conduction type of the doping of example one carries out p-type and N-type；Tool
Body is that two LDMOS device of the embodiment of the present invention includes:
The silicon substrate 200 of n-type doping, silicon substrate 200 described in the embodiment of the present invention two or selects p-type doped structure, leads to
Cross 200 structure of silicon substrate that the realization n-type doping of deep N-well 201 of n-type doping is formed in P-type silicon substrate 200.It is served as a contrast in the silicon
An oxygen separation layer 202 is formed on bottom 101.
First drift region 203 is infused by the P-type ion in the selection area for the deep N-well 201 for being formed in the silicon substrate 200
Enter district's groups at.
Channel region 204 is made of, institute the N-type well region in the selection area for the deep N-well 201 for being formed in the silicon substrate 200
The first side and the channel region 204 for stating the first drift region 203 are horizontally in contact.
Polysilicon gate 206, is formed in 204 top of the channel region, the polysilicon gate 206 and the silicon substrate 200
Isolation has gate dielectric layer 205 between deep N-well 201, and preferably, the gate dielectric layer 205 is gate oxide；The polysilicon gate 206
Channel region 204 described in covering part simultaneously extends to 203 top of the first drift region, the institute covered by the polysilicon gate 206
It states 204 surface of channel region and is used to form channel.
Source region 208 is made of the p-type heavily doped region being formed in the channel region 204, the source region 208 and described more
First side autoregistration of crystal silicon grid 206.
Second drift region 207, by the polysilicon for the p-type doping being formed on 201 surface of deep N-well of the silicon substrate 200
Composition；The polysilicon of second drift region 207 and the polysilicon of the polysilicon gate 206 are formed simultaneously using same process.
The p-type that is doped to of second drift region 207 is lightly doped, and the polysilicon gate 206 is doped to p-type heavy doping, meets respectively
Needs as grid and drift region.
Second drift region 207 is located at the top of first drift region 203 and the bottom of second drift region 207
Portion and first drift region 203 are in contact and are superimposed the drift region to form LDMOS device；The of second drift region 207
Side is close to second side of the polysilicon gate 206 and the first side of second drift region 207 and the polysilicon gate 206
At a distance, the second of second drift region 207 is laterally away from the side of second side of the polysilicon gate 206 to second side
To extension.
It is all formed with thermal oxide layer 210 on the surface of second drift region 207 and the polysilicon gate 206, described
Second drift region 207 and the side of the polysilicon gate 206 are all formed with silicon nitride spacer 211.Second drift region 207
Second side of first side and the polysilicon gate 206 is isolated by silicon nitride spacer 211.The impurity of second drift region 207
In the polycrystalline silicon deposit of second drift region 207, doping forms or passes through after deposition ion implantation doping shape in place
At.
There is the gate medium at interval between first side bottom of second drift region 207 and first drift region 203
Layer 205, second side of second drift region 207 extends to the field oxygen on the outside of second side of first drift region 203
On separation layer 202, the gate dielectric layer 205 of 207 bottom of the second drift region and the field oxygen separation layer 202 are used as polycrystalline
The terminal of silicon etching is to facilitate the etching of the polysilicon of second drift region 207.
Drain region 209 is made of, the drain region the p-type heavily doped region being formed in 207 selection area of the second drift region
209 second side and second side of the drain region 209 and the polysilicon gate 206 close to second drift region 207 is separated by one
Lateral distance.
Thickness by adjusting second drift region 207 adjusts the conducting resistance of the LDMOS device, second drift
Move the conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of thickness in area 207
It is smaller.
It as shown in figs.3 a and 3b, is the TCAD device of one LDMOS device of existing LDMOS device and the embodiment of the present invention respectively
Simulation drawing；Fig. 3 C is the linear source-drain current of the TCAD simulation of the embodiment of the present invention one and existing LDMOS device and the pass of grid voltage
It is that curve compares figure；It is found that one LDMOS device of the embodiment of the present invention increases one by polysilicon group than existing LDMOS device
At the second drift region after, the thickness of drift region will increase, can reduce the dead resistance of entire drift region, the curve in Fig. 3 C
301 correspond to the relation curve of the linear source-drain current of existing LDMOS device and grid voltage, curve 302 corresponds to the present invention and implements
The linear source-drain current of one LDMOS device of example and the relation curve of grid voltage, it is known that one LDMOS device of the embodiment of the present invention it is linear
Electric current is increased, and the conducting resistance of device is reduced；This sufficiently demonstrates the embodiment of the present invention one and increases the second drift
Really the linear current of device can be effectively increased behind area, reduces the conducting resistance of device, be able to maintain higher breakdown voltage.
It is the structural schematic diagram of LDMOS device in each step of one method of the embodiment of the present invention as shown in Fig. 4 A to Fig. 4 I.This
The manufacturing method of one LDMOS device of inventive embodiments includes the following steps:
Step 1: as shown in Figure 4 A, providing the silicon substrate 101 of p-type doping；The fabricating yard oxygen on the silicon substrate 101
Separation layer 102.Field oxygen separation layer 102 is local field oxygen separation layer (LOCOS) or shallow groove isolation layer (STI).
Step 2: as shown in Figure 4 B, the ion implanting of the carry out P type trap zone in the selection area of the silicon substrate 101
Channel region 104 is formed, the selection area for forming the channel region 104 is defined by photoetching process.The ion of the channel region 104 is infused
The impurity entered is boron or indium, can be formed using multiple ion implanting.
Step 3: as shown in Figure 4 C, being formed in the selection area of the silicon substrate 101 using N-type ion injection technology
First drift region 103, the selection area for forming first drift region 103 are defined by photoetching process；First drift region 103
The first side and the channel region 104 be horizontally in contact.The impurity of the ion implanting of first drift region 103 is usually
Phosphorus can be formed using the multiple ion implanting of different-energy.
Step 4: as shown in Figure 4 C, carrying out furnace anneal processing to the channel region 104 and first drift region 103.
Preferably, the temperature of the furnace anneal is 900 DEG C~1200 DEG C, the time is 0.5 hour~5 hours.
Step 5: as shown in Figure 4 D, growing gate dielectric layer 105 on 101 surface of silicon substrate, preferably, the grid are situated between
Matter layer 105 is gate oxide.
Step 6: as shown in Figure 4 E, being removed, being removed to 105 part of gate dielectric layer using lithographic etch process
The part gate dielectric layer 105 is is in contact the institute in region positioned at first drift region 103 and subsequent second drift region 107
State gate dielectric layer 105.
Step 7: as illustrated in figure 4f, the substrate face depositing polysilicon after the gate dielectric layer 105 etching
106a；It is doped or undoped that N-type impurity in place is carried out in the polysilicon 106a deposition process, n-type doping preferably in place
Impurity be phosphorus.
Step 8: as illustrated in figure 4f, carrying out N-type impurity to the polysilicon 106a using comprehensive ion implantation technology and mixing
It is miscellaneous.Preferably, the ion implanted impurity of the polysilicon is phosphorus.
Step 9: as illustrated in figure 4f, using rapid thermal anneal process to the impurity of the polysilicon 106a at
Reason.Preferably, the temperature of the rapid thermal annealing is 1000 DEG C, the time is greater than 10 seconds.
Step 10: as shown in Figure 4 G, being performed etching using lithographic etch process to the polysilicon and being formed simultaneously polysilicon
Grid 106 and the second drift region 107.
The polysilicon gate 106 is located at ditch described in 104 top of channel region and 106 covering part of the polysilicon gate
Road area 104 simultaneously extends to 103 top of the first drift region, 104 surface of the channel region covered by the polysilicon gate 106
It is used to form channel.
Second drift region 107 is located at the top of first drift region 103 and the bottom of second drift region 107
Portion and first drift region 103 are in contact and are superimposed the drift region to form LDMOS device；The of second drift region 107
Side is close to second side of the polysilicon gate 106 and the first side of second drift region 107 and the polysilicon gate 106
At a distance, the second of second drift region 107 is laterally away from the side of second side of the polysilicon gate 106 to second side
To extension；There is the gate dielectric layer at interval between first side bottom of second drift region 107 and first drift region 103
105, second side of second drift region 107 extends to the field on the outside of second side of first drift region 103
On oxygen separation layer 102, the gate dielectric layer 105 of 107 bottom of the second drift region and the field oxygen separation layer 102 are used as more
The terminal of crystal silicon etching is to facilitate the etching of the polysilicon of second drift region 107.
Thickness by adjusting second drift region 107 adjusts the conducting resistance of the LDMOS device, second drift
Move the conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of thickness in area 107
It is smaller.
Step 11: as shown at figure 4h, to the polysilicon surface of the polysilicon gate 106 and second drift region 107
It carries out thermal oxide and forms a thermal oxide layer 110.Preferably, the thermal oxide layer 110 with a thickness of 20 angstroms~100 angstroms.
Step 12: as shown in fig. 41, deposition silicon nitride film, the silicon nitride film is dry-etched in described in
The side of polysilicon gate 106 and second drift region 107 forms silicon nitride spacer 111.
Step 13: injecting to form source region 108 and drain region 109 as shown in Figure 1, carrying out N-type heavy doping ion, the source region
108 are formed in the channel region 104 and the first side autoregistration of the source region 108 and the polysilicon gate 106；The leakage
Area 109 is formed in 107 selection area of the second drift region, the drain region 109 close to second drift region 107 second
Side and second side of the drain region 109 and the polysilicon gate 106 are separated by a lateral distance.
Following steps please refer to shown in Fig. 2, and the manufacturing method of two LDMOS device of the embodiment of the present invention includes the following steps:
Step 1: providing the silicon substrate of a n-type doping；Fabricating yard oxygen separation layer on the silicon substrate.The present invention is implemented
The silicon substrate of n-type doping adds the deep N-well 201 being formed in P-type silicon substrate 200 using the silicon substrate 200 of p-type doping and replaces in example
It changes.
Step 2: the ion implanting shape of the carry out N-type well region in the selection area of the deep N-well 201 of the silicon substrate 200
At channel region 204, the selection area for forming the channel region 204 is defined by photoetching process.
Step 3: is formed in the selection area of the deep N-well 201 of the silicon substrate 200 using P-type ion injection technology
One drift region 203, the selection area for forming first drift region 203 are defined by photoetching process；First drift region 203
First side and the channel region 204 are horizontally in contact.
Step 4: carrying out furnace anneal processing to the channel region 204 and first drift region 203.Preferably, described
The temperature of furnace anneal is 900 DEG C~1200 DEG C, the time is 0.5 hour~5 hours.
Step 5: growing gate dielectric layer 205 on 201 surface of deep N-well of the silicon substrate 200.Preferably, the gate medium
Layer 205 is gate oxide.
Step 6: being removed using lithographic etch process to 205 part of gate dielectric layer, the part the being removed grid are situated between
Matter layer 205 is the gate dielectric layer in region of being in contact positioned at first drift region 203 and subsequent second drift region 207
205。
Step 7: the substrate face depositing polysilicon after the gate dielectric layer 205 etching；It forms sediment in the polysilicon
It is doped or undoped that p type impurity in place is carried out during product；The impurity of p-type doping preferably in place is boron.
Step 8: carrying out p type impurity doping to the polysilicon using comprehensive ion implantation technology.Preferably, described more
The ion implanted impurity of crystal silicon is boron.
Step 9: being handled using impurity of the rapid thermal anneal process to the polysilicon.Preferably, described fast
The temperature of speed heat annealing is 1000 DEG C, the time is greater than 10 seconds.
Polysilicon gate 206 and second are formed simultaneously Step 10: performing etching using lithographic etch process to the polysilicon
Drift region 207.
The polysilicon gate 206 is located at ditch described in 204 top of channel region and 206 covering part of the polysilicon gate
Road area 204 simultaneously extends to 203 top of the first drift region, 204 surface of the channel region covered by the polysilicon gate 206
It is used to form channel.
Second drift region 207 is located at the top of first drift region 203 and the bottom of second drift region 207
Portion and first drift region 203 are in contact and are superimposed the drift region to form LDMOS device；The of second drift region 207
Side is close to second side of the polysilicon gate 206 and the first side of second drift region 207 and the polysilicon gate 206
At a distance, the second of second drift region 207 is laterally away from the side of second side of the polysilicon gate 206 to second side
To extension；There is the gate dielectric layer at interval between first side bottom of second drift region 207 and first drift region 203
205, second side of second drift region 207 extends to the field on the outside of second side of first drift region 203
On oxygen separation layer, the gate dielectric layer 205 and the field oxygen separation layer of 207 bottom of the second drift region are used as polysilicon quarter
The terminal of erosion is to facilitate the etching of the polysilicon of second drift region 207.
Thickness by adjusting second drift region 207 adjusts the conducting resistance of the LDMOS device, second drift
Move the conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of thickness in area 207
It is smaller.
Step 11: the polysilicon surface to the polysilicon gate 206 and second drift region 207 carries out thermal oxide shape
At a thermal oxide layer 210.Preferably, the thermal oxide layer 210 with a thickness of 20 angstroms~100 angstroms.
Step 12: deposition silicon nitride film, carries out the silicon nitride film to be dry-etched in the polysilicon gate 206
Silicon nitride spacer 211 is formed with the side of second drift region 207.
It injects to form source region 208 and drain region 209 Step 13: carrying out p-type heavy doping ion, the source region 208 is formed in
In the channel region 204 and the first side autoregistration of the source region 208 and the polysilicon gate 206；The drain region 209 is formed
In 207 selection area of the second drift region, the drain region 209 is close to second side of second drift region 207 and described
Second side of drain region 209 and the polysilicon gate 206 is separated by a lateral distance.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of LDMOS device characterized by comprising
The silicon substrate of first conduction type doping；
First drift region, the second conductive type ion injection region in the selection area by being formed in the silicon substrate form；
Channel region, the first conductive type of trap district's groups in the selection area by being formed in the silicon substrate are at first drift
First side in area and the channel region are horizontally in contact；
Polysilicon gate is formed in above the channel region, and isolation has gate dielectric layer between the polysilicon gate and the silicon substrate, institute
It states channel region described in polysilicon gate covering part and extends to above first drift region, the institute covered by the polysilicon gate
It states channel region surface and is used to form channel；
Source region is made of, the source region and the polysilicon the second conduction type heavily doped region being formed in the channel region
First side autoregistration of grid；
Second drift region is made of, described the polysilicon for the second conduction type doping being formed in the surface of silicon
Two drift regions are located at the top of first drift region and the bottom of second drift region and first drift region are in contact
And it is superimposed the drift region for forming LDMOS device；First side of second drift region close to the polysilicon gate second side and
Second side of first side of second drift region and the polysilicon gate at a distance, the second of second drift region
The direction for being laterally away from second side of the polysilicon gate extends；
Drain region is made of, the drain region the second conduction type heavily doped region being formed in the selection area of second drift region
Second side and second side of the drain region and the polysilicon gate close to second drift region are separated by a lateral distance；
Thickness by adjusting second drift region adjusts the conducting resistance of the LDMOS device, second drift region
The conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of thickness is smaller.
2. LDMOS device as described in claim 1, it is characterised in that: the polysilicon and the polysilicon of second drift region
The polysilicon of grid is formed simultaneously using same process.
3. LDMOS device as claimed in claim 1 or 2, it is characterised in that: the first side bottom of second drift region and described
There is the gate dielectric layer at interval between first drift region, and second side of second drift region is extended to positioned at first drift
On field oxygen separation layer on the outside of the second side in area, the gate dielectric layer of second drift region bottom and the field oxygen separation layer
Terminal as etching polysilicon is to facilitate the etching of the polysilicon of second drift region.
4. LDMOS device as claimed in claim 1 or 2, it is characterised in that: the first side of second drift region and the polycrystalline
Second side of Si-gate is isolated by silicon nitride spacer.
5. LDMOS device as claimed in claim 1 or 2, it is characterised in that: the impurity of second drift region is in second drift
Doping is formed or is formed after deposition by ion implantation doping in place when moving the polycrystalline silicon deposit in area.
6. LDMOS device as claimed in claim 1 or 2, it is characterised in that: the LDMOS device be N-type device, described first
Conduction type is p-type, and second conduction type is N-type；Alternatively, the LDMOS device is P-type device, described first is conductive
Type is N-type, and second conduction type is p-type.
7. LDMOS device as claimed in claim 1 or 2, it is characterised in that: the LDMOS device is symmetrical device；Or institute
Stating LDMOS device is symmetrical device.
8. a kind of manufacturing method of LDMOS device, which comprises the steps of:
Step 1: providing the silicon substrate of one first conduction type doping；Fabricating yard oxygen separation layer on the silicon substrate；
Step 2: the ion implanting of carry out the first conduction type well region in the selection area of the silicon substrate forms channel
Area, the selection area for forming the channel region are defined by photoetching process；
Step 3: the first drift is formed in the selection area of the silicon substrate using the second conductive type ion injection technology
Area, the selection area for forming first drift region are defined by photoetching process；First side of first drift region and the ditch
Road area is horizontally in contact；
Step 4: carrying out furnace anneal processing to the channel region and first drift region；
Step 5: growing gate dielectric layer in the surface of silicon；
Step 6: being removed using lithographic etch process to the gate dielectric layer part, the part the being removed gate dielectric layer is
It is in contact the gate dielectric layer in region positioned at first drift region and subsequent second drift region；
Step 7: the substrate face depositing polysilicon after gate dielectric layer etching；In the polysilicon deposition process
Middle progress the second conductive type impurity in place is doped or undoped；
Step 8: carrying out the second conductive type impurity doping to the polysilicon using comprehensive ion implantation technology；
Step 9: being handled using impurity of the rapid thermal anneal process to the polysilicon；
Polysilicon gate and the second drift region are formed simultaneously Step 10: performing etching using lithographic etch process to the polysilicon；
The polysilicon gate is located at channel region described in the channel region top and the polysilicon gate covering part and extends to institute
It states above the first drift region, the channel region surface covered by the polysilicon gate is used to form channel；
Second drift region is located at the top of first drift region and the bottom of second drift region and described first is floated
Area is moved to be in contact and be superimposed the drift region to form LDMOS device；First side of second drift region is close to the polysilicon gate
Second side and second drift region the first side and the polysilicon gate second side at a distance, it is described second drift
The direction for moving second side that the second of area is laterally away from the polysilicon gate extends；First side bottom of second drift region and
There is the gate dielectric layer at interval between first drift region, and second side of second drift region is extended to positioned at described first
On the field oxygen separation layer on the outside of second side of drift region, the gate dielectric layer of second drift region bottom and the field
Oxygen separation layer is used as the terminal of etching polysilicon to facilitate the etching of the polysilicon of second drift region；
Thickness by adjusting second drift region adjusts the conducting resistance of the LDMOS device, second drift region
The conducting resistance of smaller, the described LDMOS device of dead resistance of the drift region of bigger, the described LDMOS device of thickness is smaller；
Step 11: carrying out thermal oxide to the polysilicon surface of the polysilicon gate and second drift region forms a thermal oxide
Layer；
Step 12: deposition silicon nitride film, be dry-etched in the polysilicon gate and described to the silicon nitride film
The side of second drift region forms silicon nitride spacer；
It injects to form source region and drain region Step 13: carrying out the second conduction type heavy doping ion, the source region is formed in described
In channel region and the first side autoregistration of the source region and the polysilicon gate；The drain region is formed in second drift region
In selection area, the drain region is close to second side of second drift region and the second side in the drain region and the polysilicon gate
It is separated by a lateral distance.
9. method as claimed in claim 8, it is characterised in that: the LDMOS device is N-type device, first conduction type
For p-type, second conduction type is N-type, and the impurity of the ion implanting of channel region described in step 2 is boron or indium, step 7
Described in the impurity adulterated in place of polysilicon be phosphorus, the ion implanted impurity of polysilicon described in step 8 is phosphorus；Alternatively, institute
Stating LDMOS device is P-type device, and first conduction type is N-type, and second conduction type is p-type, described in step 2
The impurity of the ion implanting of channel region is phosphorus or arsenic, and the impurity of polysilicon described in step 7 adulterated in place is boron, step 8
Described in the ion implanted impurity of polysilicon be boron, the silicon substrate of the n-type doping in step 1 is by being formed in P-type silicon substrate
Deep N-well composition.
10. such as claim 8 or 9 the methods, it is characterised in that: the temperature of the furnace anneal in step 4 is 900 DEG C
~1200 DEG C, the time be 0.5 hour~5 hours；The temperature of the rapid thermal annealing in step 9 is 1000 DEG C, the time is big
In 10 seconds；The thermal oxide layer formed in step 11 with a thickness of 20 angstroms~100 angstroms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410262236.2A CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410262236.2A CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104518027A CN104518027A (en) | 2015-04-15 |
| CN104518027B true CN104518027B (en) | 2019-06-11 |
Family
ID=52793044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410262236.2A Active CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104518027B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298744B (en) * | 2015-05-11 | 2018-12-11 | 北大方正集团有限公司 | The preparation method and power device of power device |
| MX2019009532A (en) * | 2017-02-14 | 2019-09-16 | Nissan Motor | Semiconductor device and semiconductor device production method. |
| TWI646653B (en) * | 2017-12-28 | 2019-01-01 | 新唐科技股份有限公司 | Laterally diffused metal oxide semiconductor field effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
| CN103035671B (en) * | 2012-08-20 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacture method thereof |
-
2014
- 2014-06-13 CN CN201410262236.2A patent/CN104518027B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104518027A (en) | 2015-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105226058B (en) | JFET and ldmos transistor are prepared in monolithic power integrated circuit using deep diffusion region | |
| EP1396030B1 (en) | Vertical power semiconductor device and method of making the same | |
| EP2362422A2 (en) | Vertical power semiconductor device and method of making the same | |
| CN101026191A (en) | Semiconductor device and method of manufacturing the same | |
| US20100200915A1 (en) | Lateral trench mosfet having a field plate | |
| CN104517852A (en) | Lateral drain metal oxide semiconductor device and method of fabricating same | |
| CN103137697A (en) | Power MOSFET and methods for forming the same | |
| KR101699585B1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN101399288A (en) | LDMOS chip light doped drift region structure and forming method | |
| CN103632974A (en) | Manufacturing method for improving in-plane uniformity of P type LDMOS surface channel device | |
| US20170288047A1 (en) | Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor | |
| US20160181400A1 (en) | LDMOS Device and Its Manufacturing Method | |
| CN105448916A (en) | Transistor and method of forming same | |
| CN106298939A (en) | A kind of accumulation type DMOS with complex media Rotating fields | |
| CN104518027B (en) | LDMOS device and its manufacturing method | |
| US11764296B2 (en) | Method for manufacturing a semiconductor device | |
| WO2022193656A1 (en) | Semiconductor device capable of reducing switching loss and manufacturing method therefor | |
| CN106887451B (en) | Super junction device and manufacturing method thereof | |
| CN208028069U (en) | Novel two-sided step buried oxide SOI LDMOS with buried structure | |
| CN107785367A (en) | It is integrated with the device and its manufacture method of depletion type junction field effect transistor | |
| CN104241358B (en) | Radio frequency ldmos device and manufacturing method thereof | |
| KR20130036501A (en) | Power mosfet having superjunction trench and fabrication method thereof | |
| CN104681438A (en) | Forming method of semiconductor device | |
| CN103594516A (en) | Semiconductor device and method of making the same | |
| CN104538441B (en) | Radio frequency LDMOS device and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |