CN104518027A - LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof - Google Patents
LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof Download PDFInfo
- Publication number
- CN104518027A CN104518027A CN201410262236.2A CN201410262236A CN104518027A CN 104518027 A CN104518027 A CN 104518027A CN 201410262236 A CN201410262236 A CN 201410262236A CN 104518027 A CN104518027 A CN 104518027A
- Authority
- CN
- China
- Prior art keywords
- drift region
- region
- polysilicon
- ldmos device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 183
- 229920005591 polysilicon Polymers 0.000 claims abstract description 183
- 239000000758 substrate Substances 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005468 ion implantation Methods 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 26
- 229910052760 oxygen Inorganic materials 0.000 claims description 26
- 239000001301 oxygen Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 230000001105 regulatory effect Effects 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000004088 simulation Methods 0.000 description 8
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses an LDMOS (laterally diffused metal oxide semiconductor) device and a manufacturing method thereof. A drift region of the LDMOS device comprises a first drift region and a second drift region; the first drift region is formed by an ion implantation region formed in a selected area of a silicon substrate; the second drift region is formed by doped polysilicon formed on the surface of the silicon substrate; the second drift region is overlapped on the first drift region, and a drain region is formed in the second drift region. Owing to arrangement of the second drift region, thickness of the whole drift region is increased, and accordingly parasitic resistance of the whole drift region is reduced while effectiveness in increase of linear current of the device and reduction of on resistance of the device can be achieved. In addition, the LDMOS device is capable of keeping high breakdown voltage and is low in process cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of lateral fet (LDMOS device; The invention still further relates to a kind of manufacture method of LDMOS device.
Background technology
Lateral fet (LDMOS) is the semiconductor high-voltage device generally used, and it is widely used in the fields such as power management, LCD and LED driving, esd protection.Application mode has simulation application and switch application two kinds usually.When LDMOS is used as switch, device is needed to have very low conducting resistance (the device source ohmic leakage of linear zone), to reduce switching power loss.In LDMOS, channel length is much smaller than drift region length, and the conducting resistance of device is dominated by drift zone resistance, therefore switch LDMOS needs to increase drift doping concentration as far as possible, reduce drift region length, increase drift region thickness, to reach the object reducing conducting resistance.But LDMOS must meet the requirement of puncture voltage, raising and the reducing of length of drift doping concentration are all subject to certain restrictions.Being increased in non-epitaxial technique of drift region thickness by macro-energy ion implantation and can only push away trap formation for a long time, but brings too much horizontal proliferation like this, causes excessive short-channel effect.The LDMOS of epitaxy can form thick drift region, but process costs improves.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of LDMOS device, and effectively can increase the linear current of device, reduce the conducting resistance of device, can keep higher puncture voltage, process costs is low.For this reason, the present invention also provides a kind of manufacture method of LDMOS device.
For solving the problems of the technologies described above, LDMOS device provided by the invention comprises:
The silicon substrate of the first conduction type doping.
First drift region, is made up of the second conductive type ion injection region be formed in the selection area of described silicon substrate.
Channel region, is made up of the first conduction type well region be formed in the selection area of described silicon substrate, and the first side and the described channel region of described first drift region contact in the horizontal.
Polysilicon gate, be formed at above described channel region, between described polysilicon gate and described silicon substrate, isolation has gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.
Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate.
Second drift region, the polysilicon adulterated by the second conduction type be formed in described surface of silicon forms, and described second drift region is positioned at the top of described first drift region and the bottom of described second drift region and described first drift region contact and superpose the drift region forming LDMOS device; First side of described second drift region near the second side of described polysilicon gate and the first side of described second drift region and the second side of described polysilicon gate are separated by a segment distance, the second side direction of described second drift region extends away from the direction of the second side of described polysilicon gate.
Drain region, is made up of the second conduction type heavily doped region be formed in described second drift region selection area, described drain region near the second side of described second drift region and the second side of described drain region and described polysilicon gate is separated by a lateral separation.
By the conducting resistance regulating the thickness of described second drift region to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region is less.
Further improvement is, the polysilicon of described second drift region and the polysilicon of described polysilicon gate adopt same process to be formed simultaneously.
Further improvement is, between first side bottom of described second drift region and described first drift region, there is described gate dielectric layer at interval, second side of described second drift region extends on the field oxygen separator outside the second side being positioned at described first drift region, and the described gate dielectric layer bottom described second drift region and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region.
Further improvement is, the first side of described second drift region and the second side of described polysilicon gate are isolated by silicon nitride spacer.
Further improvement is, impurity doping in place when the polysilicon deposition of described second drift region of described second drift region is formed or formed by ion implantation doping after deposition.
Further improvement is, described LDMOS device is N-type device, and described first conduction type is P type, and described second conduction type is N-type; Or described LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.
Further improvement is, described LDMOS device is symmetrical device; Or described LDMOS device is symmetrical device.
For solving the problems of the technologies described above, the manufacture method of LDMOS device provided by the invention comprises the steps:
Step one, the silicon substrate providing one first conduction type to adulterate; Fabricating yard oxygen separator on described silicon substrate.
Step 2, in the selection area of described silicon substrate carry out the first conduction type well region ion implantation formed channel region, the selection area forming described channel region is defined by photoetching process.
Step 3, adopt the second conductive type ion injection technology in the selection area of described silicon substrate, form the first drift region, the selection area forming described first drift region is defined by photoetching process; First side and the described channel region of described first drift region contact in the horizontal.
Step 4, furnace anneal process is carried out to described channel region and described first drift region.
Step 5, at described surface of silicon growth gate dielectric layer.
Step 6, adopt lithographic etch process to remove described gate dielectric layer part, the described gate dielectric layer of removed part is be positioned at described first drift region and the second follow-up drift region to contact the described gate dielectric layer in region.
Step 7, described substrate face depositing polysilicon after described gate dielectric layer etching; In described polysilicon deposition process, carry out the second conductive type impurity doping in place or undope.
Step 8, comprehensive ion implantation technology is adopted to carry out the second conductive type impurity doping to described polysilicon.
Step 9, the impurity of employing rapid thermal anneal process to described polysilicon process.
Step 10, employing lithographic etch process etch described polysilicon and form polysilicon gate and the second drift region simultaneously.
Described polysilicon gate is positioned at above described channel region and channel region described in described polysilicon gate cover part and extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.
Described second drift region is positioned at the top of described first drift region and the bottom of described second drift region and described first drift region contact and superpose the drift region forming LDMOS device; First side of described second drift region near the second side of described polysilicon gate and the first side of described second drift region and the second side of described polysilicon gate are separated by a segment distance, the second side direction of described second drift region extends away from the direction of the second side of described polysilicon gate; Between first side bottom of described second drift region and described first drift region, there is described gate dielectric layer at interval, second side of described second drift region extend to be positioned at described first drift region the second side outside described field oxygen separator on, the described gate dielectric layer bottom described second drift region and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region.
By the conducting resistance regulating the thickness of described second drift region to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region is less.
Step 11, thermal oxidation is carried out to the polysilicon surface of described polysilicon gate and described second drift region form a thermal oxide layer.
Step 12, deposition silicon nitride film, the side described silicon nitride film being dry-etched in described polysilicon gate and described second drift region forms silicon nitride spacer.
Step 13, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, and described source region is formed at the first side autoregistration of in described channel region and described source region and described polysilicon gate; Described drain region is formed in described second drift region selection area, described drain region near the second side of described second drift region and the second side of described drain region and described polysilicon gate is separated by a lateral separation.
Further improvement is, described LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the impurity of the ion implantation of channel region described in step 2 is boron or indium, the impurity of the doping in place of polysilicon described in step 7 is phosphorus, and the ion implanted impurity of polysilicon described in step 8 is phosphorus; Or, described LDMOS device is P type device, described first conduction type is N-type, described second conduction type is P type, the impurity of the ion implantation of channel region described in step 2 is phosphorus or arsenic, the impurity of the doping in place of polysilicon described in step 7 is boron, and the ion implanted impurity of polysilicon described in step 8 is boron, and the silicon substrate of the N-type doping in step one is made up of the dark N trap be formed in P-type silicon substrate.
Further improvement is, the temperature of the described furnace anneal in step 4 is 900 DEG C ~ 1200 DEG C, the time is 0.5 hour ~ 5 hours; The temperature of the described rapid thermal annealing in step 9 is 1000 DEG C, the time is for being greater than 10 seconds; The thickness of the described thermal oxide layer formed in step 11 is 20 dust ~ 100 dusts.
The first drift region of forming, diffusion region is injected and the second drift region of being made up of polysilicon doping is formed by stacking by being formed at substrate intermediate ion in drift region of the present invention, only inject diffusion region and form and compare by being formed at substrate intermediate ion with drift region of the prior art, the setting of the second drift region of the present invention can make the thickness of whole drift region increase, thus the dead resistance that can reduce whole drift region is less, and effectively can increase the linear current of device, the conducting resistance of reduction device; Meanwhile, the present invention does not need the doping content by increasing the first drift region and the second drift region to reduce the dead resistance of drift region, so device of the present invention can also keep higher puncture voltage; Second drift region of the present invention is made up of polysilicon, synchronously can be formed with polysilicon that polysilicon gate adopts, so process costs of the present invention is low.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of the embodiment of the present invention one LDMOS device;
Fig. 2 is the structural representation of the embodiment of the present invention two LDMOS device;
Fig. 3 A is semiconductor process simulation and device simulation instrument (Technology Computer AidedDesign, TCAD) the device simulation figure of existing LDMOS device;
Fig. 3 B is the TCAD device simulation figure of the embodiment of the present invention one LDMOS device;
Fig. 3 C is the linear sources leakage current of TCAD simulation and the relation curve comparison diagram of grid voltage of the embodiment of the present invention one and existing LDMOS device;
Fig. 4 A-Fig. 4 I is the structural representation of LDMOS device in each step of the embodiment of the present invention one method.
Embodiment
Embodiment of the present invention LDMOS device comprises:
The silicon substrate of the first conduction type doping.
First drift region, is made up of the second conductive type ion injection region be formed in the selection area of described silicon substrate.
Channel region, is made up of the first conduction type well region be formed in the selection area of described silicon substrate, and the first side and the described channel region of described first drift region contact in the horizontal.
Polysilicon gate, be formed at above described channel region, between described polysilicon gate and described silicon substrate, isolation has gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.
Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate.
Second drift region, the polysilicon adulterated by the second conduction type be formed in described surface of silicon forms, and described second drift region is positioned at the top of described first drift region and the bottom of described second drift region and described first drift region contact and superpose the drift region forming LDMOS device; First side of described second drift region near the second side of described polysilicon gate and the first side of described second drift region and the second side of described polysilicon gate are separated by a segment distance, the second side direction of described second drift region extends away from the direction of the second side of described polysilicon gate.
Drain region, is made up of the second conduction type heavily doped region be formed in described second drift region selection area, described drain region near the second side of described second drift region and the second side of described drain region and described polysilicon gate is separated by a lateral separation.
By the conducting resistance regulating the thickness of described second drift region to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region is less.
The polysilicon of described second drift region and the polysilicon of described polysilicon gate adopt same process to be formed simultaneously.
Between first side bottom of described second drift region and described first drift region, there is described gate dielectric layer at interval, second side of described second drift region extends on the field oxygen separator outside the second side being positioned at described first drift region, and the described gate dielectric layer bottom described second drift region and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region.
First side of described second drift region and the second side of described polysilicon gate are isolated by silicon nitride spacer.
Impurity doping in place when the polysilicon deposition of described second drift region of described second drift region is formed or is formed by ion implantation doping after deposition.
Embodiment of the present invention LDMOS device can be symmetrical device or symmetrical device.
Embodiment of the present invention LDMOS device can be N-type LDMOS and P type LDMOS device.As shown in Figure 1, be the structural representation of the embodiment of the present invention one LDMOS device; The embodiment of the present invention one LDMOS device is N-type LDMOS device, and the first conduction type is P type, and the second conduction type is N-type; The embodiment of the present invention one LDMOS device comprises:
The silicon substrate 101 of P type doping.Described silicon substrate 101 is formed with an oxygen separator 102.
First drift region 103, is made up of the N-type ion implanted region be formed in the selection area of described silicon substrate 101.
Channel region 104, is made up of the P type trap zone be formed in the selection area of described silicon substrate 101, and the first side and the described channel region 104 of described first drift region 103 contact in the horizontal.
Polysilicon gate 106, is formed at above described channel region 104, and between described polysilicon gate 106 and described silicon substrate 101, isolation has gate dielectric layer 105, and be preferably, described gate dielectric layer 5 is gate oxide; Channel region 104 described in described polysilicon gate 106 cover part also extends to above described first drift region 103, and the surface, described channel region 104 covered by described polysilicon gate 106 is for the formation of raceway groove.
Source region 108, is made up of the N-type heavily doped region be formed in described channel region 104, the first side autoregistration of described source region 108 and described polysilicon gate 106.
Second drift region 107, the polysilicon adulterated by the N-type be formed on described silicon substrate 101 surface forms, and described second drift region 107 is positioned at the top of described first drift region 103 and the bottom of described second drift region 107 and described first drift region 103 contact and superpose the drift region forming LDMOS device; First side of described second drift region 107 near the second side of described polysilicon gate 106 and described first side of the second drift region 107 and the second side of described polysilicon gate 106 are separated by a segment distance, the second side direction of described second drift region 107 extends away from the direction of the second side of described polysilicon gate 106.
The polysilicon of described second drift region 107 and the polysilicon of described polysilicon gate 106 adopt same process to be formed simultaneously.Described second drift region 107 be doped to N-type light dope, described polysilicon gate 106 be doped to N-type heavy doping, meet the needs as grid and drift region respectively.All be formed with thermal oxide layer 110 on the surface of described second drift region 107 and described polysilicon gate 106, be all formed with silicon nitride spacer 111 in the side of described second drift region 107 and described polysilicon gate 106.Described first side of the second drift region 107 and the second side of described polysilicon gate 106 are isolated by silicon nitride spacer 111.Impurity doping in place when the polysilicon deposition of described second drift region 107 of described second drift region 107 is formed or is formed by ion implantation doping after deposition.
Drain region 109, is made up of the N-type heavily doped region be formed in described second drift region 107 selection area, described drain region 109 near the second side of described second drift region 107 and the second side of described drain region 109 and described polysilicon gate 106 is separated by a lateral separation.
In the embodiment of the present invention one, by the conducting resistance regulating the thickness of described second drift region 107 to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region 107 is less.
Be preferably, between first side bottom of described second drift region 107 and described first drift region 103, there is described gate dielectric layer 105 at interval, second side of described second drift region 107 extends on the field oxygen separator 102 outside the second side being positioned at described first drift region 103, and the described gate dielectric layer 105 bottom described second drift region 107 and described field oxygen separator 102 are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region 107.
As shown in Figure 2, be the structural representation of the embodiment of the present invention two LDMOS device; The embodiment of the present invention two LDMOS device is P type LDMOS device, and described first conduction type is N-type, and described second conduction type is P type.The exchange being carried out P type and N-type by the conduction type of the doping to the embodiment of the present invention one can obtain the embodiment of the present invention two LDMOS device structure; Be specially, the embodiment of the present invention two LDMOS device comprises:
The silicon substrate 200 of N-type doping, silicon substrate 200 described in the embodiment of the present invention two still selects P type doped structure, is realized silicon substrate 200 structure of N-type doping by the dark N trap 201 forming N-type doping in P-type silicon substrate 200.Described silicon substrate 101 is formed with an oxygen separator 202.
First drift region 203, by be formed at described silicon substrate 200 dark N trap 201 selection area in P type ion implanted region form.
Channel region 204, by be formed at described silicon substrate 200 dark N trap 201 selection area in N-type well region form, the first side and the described channel region 204 of described first drift region 203 contact in the horizontal.
Polysilicon gate 206, is formed at above described channel region 204, and between the dark N trap 201 of described polysilicon gate 206 and described silicon substrate 200, isolation has gate dielectric layer 205, and be preferably, described gate dielectric layer 205 is gate oxide; Channel region 204 described in described polysilicon gate 206 cover part also extends to above described first drift region 203, and the surface, described channel region 204 covered by described polysilicon gate 206 is for the formation of raceway groove.
Source region 208, is made up of the P type heavily doped region be formed in described channel region 204, the first side autoregistration of described source region 208 and described polysilicon gate 206.
Second drift region 207, the polysilicon adulterated by the P type be formed on dark N trap 201 surface of described silicon substrate 200 forms; The polysilicon of described second drift region 207 and the polysilicon of described polysilicon gate 206 adopt same process to be formed simultaneously.The P type that the is doped to light dope of described second drift region 207, the P type that the is doped to heavy doping of described polysilicon gate 206, meets the needs as grid and drift region respectively.
Described second drift region 207 is positioned at the top of described first drift region 203 and the bottom of described second drift region 207 and described first drift region 203 contact and superpose the drift region forming LDMOS device; First side of described second drift region 207 near the second side of described polysilicon gate 206 and described first side of the second drift region 207 and the second side of described polysilicon gate 206 are separated by a segment distance, the second side direction of described second drift region 207 extends away from the direction of the second side of described polysilicon gate 206.
All be formed with thermal oxide layer 210 on the surface of described second drift region 207 and described polysilicon gate 206, be all formed with silicon nitride spacer 211 in the side of described second drift region 207 and described polysilicon gate 206.Described first side of the second drift region 207 and the second side of described polysilicon gate 206 are isolated by silicon nitride spacer 211.Impurity doping in place when the polysilicon deposition of described second drift region 207 of described second drift region 207 is formed or is formed by ion implantation doping after deposition.
Between first side bottom of described second drift region 207 and described first drift region 203, there is described gate dielectric layer 205 at interval, second side of described second drift region 207 extends on the field oxygen separator 202 outside the second side being positioned at described first drift region 203, and the described gate dielectric layer 205 bottom described second drift region 207 and described field oxygen separator 202 are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region 207.
Drain region 209, is made up of the P type heavily doped region be formed in described second drift region 207 selection area, described drain region 209 near the second side of described second drift region 207 and the second side of described drain region 209 and described polysilicon gate 206 is separated by a lateral separation.
By the conducting resistance regulating the thickness of described second drift region 207 to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region 207 is less.
As shown in figs.3 a and 3b, be the TCAD device simulation figure of existing LDMOS device and the embodiment of the present invention one LDMOS device respectively; Fig. 3 C is the linear sources leakage current of TCAD simulation and the relation curve comparison diagram of grid voltage of the embodiment of the present invention one and existing LDMOS device; Known, after the embodiment of the present invention one LDMOS device adds second drift region be made up of polysilicon than existing LDMOS device, the thickness of drift region can increase, can reduce the dead resistance of whole drift region, curve in Fig. 3 C 301 corresponds to the relation curve of the linear sources leakage current of existing LDMOS device and grid voltage, curve 302 corresponds to the linear sources leakage current of the embodiment of the present invention one LDMOS device and the relation curve of grid voltage, the linear current of the known embodiment of the present invention one LDMOS device is increased, and the conducting resistance of device is reduced; This fully demonstrates the linear current that really effectively can increase device after the embodiment of the present invention one adds the second drift region, the conducting resistance reducing device, can keep higher puncture voltage.
As shown in Fig. 4 A to Fig. 4 I, it is the structural representation of LDMOS device in each step of the embodiment of the present invention one method.The manufacture method of the embodiment of the present invention one LDMOS device comprises the steps:
Step one, as shown in Figure 4 A, provides the silicon substrate 101 of a P type doping; Fabricating yard oxygen separator 102 on described silicon substrate 101.Field oxygen separator 102 is local field oxygen separator (LOCOS) or shallow groove isolation layer (STI).
Step 2, as shown in Figure 4 B, the ion implantation of carrying out P type trap zone in the selection area of described silicon substrate 101 forms channel region 104, and the selection area forming described channel region 104 is defined by photoetching process.The impurity of the ion implantation of described channel region 104 is boron or indium, and ion implantation can be adopted repeatedly to be formed.
Step 3, as shown in Figure 4 C, adopt N-type ion implantation technology in the selection area of described silicon substrate 101, form the first drift region 103, the selection area forming described first drift region 103 is defined by photoetching process; First side and the described channel region 104 of described first drift region 103 contact in the horizontal.The impurity of the ion implantation of described first drift region 103 is generally phosphorus, and the repeatedly ion implantation of different-energy can be adopted to be formed.
Step 4, as shown in Figure 4 C, furnace anneal process is carried out to described channel region 104 and described first drift region 103.Be preferably, the temperature of described furnace anneal is 900 DEG C ~ 1200 DEG C, the time is 0.5 hour ~ 5 hours.
Step 5, as shown in Figure 4 D, at described silicon substrate 101 superficial growth gate dielectric layer 105, be preferably, described gate dielectric layer 105 is gate oxide.
Step 6, as shown in Figure 4 E, adopt lithographic etch process to remove described gate dielectric layer 105 part, the described gate dielectric layer of removed part 105 to contact the described gate dielectric layer 105 in region for being positioned at described first drift region 103 and the second follow-up drift region 107.
Step 7, as illustrated in figure 4f, the described substrate face depositing polysilicon 106a after described gate dielectric layer 105 etches; In described polysilicon 106a deposition process, carry out N-type impurity doping in place or undope, the impurity being preferably N-type in place doping is phosphorus.
Step 8, as illustrated in figure 4f, comprehensive ion implantation technology is adopted to carry out N-type impurity doping to described polysilicon 106a.Be preferably, the ion implanted impurity of described polysilicon is phosphorus.
Step 9, as illustrated in figure 4f, adopts the impurity of rapid thermal anneal process to described polysilicon 106a to process.Be preferably, the temperature of described rapid thermal annealing is 1000 DEG C, the time is for being greater than 10 seconds.
Step 10, as shown in Figure 4 G, adopts lithographic etch process to etch described polysilicon and forms polysilicon gate 106 and the second drift region 107 simultaneously.
Described polysilicon gate 106 is positioned at above described channel region 104 and channel region 104 described in described polysilicon gate 106 cover part and extends to above described first drift region 103, and the surface, described channel region 104 covered by described polysilicon gate 106 is for the formation of raceway groove.
Described second drift region 107 is positioned at the top of described first drift region 103 and the bottom of described second drift region 107 and described first drift region 103 contact and superpose the drift region forming LDMOS device; First side of described second drift region 107 near the second side of described polysilicon gate 106 and described first side of the second drift region 107 and the second side of described polysilicon gate 106 are separated by a segment distance, the second side direction of described second drift region 107 extends away from the direction of the second side of described polysilicon gate 106; Between first side bottom of described second drift region 107 and described first drift region 103, there is described gate dielectric layer 105 at interval, second side of described second drift region 107 extends on the described field oxygen separator 102 outside the second side being positioned at described first drift region 103, and the described gate dielectric layer 105 bottom described second drift region 107 and described field oxygen separator 102 are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region 107.
By the conducting resistance regulating the thickness of described second drift region 107 to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region 107 is less.
Step 11, as shown at figure 4h, carries out thermal oxidation to the polysilicon surface of described polysilicon gate 106 and described second drift region 107 and forms a thermal oxide layer 110.Be preferably, the thickness of described thermal oxide layer 110 is 20 dust ~ 100 dusts.
Step 12, as shown in fig. 41, deposition silicon nitride film, the side described silicon nitride film being dry-etched in described polysilicon gate 106 and described second drift region 107 forms silicon nitride spacer 111.
Step 13, as shown in Figure 1, carry out N-type heavy doping ion and inject and form source region 108 and drain region 109, described source region 108 is formed at the first side autoregistration of in described channel region 104 and described source region 108 and described polysilicon gate 106; Described drain region 109 is formed in described second drift region 107 selection area, described drain region 109 near the second side of described second drift region 107 and the second side of described drain region 109 and described polysilicon gate 106 is separated by a lateral separation.
Following steps please refer to shown in Fig. 2, and the manufacture method of the embodiment of the present invention two LDMOS device comprises the steps:
Step one, the silicon substrate providing a N-type to adulterate; Fabricating yard oxygen separator on described silicon substrate.In the embodiment of the present invention, the silicon substrate of N-type doping adopts the silicon substrate 200 of P type doping to add that the dark N trap 201 be formed in P-type silicon substrate 200 is replaced.
Step 2, in the selection area of the dark N trap 201 of described silicon substrate 200 carry out N-type well region ion implantation formed channel region 204, the selection area forming described channel region 204 is defined by photoetching process.
Step 3, employing P type ion implantation technology form the first drift region 203 in the selection area of the dark N trap 201 of described silicon substrate 200, and the selection area forming described first drift region 203 is defined by photoetching process; First side and the described channel region 204 of described first drift region 203 contact in the horizontal.
Step 4, furnace anneal process is carried out to described channel region 204 and described first drift region 203.Be preferably, the temperature of described furnace anneal is 900 DEG C ~ 1200 DEG C, the time is 0.5 hour ~ 5 hours.
Step 5, dark N trap 201 superficial growth gate dielectric layer 205 at described silicon substrate 200.Be preferably, described gate dielectric layer 205 is gate oxide.
Step 6, adopt lithographic etch process to remove described gate dielectric layer 205 part, the described gate dielectric layer of removed part 205 to contact the described gate dielectric layer 205 in region for being positioned at described first drift region 203 and the second follow-up drift region 207.
Step 7, described substrate face depositing polysilicon after described gate dielectric layer 205 etches; In described polysilicon deposition process, carry out p type impurity doping in place or undope; The impurity being preferably P type in place doping is boron.
Step 8, comprehensive ion implantation technology is adopted to carry out p type impurity doping to described polysilicon.Be preferably, the ion implanted impurity of described polysilicon is boron.
Step 9, the impurity of employing rapid thermal anneal process to described polysilicon process.Be preferably, the temperature of described rapid thermal annealing is 1000 DEG C, the time is for being greater than 10 seconds.
Step 10, employing lithographic etch process etch described polysilicon and form polysilicon gate 206 and the second drift region 207 simultaneously.
Described polysilicon gate 206 is positioned at above described channel region 204 and channel region 204 described in described polysilicon gate 206 cover part and extends to above described first drift region 203, and the surface, described channel region 204 covered by described polysilicon gate 206 is for the formation of raceway groove.
Described second drift region 207 is positioned at the top of described first drift region 203 and the bottom of described second drift region 207 and described first drift region 203 contact and superpose the drift region forming LDMOS device; First side of described second drift region 207 near the second side of described polysilicon gate 206 and described first side of the second drift region 207 and the second side of described polysilicon gate 206 are separated by a segment distance, the second side direction of described second drift region 207 extends away from the direction of the second side of described polysilicon gate 206; Between first side bottom of described second drift region 207 and described first drift region 203, there is described gate dielectric layer 205 at interval, second side of described second drift region 207 extends on the described field oxygen separator outside the second side being positioned at described first drift region 203, and the described gate dielectric layer 205 bottom described second drift region 207 and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region 207.
By the conducting resistance regulating the thickness of described second drift region 207 to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region 207 is less.
Step 11, thermal oxidation is carried out to the polysilicon surface of described polysilicon gate 206 and described second drift region 207 form a thermal oxide layer 210.Be preferably, the thickness of described thermal oxide layer 210 is 20 dust ~ 100 dusts.
Step 12, deposition silicon nitride film, the side described silicon nitride film being dry-etched in described polysilicon gate 206 and described second drift region 207 forms silicon nitride spacer 211.
Step 13, P type heavy doping ion of carrying out are injected and are formed source region 208 and drain region 209, and described source region 208 is formed at the first side autoregistration of in described channel region 204 and described source region 208 and described polysilicon gate 206; Described drain region 209 is formed in described second drift region 207 selection area, described drain region 209 near the second side of described second drift region 207 and the second side of described drain region 209 and described polysilicon gate 206 is separated by a lateral separation.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a LDMOS device, is characterized in that, comprising:
The silicon substrate of the first conduction type doping;
First drift region, is made up of the second conductive type ion injection region be formed in the selection area of described silicon substrate;
Channel region, is made up of the first conduction type well region be formed in the selection area of described silicon substrate, and the first side and the described channel region of described first drift region contact in the horizontal;
Polysilicon gate, be formed at above described channel region, between described polysilicon gate and described silicon substrate, isolation has gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;
Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate;
Second drift region, the polysilicon adulterated by the second conduction type be formed in described surface of silicon forms, and described second drift region is positioned at the top of described first drift region and the bottom of described second drift region and described first drift region contact and superpose the drift region forming LDMOS device; First side of described second drift region near the second side of described polysilicon gate and the first side of described second drift region and the second side of described polysilicon gate are separated by a segment distance, the second side direction of described second drift region extends away from the direction of the second side of described polysilicon gate;
Drain region, is made up of the second conduction type heavily doped region be formed in described second drift region selection area, described drain region near the second side of described second drift region and the second side of described drain region and described polysilicon gate is separated by a lateral separation;
By the conducting resistance regulating the thickness of described second drift region to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region is less.
2. LDMOS device as claimed in claim 1, is characterized in that: the polysilicon of described second drift region and the polysilicon of described polysilicon gate adopt same process to be formed simultaneously.
3. LDMOS device as claimed in claim 1 or 2, it is characterized in that: between the first side bottom of described second drift region and described first drift region, there is described gate dielectric layer at interval, second side of described second drift region extends on the field oxygen separator outside the second side being positioned at described first drift region, and the described gate dielectric layer bottom described second drift region and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region.
4. LDMOS device as claimed in claim 1 or 2, is characterized in that: the first side of described second drift region and the second side of described polysilicon gate are isolated by silicon nitride spacer.
5. LDMOS device as claimed in claim 1 or 2, is characterized in that: impurity doping in place when the polysilicon deposition of described second drift region of described second drift region is formed or formed by ion implantation doping after deposition.
6. LDMOS device as claimed in claim 1 or 2, it is characterized in that: described LDMOS device is N-type device, described first conduction type is P type, and described second conduction type is N-type; Or described LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.
7. LDMOS device as claimed in claim 1 or 2, is characterized in that: described LDMOS device is symmetrical device; Or described LDMOS device is symmetrical device.
8. a manufacture method for LDMOS device, is characterized in that, comprises the steps:
Step one, the silicon substrate providing one first conduction type to adulterate; Fabricating yard oxygen separator on described silicon substrate;
Step 2, in the selection area of described silicon substrate carry out the first conduction type well region ion implantation formed channel region, the selection area forming described channel region is defined by photoetching process;
Step 3, adopt the second conductive type ion injection technology in the selection area of described silicon substrate, form the first drift region, the selection area forming described first drift region is defined by photoetching process; First side and the described channel region of described first drift region contact in the horizontal;
Step 4, furnace anneal process is carried out to described channel region and described first drift region;
Step 5, at described surface of silicon growth gate dielectric layer;
Step 6, adopt lithographic etch process to remove described gate dielectric layer part, the described gate dielectric layer of removed part is be positioned at described first drift region and the second follow-up drift region to contact the described gate dielectric layer in region;
Step 7, described substrate face depositing polysilicon after described gate dielectric layer etching; In described polysilicon deposition process, carry out the second conductive type impurity doping in place or undope;
Step 8, comprehensive ion implantation technology is adopted to carry out the second conductive type impurity doping to described polysilicon;
Step 9, the impurity of employing rapid thermal anneal process to described polysilicon process;
Step 10, employing lithographic etch process etch described polysilicon and form polysilicon gate and the second drift region simultaneously;
Described polysilicon gate is positioned at above described channel region and channel region described in described polysilicon gate cover part and extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;
Described second drift region is positioned at the top of described first drift region and the bottom of described second drift region and described first drift region contact and superpose the drift region forming LDMOS device; First side of described second drift region near the second side of described polysilicon gate and the first side of described second drift region and the second side of described polysilicon gate are separated by a segment distance, the second side direction of described second drift region extends away from the direction of the second side of described polysilicon gate; Between first side bottom of described second drift region and described first drift region, there is described gate dielectric layer at interval, second side of described second drift region extend to be positioned at described first drift region the second side outside described field oxygen separator on, the described gate dielectric layer bottom described second drift region and described field oxygen separator are used as the terminal of etching polysilicon thus facilitate the etching of the polysilicon of described second drift region;
By the conducting resistance regulating the thickness of described second drift region to regulate described LDMOS device, the conducting resistance of less, the described LDMOS device of dead resistance of the drift region of larger, the described LDMOS device of thickness of described second drift region is less;
Step 11, thermal oxidation is carried out to the polysilicon surface of described polysilicon gate and described second drift region form a thermal oxide layer;
Step 12, deposition silicon nitride film, the side described silicon nitride film being dry-etched in described polysilicon gate and described second drift region forms silicon nitride spacer;
Step 13, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, and described source region is formed at the first side autoregistration of in described channel region and described source region and described polysilicon gate; Described drain region is formed in described second drift region selection area, described drain region near the second side of described second drift region and the second side of described drain region and described polysilicon gate is separated by a lateral separation.
9. method as claimed in claim 8, it is characterized in that: described LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the impurity of the ion implantation of channel region described in step 2 is boron or indium, the impurity of the doping in place of polysilicon described in step 7 is phosphorus, and the ion implanted impurity of polysilicon described in step 8 is phosphorus; Or, described LDMOS device is P type device, described first conduction type is N-type, described second conduction type is P type, the impurity of the ion implantation of channel region described in step 2 is phosphorus or arsenic, the impurity of the doping in place of polysilicon described in step 7 is boron, and the ion implanted impurity of polysilicon described in step 8 is boron, and the silicon substrate of the N-type doping in step one is made up of the dark N trap be formed in P-type silicon substrate.
10. method as described in claim 8 or 9, is characterized in that: the temperature of the described furnace anneal in step 4 is 900 DEG C ~ 1200 DEG C, the time is 0.5 hour ~ 5 hours; The temperature of the described rapid thermal annealing in step 9 is 1000 DEG C, the time is for being greater than 10 seconds; The thickness of the described thermal oxide layer formed in step 11 is 20 dust ~ 100 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410262236.2A CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410262236.2A CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104518027A true CN104518027A (en) | 2015-04-15 |
| CN104518027B CN104518027B (en) | 2019-06-11 |
Family
ID=52793044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410262236.2A Active CN104518027B (en) | 2014-06-13 | 2014-06-13 | LDMOS device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104518027B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298744A (en) * | 2015-05-11 | 2017-01-04 | 北大方正集团有限公司 | The preparation method of power device and power device |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
| CN110291620A (en) * | 2017-02-14 | 2019-09-27 | 日产自动车株式会社 | The manufacturing method of semiconductor device and semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
| CN103035671A (en) * | 2012-08-20 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) device and manufacture method thereof |
-
2014
- 2014-06-13 CN CN201410262236.2A patent/CN104518027B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777363A (en) * | 1993-11-29 | 1998-07-07 | Texas Instruments Incorporated | Semiconductor device with composite drift region |
| CN103035671A (en) * | 2012-08-20 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) device and manufacture method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298744A (en) * | 2015-05-11 | 2017-01-04 | 北大方正集团有限公司 | The preparation method of power device and power device |
| CN106298744B (en) * | 2015-05-11 | 2018-12-11 | 北大方正集团有限公司 | The preparation method and power device of power device |
| CN110291620A (en) * | 2017-02-14 | 2019-09-27 | 日产自动车株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN110291620B (en) * | 2017-02-14 | 2020-07-14 | 日产自动车株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104518027B (en) | 2019-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9450056B2 (en) | Lateral DMOS device with dummy gate | |
| US9825149B2 (en) | Split gate power semiconductor field effect transistor | |
| US9041102B2 (en) | Power transistor and associated method for manufacturing | |
| US7989293B2 (en) | Trench device structure and fabrication | |
| US9997605B2 (en) | LDMOS device and its manufacturing method | |
| KR101699585B1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN107425046B (en) | LDMOS device and manufacturing method thereof | |
| US8482066B2 (en) | Semiconductor device | |
| CN102751332B (en) | Depletion type power semiconductor device and manufacturing method thereof | |
| CN102610641B (en) | High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| US9178054B2 (en) | Planar vertical DMOS transistor with reduced gate charge | |
| US9184278B2 (en) | Planar vertical DMOS transistor with a conductive spacer structure as gate | |
| US8575688B2 (en) | Trench device structure and fabrication | |
| CN103855210A (en) | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof | |
| US11309406B2 (en) | Method of manufacturing an LDMOS device having a well region below a groove | |
| CN109273364B (en) | Semiconductor structure and forming method thereof | |
| CN104518027A (en) | LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN103545346A (en) | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| US11107917B2 (en) | High voltage semiconductor device and manufacturing method thereof | |
| US20180269322A1 (en) | Power MOSFETs with Superior High Frequency Figure-of-Merit and Methods of Forming Same | |
| CN202736927U (en) | Depletion type power semiconductor device | |
| US9543149B2 (en) | High voltage lateral extended drain MOS transistor with improved drift layer contact | |
| CN103730517A (en) | Junction field effect transistor and manufacturing method thereof | |
| CN108899282B (en) | Trench gate field effect transistor with charge balance structure and manufacturing method thereof | |
| CN102130166A (en) | Dddmos device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |