CN103035671A - Laterally diffused metal oxide semiconductor (LDMOS) device and manufacture method thereof - Google Patents

Laterally diffused metal oxide semiconductor (LDMOS) device and manufacture method thereof Download PDF

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CN103035671A
CN103035671A CN2012102971260A CN201210297126A CN103035671A CN 103035671 A CN103035671 A CN 103035671A CN 2012102971260 A CN2012102971260 A CN 2012102971260A CN 201210297126 A CN201210297126 A CN 201210297126A CN 103035671 A CN103035671 A CN 103035671A
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drift region
conduction type
extension
ldmos device
type
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CN103035671B (en
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钱文生
李娟娟
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention discloses a laterally diffused metal oxide semiconductor (LDMOS) device. A second conduction type drift region is arranged between a channel and a drain terminal, the upper surface of the drift region is horizontal, at least one second conduction type epitaxy drift region is arranged on the drift region, the epitaxy drift region is only distributed above one side, close to the channel, of the drift region, and the first conduction type and the second conduction type are respectively in a p shape and in an n shape. In an embodiment, the upper surface of the epitaxy drift region is in a horizontal shape. In another embodiment, the upper surface of the epitaxy drift region is in a step shape, the thickness of the epitaxy layer progressively decreases in the direction from the channel to the drain terminal. The invention further discloses a manufacture method of the LDMOS device. The drift region and the epitaxy drift region can joint form a work drift region of the LDMOS device. The thickness of one side, close to the channel, of the work drift region is increased so as to effectively reduce on resistance of the LDMOS device and achieve high breakdown voltage.

Description

LDMOS device and manufacture method thereof
Technical field
The application relates to a kind of semiconductor device, particularly relates to LDMOS(Laterally Diffused MOS, laterally diffused MOS transistor) device.
Background technology
The LDMOS device is through being often used as device for power switching.See also Fig. 1, this is a kind of schematic diagram of existing N-shaped LDMOS device.In p-type substrate (or epitaxial loayer) 10, have laterally adjacent p-type doped region 11 and N-shaped drift region 12.The upper surface of N-shaped drift region 12 is horizontal.Has N-shaped heavy doping source 19 in the centre position of p-type doped region 11.One end of gate oxide 13 is on N-shaped drift region 12, and the other end is on N-shaped heavy doping source 19, and mid portion is on p-type doped region 11.Has grid 14 on the gate oxide 13.The both sides of gate oxide 13 and grid 14 have side wall 15.Has N-shaped heavy doping drain terminal 20 in N-shaped drift region 12 away from an end of p-type doped region 11.Has p-type heavy doping raceway groove exit 21 at p-type doped region 11 away from an end of N-shaped drift region 12.The p-type doped region 11 of gate oxide 13 belows is raceway grooves of device.
If the basis at Fig. 1 a increases a n trap, this n trap is in p-type substrate (or epitaxial loayer) 10, and N-shaped doped region 11 ' and p-type drift region 12 ' be all in the n trap that this increases newly, and all the other each several part structures are identical, but doping type is opposite, then is the p-type LDMOS device of non-channel isolation type.
Above-mentioned LDMOS device is non-channel isolation type, also has the LDMOS device of a class channel isolation type.If the basis at Fig. 1 a increases a n trap, this n trap is in p-type substrate (or epitaxial loayer) 10, and p-type doped region 11 and N-shaped drift region 12 be all in the n trap that this increases newly, and all the other each several part structures are identical, doping type is also identical, then is the N-shaped LDMOS device of channel isolation type.
In order to reduce power consumption, need the LDMOS device to have alap conducting resistance.Therefore when designs, always reduce as much as possible the length (the size A among Fig. 1 a) of drift region and/or improve the doping content of drift region, to reduce the series resistance of drift region.The LDMOS device all is high tension apparatus, and puncture voltage is its important characterisitic parameter.In order to improve puncture voltage, need the LDMOS device to have as far as possible larger drift region length and lower drift region doping content.Obviously, the conducting resistance of LDMOS device and puncture voltage are a pair of technical indicators that needs balance, and existing LDMOS device is difficult to take into account.
Summary of the invention
The application's technical problem to be solved provides a kind of LDMOS device of brand new, can obtain simultaneously lower conducting resistance and higher puncture voltage.
For solving the problems of the technologies described above, the application LDMOS device has the drift region of the second conduction type between raceway groove and drain terminal, the upper surface level of described drift region, the extension drift region that has at least one the second conduction type on described drift region, described extension drift region only are distributed in described drift region near the top of raceway groove one side;
Described the first conduction type, the second conduction type are respectively p-type, N-shaped; Perhaps opposite.
In one embodiment, the upper surface of described extension drift region is horizontal.
In another embodiment, the upper surface of described extension drift region is stepped, and on the direction from the raceway groove to the drain terminal thickness monotone decreasing (not being strictly monotone decreasing) of this epitaxial loayer.
In two embodiment, the extension drift region all can be one or more.When having polylith extension drift region, can be close between them, also can be at a distance of a segment distance.
Described extension drift region is if N-shaped mixes, and impurity is preferably arsenic or phosphorus; If p-type is mixed, impurity is preferably boron.
The doping content of described extension drift region is 0.5 times～2 times of doping content of drift region.
The thickness of described extension drift region is 0.1 times～1 times of drift region thickness.
The manufacture method of the described LDMOS device of the application comprises the steps:
In the 1st step, in the substrate of the first conduction type, adopt ion implantation technology to form the doped region of the first laterally adjacent conduction type and the drift region of the second conduction type;
The 2nd step, silicon chip form gate oxide and on polysilicon gate, gate oxide is across the line of demarcation of doped region and drift region;
In the 3rd step, form side wall in the both sides of gate oxide and polysilicon gate;
Form the heavy doping source of the second conduction type in the centre position of doped region, between heavy doping source and the drift region and the part doped region of adjacent gate oxide be exactly the raceway groove of LDMOS device;
Form the heavy doping drain terminal of the second conduction type away from that end of gate oxide in the drift region;
In doped region, form the heavy doping raceway groove exit of the first conduction type away from that end of gate oxide;
The 4th step, at silicon chip surface deposit one deck dielectric layer, then adopt photoetching process to expose the extension window in described drift region near the side wall place, and in this extension window, grow the extension drift region of the second conduction type with extension and in-situ doped technique, remove at last dielectric layer;
Described the first conduction type, the second conduction type are respectively p-type, N-shaped; Perhaps opposite.
The 4th step of said method is applicable to form the epitaxial loayer of upper surface level.
If the stepped epitaxial loayer of upper surface, the 4th step of said method changes into:
The 4a step, at silicon chip surface deposit n dielectric layer, then adopt photoetching process to expose n extension window in described drift region near the side wall place, and in this n extension window, grow n extension drift region with extension and in-situ doped technique, remove at last the n dielectric layer; Described n is natural number;
Repeat 4a step 1 time to repeatedly, each formed extension drift region is all on the next door of upper once formed extension drift region, can be to be close to or at a distance of a segment distance.
In the described LDMOS device of the application, the drift region of the second conduction type and extension drift region are jointly as the drift region of LDMOS device when working.The thickness of this work drift region is in raceway groove monotone decreasing (being non-strictly monotone increasing) on the direction of drain terminal, at the easy depleted region deposit silicon epitaxy layer identical with the drift region conduction type near grid.When drain terminal added high pressure, this work drift region still can all exhaust, and this is so that the LDMOS device can bear higher puncture voltage.Epitaxial loayer preferably adopts original position (in place) to mix, and can control well the horizontal proliferation of impurity, and the impurity in the silicon epitaxy layer just can not increase the doping content of drift region, below like this, also can not increase the ionization by collision of device.Because there is increase the work drift region near the thickness of raceway groove one side, has effectively reduced the conducting resistance of LDMOS device.Therefore, the application's LDMOS device can obtain high-breakdown-voltage and low on-resistance simultaneously, and device property improves a lot than traditional devices.
Description of drawings
Fig. 1 is the vertical cut-away schematic view of existing N-shaped LDMOS device;
Fig. 2 a is the vertical cut-away schematic view of embodiment one of the application's N-shaped LDMOS device;
Fig. 2 b is the vertical cut-away schematic view of embodiment one of the application's p-type LDMOS device;
Fig. 3 a is the vertical cut-away schematic view of embodiment two of the application's N-shaped LDMOS device;
Fig. 3 b is the vertical cut-away schematic view of embodiment two of the application's p-type LDMOS device;
Fig. 4 a to Fig. 4 f is the manufacture method schematic diagram of embodiment two of the application's N-shaped LDMOS device.
Description of reference numerals among the figure:
10 is p-type silicon substrate (or epitaxial loayer); 11 is the p-type raceway groove; 11 ' is the N-shaped raceway groove; 12 is the N-shaped drift region; 12 ' is the p-type drift region; 13 is gate oxide; 14 is polysilicon gate; 15 is side wall; 16 is the first medium layer; 17 is the second medium layer; 18 is the 3rd dielectric layer; 19 is N-shaped heavy doping source; 19 ' is p-type heavy doping source; 20 is N-shaped heavy doping drain terminal; 20 ' is p-type heavy doping drain terminal; 21 is p-type heavy doping raceway groove exit; 21 ' is N-shaped heavy doping raceway groove draw-out area; 80 is N-shaped extension drift region; 80 ' is p-type extension drift region; 81 is N-shaped the first extension drift region; 81 ' is p-type the first extension drift region; 82 is N-shaped the second extension drift region; 82 ' is p-type the second extension drift region; 83 is N-shaped the 3rd extension drift region; 83 ' is p-type the 3rd extension drift region; 90 is the n trap.
Embodiment
See also Fig. 2 a, this is the embodiment one of N-shaped LDMOS device of the application's non-channel isolation type.In p-type substrate (or epitaxial loayer) 10, have laterally adjacent p-type doped region 11 and N-shaped drift region 12.The upper surface of N-shaped drift region 12 is horizontal.Has N-shaped heavy doping source 19 in the centre position of p-type doped region 11.One end of gate oxide 13 is on N-shaped drift region 12, and the other end is on N-shaped heavy doping source 19, and mid portion is on p-type doped region 11.Has grid 14 on the gate oxide 13.The both sides of gate oxide 13 and grid 14 have side wall 15.Has N-shaped heavy doping drain terminal 20 in N-shaped drift region 12 away from an end of p-type doped region 11.Has p-type heavy doping raceway groove exit 21 at p-type doped region 11 away from an end of N-shaped drift region 12.The p-type doped region 11 of gate oxide 13 belows is raceway grooves of device.The difference of itself and existing LDMOS device only is: have a N-shaped extension drift region 80 on N-shaped drift region 12, the upper surface level of described N-shaped extension drift region 80, described N-shaped extension drift region 80 only are distributed in N-shaped drift region 12 near the top of raceway groove one side.More specifically, described N-shaped epitaxial loayer 80 next-door neighbour's side walls 15, and and have a segment distance between the N-shaped heavy doping drain terminal 20.
Replacedly, the N-shaped extension drift region 80 of a monoblock also can be divided into polylith among Fig. 2 a, and all keeping upper surface between this polylith is sustained height, and (and and side wall 15 between) can be close to each other between this polylith, also can be each other at a distance of a segment distance.
Increase n trap 90 on Fig. 2 a basis, this n trap 90 and surrounds N-shaped doped region 11 ' and p-type drift region 12 ' in p-type substrate (or epitaxial loayer) 10, the identical but doping type of all the other each several part structures becomes on the contrary, then formed the embodiment one of the application's p-type LDMOS device, shown in Fig. 2 b.
Increase n trap 90 on Fig. 2 a basis, this n trap 90 is in p-type substrate (or epitaxial loayer) 10, and encirclement p-type doped region 11 and N-shaped drift region 12, all the other each several part structures are identical, doping type is also identical, has then formed the embodiment one of N-shaped LDMOS device of the application's channel isolation type, and is not shown.
See also Fig. 3 a, this is the embodiment two of N-shaped LDMOS device of the application's non-channel isolation type.The difference of itself and existing LDMOS device only is: have three N-shaped epitaxial loayers 81,82,83 on N-shaped drift region 12, described three N-shaped epitaxial loayers 81,82,83 only are distributed in N-shaped drift region 12 near the top of raceway groove one sides.More specifically, described three N-shaped epitaxial loayers 81,82,83 next-door neighbour's side walls 15, and and have a segment distance between the N-shaped heavy doping drain terminal 20.The above three N-shaped epitaxial loayer 81 of direction from raceway groove to N-shaped heavy doping drain terminal 20,82,83 thickness monotone decreasing are like this as just stepped by the upper surface of these the three N-shaped extension drift regions that form.Alternatively, (and and side wall 15 between) can be mutually adjacent between described three N-shaped epitaxial loayers 81,82,83, also can space one segment distance.
Increase n trap 90 on Fig. 3 a basis, this n trap 90 and surrounds N-shaped doped region 11 ' and p-type drift region 12 ' in p-type substrate (or epitaxial loayer) 10, the identical but doping type of all the other each several part structures becomes on the contrary, then formed the embodiment two of the application's p-type LDMOS device, shown in Fig. 3 b.
Increase n trap 90 on Fig. 3 a basis, this n trap 90 is in p-type substrate (or epitaxial loayer) 10, and encirclement p-type doped region 11 and N-shaped drift region 12, all the other each several part structures are identical, doping type is also identical, has then formed the embodiment two of N-shaped LDMOS device of the application's channel isolation type, and is not shown.
In above-described embodiment two, represented that exemplarily N-shaped epitaxial loayer 80 is divided into three section 81,82,83, its quantity can be reduced to two sections or expand to more than four sections.
The described LDMOS device of the application on the drift region near the newly-increased at least one extension drift region with the identical doping type in drift region of raceway groove one side, these two parts have formed the drift region (for distinguish for the purpose of, be called work drift region) of LDMOS device when work jointly.In-situ doped epitaxial growth technology is preferably adopted in described extension drift region, thereby the impurity that can guarantee this extension drift region can not increase the doping content of the drift region of its below, especially can not increase not the doping content of the drift region that is covered by epitaxial loayer, therefore can not increase the ionization by collision intensity of drift region.And described epitaxial loayer only is distributed in the top, drift region near raceway groove one side, and be not distributed in above the drift region of close drain terminal one side, by reasonably thickness and the doping content of selective epitaxy layer, can guarantee when drain terminal voltage progressively strengthens, before ionization by collision occurs, whole work drift region can all be exhausted, thereby the puncture voltage of retainer member is constant.Because the effective thickness of work drift region increases, and can effectively reduce the conducting resistance of device.Form if described epitaxial loayer is repeatedly epitaxial growth, then each epitaxially grown thickness and in-situ doped concentration all can be different.The closer to the epitaxial loayer of drain terminal, its thickness is less, and doping content is also lower, and this will all exhaust whole work drift region when work more effectively, realize when realizing high-breakdown-voltage and low on-resistance.
The below introduces its manufacture method take the N-shaped LDMOS device of the non-channel isolation type shown in Fig. 2 a as example:
The 1st step saw also Fig. 4 a, adopted ion implantation technology to form laterally adjacent p-type doped region 11 and N-shaped drift region 12 in p-type substrate 10.
The 2nd step saw also Fig. 4 b, thermal oxide growth or deposit one deck silica on silicon chip, deposit one deck polysilicon thereon, adopt photoetching and etching technics form gate oxide 13 and on polysilicon gate 14.One end of gate oxide 13 is on p-type doped region 11, and the other end is on N-shaped drift region 12, and namely it is across the line of demarcation of p-type doped region 11 and N-shaped drift region 12.
The 3rd step saw also Fig. 4 c, deposit one deck dielectric material on silicon chip, and for example silicon nitride adopts dry method to anti-carve technique and removes this layer dielectric material, thereby forms side wall 15 in the both sides of gate oxide 13 and polysilicon gate 14 by residual dielectric material.
Being close to side wall 15 in p-type doped region 11 adopts ion implantation technology to form N-shaped heavy doping source 19.Because stopping of side wall 15, N-shaped heavy doping source 19 is positioned at the centre position of p-type doped region 11 after annealing process, one end of gate oxide 13 is positioned on the N-shaped heavy doping source 19, and the part p-type doped region 11 between N-shaped heavy doping source 19 and the N-shaped drift region 12 and under gate oxide 13 is exactly the raceway groove of LDMOS device.
That end away from gate oxide 13 in N-shaped drift region 12 adopts ion implantation technology to form N-shaped heavy doping drain terminal 20.
That end away from gate oxide 13 in p-type doped region 11 adopts ion implantation technology to form p-type heavy doping raceway groove exit 21.
The 4a step sees also Fig. 4 d, and dielectric layer deposited 16 on whole silicon chip, such as silica, silicon nitride, silicon oxynitride etc.Then adopt photoetching process on N-shaped drift region 12 near the position of side wall 15 (can be close to side wall 15, also can and side wall 15 between have a less segment distance) expose an extension window.Then in this extension window, adopt epitaxy technique to grow extension drift region 80.Remove at last dielectric layer 16, for example adopt wet corrosion technique.Has a larger segment distance between this extension drift region 80 and the N-shaped heavy doping drain terminal 20.
If want the N-shaped LDMOS device of the non-channel isolation type shown in the shop drawings 3a, the 4th step of said method changes into so:
In the 4a step, see also Fig. 4 d, deposit first medium layer 16 on whole silicon chip, such as silica, silicon nitride, silicon oxynitride etc.Then adopt photoetching process on N-shaped drift region 12 near the position of side wall 15 (can be close to side wall 15, also can and side wall 15 between have a less segment distance) expose an extension window.Then in this extension window, adopt epitaxy technique to grow the first extension drift region 81.Remove at last first medium layer 16, for example adopt wet corrosion technique.Has a larger segment distance between this first extension drift region 81 and the N-shaped heavy doping drain terminal 20.
In the 4b step, see also Fig. 4 e, deposit second medium layer 17 on whole silicon chip, such as silica, silicon nitride, silicon oxynitride etc.Then adopt photoetching process on N-shaped drift region 12 near the position of the first extension drift region 81 (can be close to the first extension drift region 81, also can and the first extension drift region 81 between have a less segment distance) expose an extension window.Then in this extension window, adopt epitaxy technique to grow the second extension drift region 82.Remove at last second medium layer 17, for example adopt wet corrosion technique.Has a larger segment distance between this second extension drift region 82 and the N-shaped heavy doping drain terminal 20.
In the 4c step, see also Fig. 4 f, deposit the 3rd dielectric layer 18 on whole silicon chip, such as silica, silicon nitride, silicon oxynitride etc.Then adopt photoetching process on N-shaped drift region 12 near the position of the second extension drift region 82 (can be close to the second extension drift region 82, also can and the second extension drift region 82 between have a less segment distance) expose an extension window.Then in this extension window, adopt epitaxy technique to grow the 3rd extension drift region 83.Remove at last the 3rd dielectric layer 18, for example adopt wet corrosion technique.Has a larger segment distance between the 3rd extension drift region 83 and the N-shaped heavy doping drain terminal 20.
Above-mentioned 4a to the 4c step, it can do corresponding increase and decrease according to the composing quantity difference of epitaxial loayer in order to form an example of the extension drift region that is comprised of three parts.
After the Implantation in described the 1st step of method, the 3rd step annealing process is arranged.The 1st step was preferably the high temperature furnace annealing process, and the 3rd step was preferably rapid thermal annealing (RTA) technique.
Described the 4th step (or 4a to 4c goes on foot) of method also can be put into before the 3rd step or intert and carry out between the 3rd step.If when forming the extension drift region, do not have side wall 15 as reference, then need guarantee this extension drift region apart from raceway groove one segment distance, so that make gate oxide cross over the line of demarcation of raceway groove and drift region.
The 1st step of said method is changed into: in p-type substrate (or epitaxial loayer) 10, adopt first ion implantation technology to form n trap 90(shown in Fig. 3 b), should will adopt ion implantation technology to form laterally adjacent N-shaped doped region 11 ' and p-type drift region 12 ' in the n trap 90 again.Each step is identical later on, but each several part doping type and Implantation type opposite then are the manufacture methods of the application's p-type LDMOS device.
The 1st step of said method is changed into: in p-type substrate (or epitaxial loayer) 10, adopt first ion implantation technology to form n trap (not shown), in the n trap, adopt again ion implantation technology to form laterally adjacent p-type doped region 11 and N-shaped drift region 12.Later on each step is identical, and the each several part doping type is also identical with the Implantation type, then is the manufacture method of N-shaped LDMOS device of the application's channel isolation type.
Be the application's preferred embodiment only below, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.All within the application's spirit and principle, any modification of doing, be equal to replacement, improvement etc., all should be included within the application's the protection range.

Claims (10)

1. LDMOS device, the drift region that between raceway groove and drain terminal, has the second conduction type, the upper surface level of described drift region, it is characterized in that, the extension drift region that has at least one the second conduction type on described drift region, described extension drift region only are distributed in described drift region near the top of raceway groove one side;
Described the first conduction type, the second conduction type are respectively p-type, N-shaped; Perhaps opposite.
2. LDMOS device according to claim 1 is characterized in that, the upper surface of described extension drift region is horizontal.
3. LDMOS device according to claim 1 is characterized in that, the upper surface of described extension drift region is stepped, and on the direction from the raceway groove to the drain terminal thickness monotone decreasing of this epitaxial loayer.
4. according to claim 2 or 3 described LDMOS devices, it is characterized in that described extension drift region is one or more; When having polylith extension drift region, between them or be close to, perhaps at a distance of a segment distance.
5. LDMOS device according to claim 1 is characterized in that, the doping content of described extension drift region is 0.5 times～2 times of doping content of drift region.
6. LDMOS device according to claim 1 is characterized in that, the thickness of described extension drift region is 0.1 times～1 times of drift region thickness.
7. the manufacture method of LDMOS device as claimed in claim 1 is characterized in that, comprises the steps:
In the 1st step, in the substrate of the first conduction type, adopt ion implantation technology to form the doped region of the first laterally adjacent conduction type and the drift region of the second conduction type;
The 2nd step, silicon chip form gate oxide and on polysilicon gate, gate oxide is across the line of demarcation of doped region and drift region;
In the 3rd step, form side wall in the both sides of gate oxide and polysilicon gate;
Form the heavy doping source of the second conduction type in the centre position of doped region, between heavy doping source and the drift region and the part doped region of adjacent gate oxide be exactly the raceway groove of LDMOS device;
Form the heavy doping drain terminal of the second conduction type away from that end of gate oxide in the drift region;
In doped region, form the heavy doping raceway groove exit of the first conduction type away from that end of gate oxide;
The 4th step, at silicon chip surface deposit one deck dielectric layer, then adopt photoetching process to expose the extension window in described drift region near the side wall place, and in this extension window, grow the extension drift region of the second conduction type with extension and in-situ doped technique, remove at last dielectric layer;
Described the first conduction type, the second conduction type are respectively p-type, N-shaped; Perhaps opposite.
8. the manufacture method of LDMOS device according to claim 7 is characterized in that, described the 4th step of method changes into:
The 4a step, at silicon chip surface deposit n dielectric layer, then adopt photoetching process to expose n extension window in described drift region near the side wall place, and in this n extension window, grow n extension drift region with extension and in-situ doped technique, remove at last the n dielectric layer; Described n is natural number;
Repeat 4a step 1 time to repeatedly, each formed extension drift region all on the next door of upper once formed extension drift region, perhaps is close to, perhaps at a distance of a segment distance.
9. the manufacture method of LDMOS device according to claim 7, it is characterized in that, described the 1st step of method is changed into: in the substrate of the first conduction type, adopt ion implantation technology to form the trap of the second conduction type, in this trap, form the doped region of the first laterally adjacent conduction type and the drift region of the second conduction type with ion implantation technology; All the other each steps are constant.
10. the manufacture method of LDMOS device according to claim 7, it is characterized in that, described the 1st step of method is changed into: in the substrate of the first conduction type, adopt ion implantation technology to form the trap of the second conduction type, in this trap, form the doped region of the second laterally adjacent conduction type and the drift region of the first conduction type with ion implantation technology; Identical but the doping type of all the other each steps becomes on the contrary.
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CN104518027A (en) * 2014-06-13 2015-04-15 上海华虹宏力半导体制造有限公司 LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
CN109244142A (en) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 A kind of LDMOS and its manufacturing method
CN111725070A (en) * 2020-07-16 2020-09-29 杰华特微电子（杭州）有限公司 Manufacturing method of semiconductor device and semiconductor device
CN115881778A (en) * 2023-01-19 2023-03-31 北京智芯微电子科技有限公司 Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit

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CN101707205A (en) * 2009-11-27 2010-05-12 南京邮电大学 Transverse power transistor with inclined surface drift region

Cited By (4)

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CN104518027A (en) * 2014-06-13 2015-04-15 上海华虹宏力半导体制造有限公司 LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
CN109244142A (en) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 A kind of LDMOS and its manufacturing method
CN111725070A (en) * 2020-07-16 2020-09-29 杰华特微电子（杭州）有限公司 Manufacturing method of semiconductor device and semiconductor device
CN115881778A (en) * 2023-01-19 2023-03-31 北京智芯微电子科技有限公司 Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit

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